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Smith" , Jiqian Chen , Huang Rui Subject: [XEN PATCH v16 1/3] x86/irq: allow setting IRQ permissions from GSI instead of pIRQ Date: Mon, 30 Sep 2024 11:42:48 +0800 Message-ID: <20240930034250.2682265-2-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240930034250.2682265-1-Jiqian.Chen@amd.com> References: <20240930034250.2682265-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBD:EE_|LV8PR12MB9083:EE_ X-MS-Office365-Filtering-Correlation-Id: c57dfba8-9e00-4837-707d-08dce10217c9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?eZBKTd1vpfklnL2GnVSUqsEFC11Fx+lvg19jwmwxfG8+es9ci1rh4owrVkYg?= =?us-ascii?Q?Ur1wRZ1Gcv0XWYAdquZ5S+lMNgAfuGN32fMt2oTe/JPOdFzMAUK8mmNkPWX/?= =?us-ascii?Q?hv/AuIjg026XviFiffBtn6X3ss3qDR2PtRa0ZbImU5BJ+RpLlYuDrTmliC/C?= =?us-ascii?Q?rrzFDjXJ6eLR6fVf/68ICet6jx9F2P060icThYpVUoY/4fq9wmGzlt95m6Y3?= =?us-ascii?Q?jFJ6a+VPLXOA3Sl3ZbAR/th/0tRR4FzUTDhdMFIHgaWSV54qpcGVKhELm06m?= =?us-ascii?Q?oQ8eG/i7yZbzTNUGzWgGWcA1p/z3iKhFTE/18tC8NPTaUodR0E6dze3Ma5Gs?= =?us-ascii?Q?ViDLYWJm3OMV5g4ND0ldk2GoScy7hX6DGk9Sd2SRdUYhDBl95Wf4mchmDLJ3?= =?us-ascii?Q?P0Du2TMvZy5GztZRqYYSxij/SNdjgPeBluf5qAvIuHLG80CvL5qby94qzu7o?= =?us-ascii?Q?Nt+lOISxXStHVCN0iC5yn+AEiPTqEuHJiYpEBwJG3KKQZPFeqB9F3gHHz1B3?= =?us-ascii?Q?v51JiRye+xurzeZwuqzDU/UrS+eYzw0dJJZ+43eDELESQ9KZs0vYtUvx8igM?= =?us-ascii?Q?wHqD0uhGdUXpHmrH9aG6rbK1ii5kcBsP/eHYOZJ763bBSv1BWAM+AfNHKLVQ?= =?us-ascii?Q?4p2DNbf1mdWsqwp7PFRa2mw9LKpV2y8YOMc3vSb6ZaXtBMtai3fxMITtnzmt?= =?us-ascii?Q?+mMwEekwnTDc4/zAWTMzZqyNE7R0k1AT7tTOVx8S7IedlnHtwZ8uvFbJJ5Zs?= =?us-ascii?Q?B0vUMHx+F2MJGtFPVRBvO/s3zDABKAcilFI4+HQQYkcMvoldQKtnUQlM+F0J?= =?us-ascii?Q?Xdlch5cUH7ZRczJhL513p4rdAIBqhAkjGOI1NnTlJua3HpdKK3swO58iqaR+?= =?us-ascii?Q?otbQyYP7sv8utOGT8SChRbLyzws2NRxwkI5KLJS70E/NlByVMCjYPewrdLHY?= =?us-ascii?Q?42Gs1BBLLDRDx8b+ku3VJETownphbZdHhfCRi6AbVy8dhwKgPn52of1B8IyW?= =?us-ascii?Q?g8SamXGdtwCEgz4lC+iogtcWT/n5l0BVns9scJNRyG8r6q2FWEc2svTz+z0f?= =?us-ascii?Q?CGcNFne2EzCuH4l49YRw1MtFN09L9pYjiRWJ4Vvix+hZyJE+T2uAIngFGJC1?= =?us-ascii?Q?QZAdn3TjSgihPn5pQAfM9d4L0HL9bqGp7n2BDvTM+8uLvHHJpqZd8cUMvghP?= =?us-ascii?Q?xlLESYEHhm45162vQCZFkRWbhcv9UmNNlVSkyCR9Oc8BzAoMRe+nIpoDKDE0?= =?us-ascii?Q?lwZAjpwrpunKYy8LjcuBoZOFIkjLPb3bwt0DFKneuZMb5eBu4LzmEa0y+LFJ?= =?us-ascii?Q?TpUpYp76bmcSk+23/ckd16P6iRkOxCEyvheT00O1lS6JvXYXNV6fj/1/8hcU?= =?us-ascii?Q?hXZfjXlL9zcODH9hg8j86rL4+KE4FlaVQJZgCGI1mWzf5CzuJnOMpR+Mo2Cu?= =?us-ascii?Q?SlP8F7Q3lMwEtbQ+dPRJ8f9JGDfdL0gD?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2024 03:43:48.4404 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c57dfba8-9e00-4837-707d-08dce10217c9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9083 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1727667872335116600 Content-Type: text/plain; charset="utf-8" Some domains are not aware of the pIRQ abstraction layer that maps interrupt sources into Xen space interrupt numbers. pIRQs values are only exposed to domains that have the option to route physical interrupts over event channels. This creates issues for PCI-passthrough from a PVH domain, as some of the passthrough related hypercalls use pIRQ as references to physical interrupts on the system. One of such interfaces is XEN_DOMCTL_irq_permission, used to grant or revoke access to interrupts, takes a pIRQ as the reference to the interrupt to be adjusted. Since PVH doesn't manage interrupts in terms of pIRQs, introduce a new hypercall that allows setting interrupt permissions based on GSI value rather than pIRQ. Note the GSI hypercall parameters is translated to an IRQ value (in case there are ACPI overrides) before doing the checks. Signed-off-by: Jiqian Chen Signed-off-by: Huang Rui Signed-off-by: Jiqian Chen Reviewed-by: Daniel P. Smith Acked-by: Jan Beulich --- v15->v16 changes: Change the code "ret =3D irq =3D gsi_2_irq(gsi);" to be MISRA compliant. Add Reviewed-by of Daniel P. Smith v13->v15 changes: Change to use the commit message wrote by Roger. Change the code comment from "Check all bits are zero except lowest bit" to= "Check only valid bits are set". Change the end return sentence of gsi_2_irq to "return irq ?: -EINVAL;" to = preserve the error code from apic_pin_2_gsi_irq(). v12->v13 changes: For struct xen_domctl_gsi_permission, rename "access_flag" to "flags", chan= ge its type from uint8_t to uint32_t, delete "pad", add XEN_DOMCTL_GSI_REVO= KE and XEN_DOMCTL_GSI_GRANT macros. Move "gsi > highest_gsi()" into function gsi_2_irq. Modify parameter gsi in function gsi_2_irq and mp_find_ioapic to unsigned i= nt type. Delete unnecessary spaces and brackets around "~XEN_DOMCTL_GSI_ACTION_MASK". Delete unnecessary goto statements and change to direct break. Add description in commit message to explain how gsi to irq isconverted. v11->v12 changes: Change nr_irqs_gsi to highest_gsi() to check gsi boundary, then need to rem= ove "__init" of highest_gsi function. Change the check of irq boundary from <0 to <=3D0, and remove unnecessary s= pace. Add #define XEN_DOMCTL_GSI_PERMISSION_MASK 1 to get lowest bit. v10->v11 changes: Extracted from patch#5 of v10 into a separate patch. Add non-zero judgment for other bits of allow_access. Delete unnecessary judgment "if ( is_pv_domain(currd) || has_pirq(currd) )". Change the error exit path identifier "out" to "gsi_permission_out". Use ARRAY_SIZE() instead of open coed. v9->v10 changes: Modified the commit message to further describe the purpose of adding XEN_D= OMCTL_gsi_permission. Added a check for all zeros in the padding field in XEN_DOMCTL_gsi_permissi= on, and used currd instead of current->domain. In the function gsi_2_irq, apic_pin_2_gsi_irq was used instead of the origi= nal new code, and error handling for irq0 was added. Deleted the extra spaces in the upper and lower lines of the struct xen_dom= ctl_gsi_permission definition. v8->v9 changes: Change the commit message to describe more why we need this new hypercall. Add comment above "if ( is_pv_domain(current->domain) || has_pirq(current->= domain) )" to explain why we need this check. Add gsi_2_irq to transform gsi to irq, instead of considering gsi =3D=3D ir= q. Add explicit padding to struct xen_domctl_gsi_permission. v5->v8 changes: Nothing. v4->v5 changes: New implementation to add new hypercall XEN_DOMCTL_gsi_permission to grant = gsi. --- xen/arch/x86/domctl.c | 32 ++++++++++++++++++++++++++++++ xen/arch/x86/include/asm/io_apic.h | 2 ++ xen/arch/x86/io_apic.c | 19 ++++++++++++++++++ xen/arch/x86/mpparse.c | 7 +++---- xen/include/public/domctl.h | 10 ++++++++++ xen/xsm/flask/hooks.c | 1 + 6 files changed, 67 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index 68b5b46d1a83..d9e8252d74d4 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -36,6 +36,7 @@ #include #include #include +#include =20 static int update_domain_cpu_policy(struct domain *d, xen_domctl_cpu_policy_t *xdpc) @@ -237,6 +238,37 @@ long arch_do_domctl( break; } =20 + case XEN_DOMCTL_gsi_permission: + { + int irq; + unsigned int gsi =3D domctl->u.gsi_permission.gsi; + uint32_t flags =3D domctl->u.gsi_permission.flags; + + /* Check only valid bits are set */ + ret =3D -EINVAL; + if ( flags & ~XEN_DOMCTL_GSI_ACTION_MASK ) + break; + + irq =3D gsi_2_irq(gsi); + if ( irq <=3D 0 ) + { + ret =3D irq ?: -EACCES; + break; + } + + ret =3D -EPERM; + if ( !irq_access_permitted(currd, irq) || + xsm_irq_permission(XSM_HOOK, d, irq, flags) ) + break; + + if ( flags ) + ret =3D irq_permit_access(d, irq); + else + ret =3D irq_deny_access(d, irq); + + break; + } + case XEN_DOMCTL_getpageframeinfo3: { unsigned int num =3D domctl->u.getpageframeinfo3.num; diff --git a/xen/arch/x86/include/asm/io_apic.h b/xen/arch/x86/include/asm/= io_apic.h index 78268ea8f666..62456806c7af 100644 --- a/xen/arch/x86/include/asm/io_apic.h +++ b/xen/arch/x86/include/asm/io_apic.h @@ -213,5 +213,7 @@ unsigned highest_gsi(void); =20 int ioapic_guest_read( unsigned long physbase, unsigned int reg, u32 *pval= ); int ioapic_guest_write(unsigned long physbase, unsigned int reg, u32 val); +int mp_find_ioapic(unsigned int gsi); +int gsi_2_irq(unsigned int gsi); =20 #endif diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c index 772700584639..e40d2f7dbd75 100644 --- a/xen/arch/x86/io_apic.c +++ b/xen/arch/x86/io_apic.c @@ -955,6 +955,25 @@ static int pin_2_irq(int idx, int apic, int pin) return irq; } =20 +int gsi_2_irq(unsigned int gsi) +{ + int ioapic, irq; + unsigned int pin; + + if ( gsi > highest_gsi() ) + return -ERANGE; + + ioapic =3D mp_find_ioapic(gsi); + if ( ioapic < 0 ) + return -EINVAL; + + pin =3D gsi - io_apic_gsi_base(ioapic); + + irq =3D apic_pin_2_gsi_irq(ioapic, pin); + + return irq ?: -EINVAL; +} + static inline int IO_APIC_irq_trigger(int irq) { int apic, idx, pin; diff --git a/xen/arch/x86/mpparse.c b/xen/arch/x86/mpparse.c index 306d8ed97a83..e13b83bbe9dd 100644 --- a/xen/arch/x86/mpparse.c +++ b/xen/arch/x86/mpparse.c @@ -842,8 +842,7 @@ static struct mp_ioapic_routing { } mp_ioapic_routing[MAX_IO_APICS]; =20 =20 -static int mp_find_ioapic ( - int gsi) +int mp_find_ioapic(unsigned int gsi) { unsigned int i; =20 @@ -854,7 +853,7 @@ static int mp_find_ioapic ( return i; } =20 - printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); + printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %u\n", gsi); =20 return -1; } @@ -915,7 +914,7 @@ void __init mp_register_ioapic ( return; } =20 -unsigned __init highest_gsi(void) +unsigned highest_gsi(void) { unsigned x, res =3D 0; for (x =3D 0; x < nr_ioapics; x++) diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h index 2a49fe46ce25..e1028fc524cf 100644 --- a/xen/include/public/domctl.h +++ b/xen/include/public/domctl.h @@ -464,6 +464,14 @@ struct xen_domctl_irq_permission { uint8_t pad[3]; }; =20 +/* XEN_DOMCTL_gsi_permission */ +struct xen_domctl_gsi_permission { + uint32_t gsi; +#define XEN_DOMCTL_GSI_REVOKE 0 +#define XEN_DOMCTL_GSI_GRANT 1 +#define XEN_DOMCTL_GSI_ACTION_MASK 1 + uint32_t flags; +}; =20 /* XEN_DOMCTL_iomem_permission */ struct xen_domctl_iomem_permission { @@ -1306,6 +1314,7 @@ struct xen_domctl { #define XEN_DOMCTL_get_paging_mempool_size 85 #define XEN_DOMCTL_set_paging_mempool_size 86 #define XEN_DOMCTL_dt_overlay 87 +#define XEN_DOMCTL_gsi_permission 88 #define XEN_DOMCTL_gdbsx_guestmemio 1000 #define XEN_DOMCTL_gdbsx_pausevcpu 1001 #define XEN_DOMCTL_gdbsx_unpausevcpu 1002 @@ -1328,6 +1337,7 @@ struct xen_domctl { struct xen_domctl_setdomainhandle setdomainhandle; struct xen_domctl_setdebugging setdebugging; struct xen_domctl_irq_permission irq_permission; + struct xen_domctl_gsi_permission gsi_permission; struct xen_domctl_iomem_permission iomem_permission; struct xen_domctl_ioport_permission ioport_permission; struct xen_domctl_hypercall_init hypercall_init; diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c index 278ad38c2af3..dfa23738cd8a 100644 --- a/xen/xsm/flask/hooks.c +++ b/xen/xsm/flask/hooks.c @@ -695,6 +695,7 @@ static int cf_check flask_domctl(struct domain *d, unsi= gned int cmd, case XEN_DOMCTL_shadow_op: case XEN_DOMCTL_ioport_permission: case XEN_DOMCTL_ioport_mapping: + case XEN_DOMCTL_gsi_permission: #endif #ifdef CONFIG_HAS_PASSTHROUGH /* --=20 2.34.1