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From: "Andrei Cherechesu (OSS)" To: xen-devel@lists.xenproject.org Cc: S32@nxp.com, andrei.cherechesu@oss.nxp.com, Andrei Cherechesu , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Jan Beulich Subject: [PATCH v1 1/5] xen/arm: Add NXP LINFlexD UART Driver Date: Tue, 10 Sep 2024 17:34:07 +0300 Message-ID: <20240910143411.178704-2-andrei.cherechesu@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240910143411.178704-1-andrei.cherechesu@oss.nxp.com> References: <20240910143411.178704-1-andrei.cherechesu@oss.nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AM0P190CA0019.EURP190.PROD.OUTLOOK.COM (2603:10a6:208:190::29) To PA4PR04MB9565.eurprd04.prod.outlook.com (2603:10a6:102:26b::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PA4PR04MB9565:EE_|AS8PR04MB7557:EE_ X-MS-Office365-Filtering-Correlation-Id: c1152014-a353-4ce6-6f1b-08dcd1a5b011 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|52116014|376014|38350700014; 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charset="utf-8" From: Andrei Cherechesu The LINFlexD UART is an UART controller available on NXP S32 processors family targeting automotive (for example: S32G2, S32G3, S32R). S32G3 Reference Manual: https://www.nxp.com/webapp/Download?colCode=3DRMS32G3. Signed-off-by: Andrei Cherechesu Signed-off-by: Peter van der Perk --- xen/arch/arm/include/asm/linflex-uart.h | 62 ++++ xen/drivers/char/Kconfig | 8 + xen/drivers/char/Makefile | 1 + xen/drivers/char/linflex-uart.c | 365 ++++++++++++++++++++++++ 4 files changed, 436 insertions(+) create mode 100644 xen/arch/arm/include/asm/linflex-uart.h create mode 100644 xen/drivers/char/linflex-uart.c diff --git a/xen/arch/arm/include/asm/linflex-uart.h b/xen/arch/arm/include= /asm/linflex-uart.h new file mode 100644 index 0000000000..62dc54d155 --- /dev/null +++ b/xen/arch/arm/include/asm/linflex-uart.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * xen/arch/arm/include/asm/linflex-uart.h + * + * Common constant definition between early printk and the UART driver + * for NXP LINFlexD UART. + * + * Andrei Cherechesu + * Copyright 2018, 2021, 2024 NXP + */ + +#ifndef __ASM_ARM_LINFLEX_UART_H +#define __ASM_ARM_LINFLEX_UART_H + +/* 32-bit register offsets */ +#define LINCR1 (0x0) +#define LINIER (0x4) +#define LINSR (0x8) +#define UARTCR (0x10) +#define UARTSR (0x14) +#define LINFBRR (0x24) +#define LINIBRR (0x28) +#define BDRL (0x38) +#define BDRM (0x3C) +#define UARTPTO (0x50) + +#define LINCR1_INIT BIT(0, U) +#define LINCR1_MME BIT(4, U) +#define LINCR1_BF BIT(7, U) + +#define LINSR_LINS GENMASK(15, 12) +#define LINSR_LINS_INIT BIT(12, U) + +#define LINIER_DRIE BIT(2, U) +#define LINIER_DTIE BIT(1, U) + +#define UARTCR_UART BIT(0, U) +#define UARTCR_WL0 BIT(1, U) +#define UARTCR_PC0 BIT(3, U) +#define UARTCR_TXEN BIT(4, U) +#define UARTCR_RXEN BIT(5, U) +#define UARTCR_PC1 BIT(6, U) +#define UARTCR_TFBM BIT(8, U) +#define UARTCR_RFBM BIT(9, U) +#define UARTCR_RDFLRFC GENMASK(12, 10) +#define UARTCR_TDFLTFC GENMASK(15, 13) +#define UARTCR_ROSE BIT(23, U) +#define UARTCR_OSR GENMASK(27, 24) + +#define UARTSR_DTFTFF BIT(1, U) +#define UARTSR_DRFRFE BIT(2, U) + +#endif /* __ASM_ARM_LINFLEX_UART_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/drivers/char/Kconfig b/xen/drivers/char/Kconfig index 3f836ab301..e175d07c02 100644 --- a/xen/drivers/char/Kconfig +++ b/xen/drivers/char/Kconfig @@ -13,6 +13,14 @@ config HAS_CADENCE_UART This selects the Xilinx Zynq Cadence UART. If you have a Xilinx Zynq based board, say Y. =20 +config HAS_LINFLEX + bool "NXP LINFlexD UART driver" + default y + depends on ARM_64 + help + This selects the NXP LINFlexD UART. If you have an NXP S32G or S32R + based board, say Y. + config HAS_IMX_LPUART bool "i.MX LPUART driver" default y diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile index e7e374775d..d3b987da1d 100644 --- a/xen/drivers/char/Makefile +++ b/xen/drivers/char/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_HAS_SCIF) +=3D scif-uart.o obj-$(CONFIG_HAS_EHCI) +=3D ehci-dbgp.o obj-$(CONFIG_XHCI) +=3D xhci-dbc.o obj-$(CONFIG_HAS_IMX_LPUART) +=3D imx-lpuart.o +obj-$(CONFIG_HAS_LINFLEX) +=3D linflex-uart.o obj-$(CONFIG_ARM) +=3D arm-uart.o obj-y +=3D serial.o obj-$(CONFIG_XEN_GUEST) +=3D xen_pv_console.o diff --git a/xen/drivers/char/linflex-uart.c b/xen/drivers/char/linflex-uar= t.c new file mode 100644 index 0000000000..4ca8f732ae --- /dev/null +++ b/xen/drivers/char/linflex-uart.c @@ -0,0 +1,365 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * xen/drivers/char/linflex-uart.c + * + * Driver for NXP LINFlexD UART. + * + * Andrei Cherechesu + * Copyright 2018, 2021-2022, 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LINFLEX_CLK_FREQ (125000000) +#define LINFLEX_BAUDRATE (115200) +#define LINFLEX_LDIV_MULTIPLIER (16) + +static struct linflex_uart { + uint32_t baud, clock_hz; + uint32_t irq; + char __iomem *regs; + struct irqaction irqaction; + struct vuart_info vuart; +} linflex_com; + +static uint32_t linflex_uart_readl(struct linflex_uart *uart, uint32_t off) +{ + return readl(uart->regs + off); +} + +static void linflex_uart_writel(struct linflex_uart *uart, uint32_t off, + uint32_t val) +{ + writel(val, uart->regs + off); +} + +static void linflex_uart_writeb(struct linflex_uart *uart, uint32_t off, + uint8_t val) +{ + writeb(val, uart->regs + off); +} + +static uint32_t linflex_uart_get_osr(uint32_t uartcr) +{ + return (uartcr & UARTCR_OSR) >> 24; +} + +static uint32_t linflex_uart_tx_fifo_mode(struct linflex_uart *uart) +{ + return linflex_uart_readl(uart, UARTCR) & UARTCR_TFBM; +} + +static uint32_t linflex_uart_rx_fifo_mode(struct linflex_uart *uart) +{ + return linflex_uart_readl(uart, UARTCR) & UARTCR_RFBM; +} + +static uint32_t linflex_uart_ldiv_multiplier(struct linflex_uart *uart) +{ + uint32_t uartcr, mul =3D LINFLEX_LDIV_MULTIPLIER; + + uartcr =3D linflex_uart_readl(uart, UARTCR); + if ( uartcr & UARTCR_ROSE ) + mul =3D linflex_uart_get_osr(uartcr); + + return mul; +} + +static void linflex_uart_flush(struct serial_port *port) +{ + struct linflex_uart *uart =3D port->uart; + + if ( linflex_uart_tx_fifo_mode(uart) ) + while ( linflex_uart_readl(uart, UARTCR) & UARTCR_TDFLTFC ); + cpu_relax(); + + if ( linflex_uart_rx_fifo_mode(uart) ) + while ( linflex_uart_readl(uart, UARTCR) & UARTCR_RDFLRFC ); + cpu_relax(); +} + +static void __init linflex_uart_init_preirq(struct serial_port *port) +{ + struct linflex_uart *uart =3D port->uart; + uint32_t ibr, fbr, divisr, dividr, ctrl; + + /* Disable RX/TX before init mode */ + ctrl =3D linflex_uart_readl(uart, UARTCR); + ctrl &=3D ~(UARTCR_RXEN | UARTCR_TXEN); + linflex_uart_writel(uart, UARTCR, ctrl); + + /* + * Smoothen the transition from early_printk by waiting + * for all pending characters to transmit + */ + linflex_uart_flush(port); + + /* Init mode */ + ctrl =3D LINCR1_INIT; + linflex_uart_writel(uart, LINCR1, ctrl); + + /* Waiting for init mode entry */ + while ( (linflex_uart_readl(uart, LINSR) & LINSR_LINS) !=3D LINSR_LINS= _INIT ) + cpu_relax(); + + /* Set Master Mode */ + ctrl |=3D LINCR1_MME; + linflex_uart_writel(uart, LINCR1, ctrl); + + /* Provide data bits, parity, stop bit, etc */ + divisr =3D uart->clock_hz; + dividr =3D (uint32_t)(uart->baud * linflex_uart_ldiv_multiplier(uart)); + + ibr =3D (uint32_t)(divisr / dividr); + fbr =3D (uint32_t)((divisr % dividr) * 16 / dividr) & 0xF; + + linflex_uart_writel(uart, LINIBRR, ibr); + linflex_uart_writel(uart, LINFBRR, fbr); + + /* Set preset timeout register value */ + linflex_uart_writel(uart, UARTPTO, 0xF); + + /* Setting UARTCR[UART] bit is required for writing other bits in UART= CR */ + linflex_uart_writel(uart, UARTCR, UARTCR_UART); + + /* 8 bit data, no parity, UART mode, Buffer mode */ + linflex_uart_writel(uart, UARTCR, UARTCR_PC1 | UARTCR_PC0 | UARTCR_WL0= | + UARTCR_UART); + + /* end init mode */ + ctrl =3D linflex_uart_readl(uart, LINCR1); + ctrl &=3D ~LINCR1_INIT; + linflex_uart_writel(uart, LINCR1, ctrl); + + /* Enable RX/TX after exiting init mode */ + ctrl =3D linflex_uart_readl(uart, UARTCR); + ctrl |=3D UARTCR_RXEN | UARTCR_TXEN; + linflex_uart_writel(uart, UARTCR, ctrl); +} + +static void linflex_uart_interrupt(int irq, void *data) +{ + struct serial_port *port =3D data; + struct linflex_uart *uart =3D port->uart; + uint32_t sts; + + sts =3D linflex_uart_readl(uart, UARTSR); + + if ( sts & UARTSR_DRFRFE ) + serial_rx_interrupt(port); + + if ( sts & UARTSR_DTFTFF ) + serial_tx_interrupt(port); +} + +static void __init linflex_uart_init_postirq(struct serial_port *port) +{ + struct linflex_uart *uart =3D port->uart; + uint32_t temp; + + uart->irqaction.handler =3D linflex_uart_interrupt; + uart->irqaction.name =3D "linflex_uart"; + uart->irqaction.dev_id =3D port; + + if ( setup_irq(uart->irq, 0, &uart->irqaction) !=3D 0 ) + { + dprintk(XENLOG_ERR, "Failed to allocate linflex_uart IRQ %d\n", + uart->irq); + return; + } + + /* Enable interrupts */ + temp =3D linflex_uart_readl(uart, LINIER); + temp |=3D (LINIER_DRIE | LINIER_DTIE); + linflex_uart_writel(uart, LINIER, temp); + dprintk(XENLOG_DEBUG, "IRQ %d enabled\n", uart->irq); +} + +static int linflex_uart_tx_ready(struct serial_port *port) +{ + struct linflex_uart *uart =3D port->uart; + + if ( linflex_uart_tx_fifo_mode(uart) ) + return (linflex_uart_readl(uart, UARTSR) & UARTSR_DTFTFF) =3D=3D 0= ? 1 : 0; + + /* + * Buffer Mode =3D> TX is waited to be ready after sending a char, + * so we can assume it is always ready before. + */ + return 1; +} + +static void linflex_uart_putc(struct serial_port *port, char c) +{ + struct linflex_uart *uart =3D port->uart; + uint32_t uartsr; + + if ( c =3D=3D '\n' ) + linflex_uart_putc(port, '\r'); + + linflex_uart_writeb(uart, BDRL, c); + + /* Buffer Mode */ + if ( !linflex_uart_tx_fifo_mode(uart) ) + { + while ( (linflex_uart_readl(uart, UARTSR) & UARTSR_DTFTFF) =3D=3D = 0 ) + cpu_relax(); + + uartsr =3D linflex_uart_readl(uart, UARTSR) | (UARTSR_DTFTFF); + linflex_uart_writel(uart, UARTSR, uartsr); + } +} + +static int linflex_uart_getc(struct serial_port *port, char *pc) +{ + struct linflex_uart *uart =3D port->uart; + uint32_t ch, uartsr, rx_fifo_mode; + + rx_fifo_mode =3D linflex_uart_rx_fifo_mode(uart); + + if ( rx_fifo_mode ) + while ( linflex_uart_readl(uart, UARTSR) & UARTSR_DRFRFE ) + cpu_relax(); + else + while ( !(linflex_uart_readl(uart, UARTSR) & UARTSR_DRFRFE) ) + cpu_relax(); + + ch =3D linflex_uart_readl(uart, BDRM); + *pc =3D ch & 0xff; + + if ( !rx_fifo_mode ) { + uartsr =3D linflex_uart_readl(uart, UARTSR) | UARTSR_DRFRFE; + linflex_uart_writel(uart, UARTSR, uartsr); + } + + return 1; +} + +static int __init linflex_uart_irq(struct serial_port *port) +{ + struct linflex_uart *uart =3D port->uart; + + return ((uart->irq > 0) ? uart->irq : -1); +} + +static const struct vuart_info *linflex_uart_vuart_info( + struct serial_port *port) +{ + struct linflex_uart *uart =3D port->uart; + + return &uart->vuart; +} + +static void linflex_uart_start_tx(struct serial_port *port) +{ + struct linflex_uart *uart =3D port->uart; + uint32_t temp; + + temp =3D linflex_uart_readl(uart, LINIER); + linflex_uart_writel(uart, LINIER, temp | LINIER_DTIE); +} + +static void linflex_uart_stop_tx(struct serial_port *port) +{ + struct linflex_uart *uart =3D port->uart; + uint32_t temp; + + temp =3D linflex_uart_readl(uart, LINIER); + temp &=3D ~(LINIER_DTIE); + linflex_uart_writel(uart, LINIER, temp); +} + +static struct uart_driver __read_mostly linflex_uart_driver =3D { + .init_preirq =3D linflex_uart_init_preirq, + .init_postirq =3D linflex_uart_init_postirq, + .tx_ready =3D linflex_uart_tx_ready, + .putc =3D linflex_uart_putc, + .flush =3D linflex_uart_flush, + .getc =3D linflex_uart_getc, + .irq =3D linflex_uart_irq, + .start_tx =3D linflex_uart_start_tx, + .stop_tx =3D linflex_uart_stop_tx, + .vuart_info =3D linflex_uart_vuart_info, +}; + +static int __init linflex_uart_init(struct dt_device_node *dev, const void= *data) +{ + const char *config =3D data; + struct linflex_uart *uart; + paddr_t addr, size; + int res; + + if ( strcmp(config, "") ) + printk("WARNING: UART configuration is not supported\n"); + + uart =3D &linflex_com; + + res =3D dt_device_get_paddr(dev, 0, &addr, &size); + if ( res ) + { + printk("linflex-uart: Unable to retrieve the base address of the U= ART\n"); + return res; + } + + res =3D platform_get_irq(dev, 0); + if ( res < 0 ) + { + printk("linflex-uart: Unable to retrieve the IRQ\n"); + return -EINVAL; + } + uart->irq =3D res; + + uart->regs =3D ioremap_nocache(addr, size); + if ( !uart->regs ) + { + printk("linflex-uart: Unable to map the UART memory\n"); + return -ENOMEM; + } + + uart->clock_hz =3D LINFLEX_CLK_FREQ; + uart->baud =3D LINFLEX_BAUDRATE; + + uart->vuart.base_addr =3D addr; + uart->vuart.size =3D size; + uart->vuart.data_off =3D BDRL; + uart->vuart.status_off =3D UARTSR; + uart->vuart.status =3D UARTSR_DTFTFF; + + /* Register with generic serial driver */ + serial_register_uart(SERHND_DTUART, &linflex_uart_driver, uart); + + dt_device_set_used_by(dev, DOMID_XEN); + + return 0; +} + +static const struct dt_device_match linflex_uart_dt_compat[] __initconst = =3D +{ + DT_MATCH_COMPATIBLE("nxp,s32g2-linflexuart"), + DT_MATCH_COMPATIBLE("nxp,s32g3-linflexuart"), + DT_MATCH_COMPATIBLE("fsl,s32v234-linflexuart"), + { /* sentinel */ }, +}; + +DT_DEVICE_START(linflex_uart, "NXP LINFlexD UART", DEVICE_SERIAL) + .dt_match =3D linflex_uart_dt_compat, + .init =3D linflex_uart_init, +DT_DEVICE_END + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.45.2