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Mon, 02 Sep 2024 03:03:59 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel Subject: [PATCH 1/4] ARM/div: Drop __div64_fls() Date: Mon, 2 Sep 2024 11:03:52 +0100 Message-Id: <20240902100355.3032079-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240902100355.3032079-1-andrew.cooper3@citrix.com> References: <20240902100355.3032079-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1725271470577116600 Content-Type: text/plain; charset="utf-8" Following the improvements to Xen's bitops, fls() does constant propagation= in all cases. Use it, and drop the local opencoded helper. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Michal Orzel --- CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel ARM32 gets a very minor code generation improvement: xen.git/xen$ ../scripts/bloat-o-meter xen-syms-arm32-{before,after} add/remove: 0/0 grow/shrink: 0/6 up/down: 0/-48 (-48) Function old new delta wallclock_time 288 280 -8 printk_start_of_line 560 552 -8 domain_vtimer_init 472 464 -8 do_settime 376 368 -8 burn_credits 760 752 -8 __printk_ratelimit 424 416 -8 But it's just a couple of operations improvement and no real change in code structure. I expect that the constant propagation being done through __builtin_clz(), rather than pure C, is giving the optimiser a bit more information to work with. This file also has an __GNUC__ < 4 case which seems ripe for removing... --- xen/arch/arm/include/asm/div64.h | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/xen/arch/arm/include/asm/div64.h b/xen/arch/arm/include/asm/di= v64.h index 0459d5cc0122..da1f1fcbd503 100644 --- a/xen/arch/arm/include/asm/div64.h +++ b/xen/arch/arm/include/asm/div64.h @@ -102,7 +102,7 @@ /* preserve low part of n for reminder computation */ \ __r =3D __n; \ /* determine number of bits to represent __b */ \ - __p =3D 1 << __div64_fls(__b); \ + __p =3D 1 << fls(__b); \ /* compute __m =3D ((__p << 64) + __b - 1) / __b */ \ __m =3D (~0ULL / __b) * __p; \ __m +=3D (((~0ULL % __b + 1) * __p) + __b - 1) / __b; \ @@ -150,8 +150,8 @@ __p /=3D (__m & -__m); \ __m /=3D (__m & -__m); \ } else { \ - __p >>=3D __div64_fls(__bits); \ - __m >>=3D __div64_fls(__bits); \ + __p >>=3D fls(__bits); \ + __m >>=3D fls(__bits); \ } \ /* No correction needed. */ \ __c =3D 0; \ @@ -217,18 +217,6 @@ __r; \ }) =20 -/* our own fls implementation to make sure constant propagation is fine */ -#define __div64_fls(bits) \ -({ \ - unsigned int __left =3D (bits), __nr =3D 0; \ - if (__left & 0xffff0000) __nr +=3D 16, __left >>=3D 16; \ - if (__left & 0x0000ff00) __nr +=3D 8, __left >>=3D 8; \ - if (__left & 0x000000f0) __nr +=3D 4, __left >>=3D 4; \ - if (__left & 0x0000000c) __nr +=3D 2, __left >>=3D 2; \ - if (__left & 0x00000002) __nr +=3D 1; \ - __nr; \ -}) - #endif /* GCC version */ =20 #endif /* BITS_PER_LONG */ --=20 2.39.2 From nobody Wed Jan 15 04:58:40 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Mon, 02 Sep 2024 03:04:00 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel Subject: [PATCH 2/4] ARM/vgic: Correct the expression for lr_all_full() Date: Mon, 2 Sep 2024 11:03:53 +0100 Message-Id: <20240902100355.3032079-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240902100355.3032079-1-andrew.cooper3@citrix.com> References: <20240902100355.3032079-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1725271464518116600 Content-Type: text/plain; charset="utf-8" The current expression hits UB with 31 LRs (shifting into the sign bit), and malfunctions with 32 LRs (shifting beyond the range of int). Swapping 1 for 1ULL fixes some of these, but still malfunctions at 64 LRs which is the architectural limit. Instead, shift -1ULL right in order to create the mask. Fixes: 596f885a3202 ("xen/arm: set GICH_HCR_UIE if all the LRs are in use") Signed-off-by: Andrew Cooper Reviewed-by: Michal Orzel --- CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel Found by code inspection while doing bitops work. I don't even know if there's a platform that really has 31 LRs, but the rest of Xen's code is written with the expectation that there may be 64. --- xen/arch/arm/gic-vgic.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 9aa245a36d98..3f14aab2efc7 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -16,7 +16,8 @@ #include #include =20 -#define lr_all_full() (this_cpu(lr_mask) =3D=3D ((1 << gic_get_nr_lrs()) -= 1)) +#define lr_all_full() \ + (this_cpu(lr_mask) =3D=3D (-1ULL >> (64 - gic_get_nr_lrs()))) =20 #undef GIC_DEBUG =20 --=20 2.39.2 From nobody Wed Jan 15 04:58:40 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Mon, 02 Sep 2024 03:04:01 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel Subject: [PATCH 3/4] ARM/vgic: Use for_each_set_bit() in gic_find_unused_lr() Date: Mon, 2 Sep 2024 11:03:54 +0100 Message-Id: <20240902100355.3032079-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240902100355.3032079-1-andrew.cooper3@citrix.com> References: <20240902100355.3032079-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1725271474560116600 Content-Type: text/plain; charset="utf-8" There are no bits set in lr_mask beyond nr_lrs, so when substituting bitmap_for_each() for for_each_set_bit(), we don't need to worry about the upper bound. However, the type of lr_mask does matter, so switch it to be uint64_t * and move unsigned long * override until the find_next_zero_bit() call. Move lr_val into a narrower scope and drop used_lr as it's declared by for_each_set_bit() itself. Drop the nr_lrs variable and use gic_get_nr_lrs() in the one location its n= ow used. It hides a triple pointer defererence, and while it may not be needed in the PRISTINE case, it certainly doesn't need to be live across the rest = of the function. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Michal Orzel --- CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel ARM64: $ ../scripts/bloat-o-meter xen-syms-arm64-{before,after} add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-28 (-28) Function old new delta gic_find_unused_lr.constprop 228 200 -28 inc -2 find_next_bit() ARM32: $ ../scripts/bloat-o-meter xen-syms-arm32-{before,after} add/remove: 0/0 grow/shrink: 1/0 up/down: 48/0 (48) Function old new delta gic_find_unused_lr 260 308 +48 because uint64_t, but -2 _find_{first,next}_bit_le() --- xen/arch/arm/gic-vgic.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 3f14aab2efc7..ea48c5375a91 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -102,25 +102,23 @@ static unsigned int gic_find_unused_lr(struct vcpu *v, struct pending_irq *p, unsigned int lr) { - unsigned int nr_lrs =3D gic_get_nr_lrs(); - unsigned long *lr_mask =3D (unsigned long *) &this_cpu(lr_mask); - struct gic_lr lr_val; + uint64_t *lr_mask =3D &this_cpu(lr_mask); =20 ASSERT(spin_is_locked(&v->arch.vgic.lock)); =20 if ( unlikely(test_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status)) ) { - unsigned int used_lr; - - bitmap_for_each ( used_lr, lr_mask, nr_lrs ) + for_each_set_bit ( used_lr, *lr_mask ) { + struct gic_lr lr_val; + gic_hw_ops->read_lr(used_lr, &lr_val); if ( lr_val.virq =3D=3D p->irq ) return used_lr; } } =20 - lr =3D find_next_zero_bit(lr_mask, nr_lrs, lr); + lr =3D find_next_zero_bit((unsigned long *)lr_mask, gic_get_nr_lrs(), = lr); =20 return lr; } --=20 2.39.2 From nobody Wed Jan 15 04:58:40 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Mon, 02 Sep 2024 03:04:02 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel Subject: [PATCH 4/4] ARM/vgic: Use for_each_set_bit() in vgic-mmio* Date: Mon, 2 Sep 2024 11:03:55 +0100 Message-Id: <20240902100355.3032079-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240902100355.3032079-1-andrew.cooper3@citrix.com> References: <20240902100355.3032079-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1725271466586116600 Content-Type: text/plain; charset="utf-8" These are all loops over a scalar value, and don't need to call general bit= op helpers behind the scenes. No functional change. Signed-off-by: Andrew Cooper --- CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel Slighly RFC. It's unclear whether len is the size of the register, or the size of the access. For sub-GPR accesses, won't the upper bits be clear anyway? If so, this can be simplified further. $ ../scripts/bloat-o-meter xen-syms-arm64-{before,after} add/remove: 0/0 grow/shrink: 2/5 up/down: 20/-140 (-120) Function old new delta vgic_mmio_write_spending 320 332 +12 vgic_mmio_write_cpending 368 376 +8 vgic_mmio_write_sactive 192 176 -16 vgic_mmio_write_cactive 192 176 -16 vgic_mmio_write_cenable 316 288 -28 vgic_mmio_write_senable 320 284 -36 vgic_mmio_write_sgir 344 300 -44 $ ../scripts/bloat-o-meter xen-syms-arm32-{before,after} add/remove: 0/0 grow/shrink: 0/4 up/down: 0/-32 (-32) Function old new delta vgic_mmio_write_sactive 204 200 -4 vgic_mmio_write_cpending 464 460 -4 vgic_mmio_write_cactive 204 200 -4 vgic_mmio_write_sgir 336 316 -20 --- xen/arch/arm/vgic/vgic-mmio-v2.c | 3 +-- xen/arch/arm/vgic/vgic-mmio.c | 36 +++++++++++++++++++++----------- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio= -v2.c index 670b335db2c3..42fac0403f07 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -90,7 +90,6 @@ static void vgic_mmio_write_sgir(struct vcpu *source_vcpu, unsigned int intid =3D val & GICD_SGI_INTID_MASK; unsigned long targets =3D (val & GICD_SGI_TARGET_MASK) >> GICD_SGI_TARGET_SHIFT; - unsigned int vcpu_id; =20 switch ( val & GICD_SGI_TARGET_LIST_MASK ) { @@ -108,7 +107,7 @@ static void vgic_mmio_write_sgir(struct vcpu *source_vc= pu, return; } =20 - bitmap_for_each ( vcpu_id, &targets, 8 ) + for_each_set_bit ( vcpu_id, (uint8_t)targets ) { struct vcpu *vcpu =3D d->vcpu[vcpu_id]; struct vgic_irq *irq =3D vgic_get_irq(d, vcpu, intid); diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index bd4caf7fc326..f7c336a238ab 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -69,9 +69,11 @@ void vgic_mmio_write_senable(struct vcpu *vcpu, unsigned long val) { uint32_t intid =3D VGIC_ADDR_TO_INTID(addr, 1); - unsigned int i; =20 - bitmap_for_each ( i, &val, len * 8 ) + if ( len < sizeof(val) ) + val &=3D (1UL << (len * 8)) - 1; + + for_each_set_bit ( i, val ) { struct vgic_irq *irq =3D vgic_get_irq(vcpu->domain, vcpu, intid + = i); unsigned long flags; @@ -114,9 +116,11 @@ void vgic_mmio_write_cenable(struct vcpu *vcpu, unsigned long val) { uint32_t intid =3D VGIC_ADDR_TO_INTID(addr, 1); - unsigned int i; =20 - bitmap_for_each ( i, &val, len * 8 ) + if ( len < sizeof(val) ) + val &=3D (1UL << (len * 8)) - 1; + + for_each_set_bit ( i, val ) { struct vgic_irq *irq; unsigned long flags; @@ -182,11 +186,13 @@ void vgic_mmio_write_spending(struct vcpu *vcpu, unsigned long val) { uint32_t intid =3D VGIC_ADDR_TO_INTID(addr, 1); - unsigned int i; unsigned long flags; irq_desc_t *desc; =20 - bitmap_for_each ( i, &val, len * 8 ) + if ( len < sizeof(val) ) + val &=3D (1UL << (len * 8)) - 1; + + for_each_set_bit ( i, val ) { struct vgic_irq *irq =3D vgic_get_irq(vcpu->domain, vcpu, intid + = i); =20 @@ -230,11 +236,13 @@ void vgic_mmio_write_cpending(struct vcpu *vcpu, unsigned long val) { uint32_t intid =3D VGIC_ADDR_TO_INTID(addr, 1); - unsigned int i; unsigned long flags; irq_desc_t *desc; =20 - bitmap_for_each ( i, &val, len * 8 ) + if ( len < sizeof(val) ) + val &=3D (1UL << (len * 8)) - 1; + + for_each_set_bit ( i, val ) { struct vgic_irq *irq =3D vgic_get_irq(vcpu->domain, vcpu, intid + = i); =20 @@ -326,9 +334,11 @@ void vgic_mmio_write_cactive(struct vcpu *vcpu, unsigned long val) { uint32_t intid =3D VGIC_ADDR_TO_INTID(addr, 1); - unsigned int i; =20 - bitmap_for_each ( i, &val, len * 8 ) + if ( len < sizeof(val) ) + val &=3D (1UL << (len * 8)) - 1; + + for_each_set_bit ( i, val ) { struct vgic_irq *irq =3D vgic_get_irq(vcpu->domain, vcpu, intid + = i); =20 @@ -356,9 +366,11 @@ void vgic_mmio_write_sactive(struct vcpu *vcpu, unsigned long val) { uint32_t intid =3D VGIC_ADDR_TO_INTID(addr, 1); - unsigned int i; =20 - bitmap_for_each ( i, &val, len * 8 ) + if ( len < sizeof(val) ) + val &=3D (1UL << (len * 8)) - 1; + + for_each_set_bit ( i, val ) { struct vgic_irq *irq =3D vgic_get_irq(vcpu->domain, vcpu, intid + = i); =20 --=20 2.39.2