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Tue, 27 Aug 2024 06:57:53 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , Stefano Stabellini , Julien Grall Subject: [PATCH 1/4] xen/evtchn: Use bitmap_for_each() in evtchn_check_pollers() Date: Tue, 27 Aug 2024 14:57:43 +0100 Message-Id: <20240827135746.1908070-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240827135746.1908070-1-andrew.cooper3@citrix.com> References: <20240827135746.1908070-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1724767090013116600 Content-Type: text/plain; charset="utf-8" It is a preprocessor-identical opencoding. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Stefano Stabellini CC: Julien Grall --- xen/common/event_channel.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c index 13b97c94d7fa..8db2ca4ba23e 100644 --- a/xen/common/event_channel.c +++ b/xen/common/event_channel.c @@ -1517,9 +1517,7 @@ void evtchn_check_pollers(struct domain *d, unsigned = int port) return; =20 /* Wake any interested (or potentially interested) pollers. */ - for ( vcpuid =3D find_first_bit(d->poll_mask, d->max_vcpus); - vcpuid < d->max_vcpus; - vcpuid =3D find_next_bit(d->poll_mask, d->max_vcpus, vcpuid+1) ) + bitmap_for_each ( vcpuid, d->poll_mask, d->max_vcpus ) { v =3D d->vcpu[vcpuid]; if ( ((v->poll_evtchn <=3D 0) || (v->poll_evtchn =3D=3D port)) && --=20 2.39.2 From nobody Sat Nov 23 12:06:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Tue, 27 Aug 2024 06:57:54 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 2/4] x86/hvm: Use for_each_set_bit() in hvm_emulate_writeback() Date: Tue, 27 Aug 2024 14:57:44 +0100 Message-Id: <20240827135746.1908070-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240827135746.1908070-1-andrew.cooper3@citrix.com> References: <20240827135746.1908070-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1724767093926116600 ... which is more consise than the opencoded form. Also, for production VMs, ~100% of emulations are simple MOVs, so it is lik= ely that there are no segments to write back. Furthermore, now that find_{first,next}_bit() are no longer in use, the seg_reg_{accessed,dirty} fields aren't forced to be unsigned long, although they do need to remain unsigned int because of __set_bit() elsewhere. No practical change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 Pulling current out into curr is good for code generation. When using curr= ent in the loop, GCC can't retain the calculation across the call to hvm_set_segment_register() and is forced to re-read from the cpu_info block. However, if curr is initialised, it's calculated even in the likely path... --- xen/arch/x86/hvm/emulate.c | 20 ++++++++++---------- xen/arch/x86/include/asm/hvm/emulate.h | 4 ++-- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c index feb4792cc567..732bdbab25b0 100644 --- a/xen/arch/x86/hvm/emulate.c +++ b/xen/arch/x86/hvm/emulate.c @@ -2908,18 +2908,18 @@ void hvm_emulate_init_per_insn( void hvm_emulate_writeback( struct hvm_emulate_ctxt *hvmemul_ctxt) { - enum x86_segment seg; + struct vcpu *curr; + unsigned int dirty =3D hvmemul_ctxt->seg_reg_dirty; =20 - seg =3D find_first_bit(&hvmemul_ctxt->seg_reg_dirty, - ARRAY_SIZE(hvmemul_ctxt->seg_reg)); + if ( likely(!dirty) ) + return; =20 - while ( seg < ARRAY_SIZE(hvmemul_ctxt->seg_reg) ) - { - hvm_set_segment_register(current, seg, &hvmemul_ctxt->seg_reg[seg]= ); - seg =3D find_next_bit(&hvmemul_ctxt->seg_reg_dirty, - ARRAY_SIZE(hvmemul_ctxt->seg_reg), - seg+1); - } + curr =3D current; + + for_each_set_bit ( seg, dirty ) + hvm_set_segment_register(curr, seg, &hvmemul_ctxt->seg_reg[seg]); + + hvmemul_ctxt->seg_reg_dirty =3D 0; } =20 /* diff --git a/xen/arch/x86/include/asm/hvm/emulate.h b/xen/arch/x86/include/= asm/hvm/emulate.h index 29d679442e10..972cdf1fa0cf 100644 --- a/xen/arch/x86/include/asm/hvm/emulate.h +++ b/xen/arch/x86/include/asm/hvm/emulate.h @@ -36,8 +36,8 @@ struct hvm_emulate_ctxt { unsigned int insn_buf_bytes; =20 struct segment_register seg_reg[10]; - unsigned long seg_reg_accessed; - unsigned long seg_reg_dirty; + unsigned int seg_reg_accessed; + unsigned int seg_reg_dirty; =20 /* * MFNs behind temporary mappings in the write callback. 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Tue, 27 Aug 2024 06:57:55 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 3/4] x86/hvm: Rework hpet_write() for improved code generation Date: Tue, 27 Aug 2024 14:57:45 +0100 Message-Id: <20240827135746.1908070-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240827135746.1908070-1-andrew.cooper3@citrix.com> References: <20240827135746.1908070-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1724767097883116600 In the HPET_STATUS handling, the use of __clear_bit(i, &new_val) is the only thing causing it to be spilled to the stack. Furthemore we only care about the bottom 3 bits, so rewrite it to be a plain for loop. For the {start,stop}_timer variables, these are spilled to the stack despite the __{set,clear}_bit() calls. Again we only care about the bottom 3 bits,= so shrink the variables from long to int. Use for_each_set_bit() rather than opencoding it at the end which amongst other things means the loop predicate is no longer forced to the stack by the loop body. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 All in all, it's modest according to bloat-o-meter: add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-29 (-29) Function old new delta hpet_write 2225 2196 -29 but we have shrunk the stack frame by 8 bytes; 0x28 as opposed to 0x30 befo= re. --- xen/arch/x86/hvm/hpet.c | 29 ++++++++--------------------- 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/xen/arch/x86/hvm/hpet.c b/xen/arch/x86/hvm/hpet.c index 87642575f9cd..e3981d5e467c 100644 --- a/xen/arch/x86/hvm/hpet.c +++ b/xen/arch/x86/hvm/hpet.c @@ -349,8 +349,7 @@ static int cf_check hpet_write( unsigned int tn, i; =20 /* Acculumate a bit mask of timers whos state is changed by this write= . */ - unsigned long start_timers =3D 0; - unsigned long stop_timers =3D 0; + unsigned int start_timers =3D 0, stop_timers =3D 0; #define set_stop_timer(n) (__set_bit((n), &stop_timers)) #define set_start_timer(n) (__set_bit((n), &start_timers)) #define set_restart_timer(n) (set_stop_timer(n),set_start_timer(n)) @@ -405,16 +404,12 @@ static int cf_check hpet_write( =20 case HPET_STATUS: /* write 1 to clear. */ - while ( new_val ) + for ( i =3D 0; i < HPET_TIMER_NUM; i++ ) { - bool active; - - i =3D ffsl(new_val) - 1; - if ( i >=3D HPET_TIMER_NUM ) - break; - __clear_bit(i, &new_val); - active =3D __test_and_clear_bit(i, &h->hpet.isr); - if ( active ) + if ( !(new_val & (1U << i)) ) + continue; + + if ( __test_and_clear_bit(i, &h->hpet.isr) ) { hvm_ioapic_deassert(v->domain, timer_int_route(h, i)); if ( hpet_enabled(h) && timer_enabled(h, i) && @@ -533,19 +528,11 @@ static int cf_check hpet_write( } =20 /* stop/start timers whos state was changed by this write. */ - while (stop_timers) - { - i =3D ffsl(stop_timers) - 1; - __clear_bit(i, &stop_timers); + for_each_set_bit ( i, stop_timers ) hpet_stop_timer(h, i, guest_time); - } =20 - while (start_timers) - { - i =3D ffsl(start_timers) - 1; - __clear_bit(i, &start_timers); + for_each_set_bit ( i, start_timers ) hpet_set_timer(h, i, guest_time); - } =20 #undef set_stop_timer #undef set_start_timer --=20 2.39.2 From nobody Sat Nov 23 12:06:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Tue, 27 Aug 2024 06:57:56 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel , Oleksii Kurochko Subject: [PATCH v2 4/4] x86/vmx: Rewrite vmx_sync_pir_to_irr() to be more efficient Date: Tue, 27 Aug 2024 14:57:46 +0100 Message-Id: <20240827135746.1908070-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240827135746.1908070-1-andrew.cooper3@citrix.com> References: <20240827135746.1908070-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1724767099944116600 There are two issues. First, pi_test_and_clear_on() pulls the cache-line to the CPU and dirties it even if there's nothing outstanding, but the final for_each_set_bit() is O(256) when O(8) would do, and would avoid multiple atomic updates to the same IRR word. Rewrite it from scratch, explaining what's going on at each step. Bloat-o-meter reports 177 -> 145 (net -32), but the better aspect is the removal calls to __find_{first,next}_bit() hidden behind for_each_set_bit(). No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel CC: Oleksii Kurochko The main purpose of this is to get rid of bitmap_for_each(). v2: * Extend the comments --- xen/arch/x86/hvm/vmx/vmx.c | 70 +++++++++++++++++++++++++++++++++----- 1 file changed, 62 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 12f8a66458db..1baed7e816c4 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2317,18 +2317,72 @@ static void cf_check vmx_deliver_posted_intr(struct= vcpu *v, u8 vector) =20 static void cf_check vmx_sync_pir_to_irr(struct vcpu *v) { - struct vlapic *vlapic =3D vcpu_vlapic(v); - unsigned int group, i; - DECLARE_BITMAP(pending_intr, X86_NR_VECTORS); + struct pi_desc *desc =3D &v->arch.hvm.vmx.pi_desc; + union { + uint64_t _64[X86_NR_VECTORS / (sizeof(uint64_t) * 8)]; + uint32_t _32[X86_NR_VECTORS / (sizeof(uint32_t) * 8)]; + } vec; + uint32_t *irr; + bool on; =20 - if ( !pi_test_and_clear_on(&v->arch.hvm.vmx.pi_desc) ) + /* + * The PIR is a contended cacheline which bounces between the CPU(s) a= nd + * IOMMU(s). An IOMMU updates the entire PIR atomically, but we can't + * express the same on the CPU side, so care has to be taken. + * + * First, do a plain read of ON. If the PIR hasn't been modified, this + * will keep the cacheline Shared and not pull it Excusive on the curr= ent + * CPU. + */ + if ( !pi_test_on(desc) ) return; =20 - for ( group =3D 0; group < ARRAY_SIZE(pending_intr); group++ ) - pending_intr[group] =3D pi_get_pir(&v->arch.hvm.vmx.pi_desc, group= ); + /* + * Second, if the plain read said that ON was set, we must clear it wi= th + * an atomic action. This will bring the cachline to Exclusive on the + * current CPU. + * + * This should always succeed because noone else should be playing with + * the PIR behind our back, but assert so just in case. + */ + on =3D pi_test_and_clear_on(desc); + ASSERT(on); + + /* + * The cacheline is now Exclusive on the current CPU, and because ON w= as + * set, some other entity (an IOMMU, or Xen on another CPU) has indica= ted + * that at PIR needs re-scanning. + * + * Note: Entities which can't update the entire cacheline atomically + * (i.e. Xen on another CPU) are required to update PIR first, t= hen + * set ON. Therefore, there is a corner case where we may have + * found and processed the PIR updates "last time around" and on= ly + * found ON this time around. This is fine; the logic still + * operates correctly. + * + * Atomically read and clear the entire pending bitmap as fast as we, = to + * reduce the window where another entity may steal the cacheline back + * from us. This is a performance concern, not a correctness concern.= If + * the another entity does steal the cacheline back, we'll just wait to + * get it back again. + */ + for ( unsigned int i =3D 0; i < ARRAY_SIZE(vec._64); ++i ) + vec._64[i] =3D xchg(&desc->pir[i], 0); + + /* + * Finally, merge the pending vectors into IRR. The IRR register is + * scattered in memory, so we have to do this 32 bits at a time. + */ + irr =3D (uint32_t *)&vcpu_vlapic(v)->regs->data[APIC_IRR]; + for ( unsigned int i =3D 0; i < ARRAY_SIZE(vec._32); ++i ) + { + if ( !vec._32[i] ) + continue; =20 - bitmap_for_each ( i, pending_intr, X86_NR_VECTORS ) - vlapic_set_vector(i, &vlapic->regs->data[APIC_IRR]); + asm ( "lock or %[val], %[irr]" + : [irr] "+m" (irr[i * 0x10]) + : [val] "r" (vec._32[i]) ); + } } =20 static bool cf_check vmx_test_pir(const struct vcpu *v, uint8_t vec) --=20 2.39.2