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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Aug 2024 16:31:42.0036 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9087873e-ac76-4140-ea5d-08dcc3911219 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8507 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1724430732271116600 Content-Type: text/plain; charset="utf-8" There are features in the forthcoming patches which are dependent on MPU. For eg fixed start address. Also, some of the Xen features (eg STATIC_MEMORY) will be selected by the MPU configuration. Thus, this patch introduces a choice between MMU and MPU for the type of memory management system. By default, MMU is selected. All the current platforms are now made dependent on MMU. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/Kconfig | 17 ++++++++++++++++- xen/arch/arm/platforms/Kconfig | 2 +- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 323c967361..686948cefd 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -58,10 +58,25 @@ config PADDR_BITS default 40 if ARM_PA_BITS_40 default 48 if ARM_64 =20 +choice + prompt "Memory management system" + default MMU if ARM + help + User can choose between the different forms of memory management system. + Most of the Arm based systems support MMU. + config MMU - def_bool y + bool "MMU" select HAS_PMAP select HAS_VMAP + help + Memory management unit is supported on most Arm based systems. + +config MPU + bool "MPU" + help + Memory protection unit is supported on some Cortex-R systems. +endchoice =20 source "arch/Kconfig" =20 diff --git a/xen/arch/arm/platforms/Kconfig b/xen/arch/arm/platforms/Kconfig index 76f7e76b1b..02322c259c 100644 --- a/xen/arch/arm/platforms/Kconfig +++ b/xen/arch/arm/platforms/Kconfig @@ -1,5 +1,5 @@ choice - prompt "Platform Support" + prompt "Platform Support" if MMU default ALL_PLAT help Choose which hardware platform to enable in Xen. --=20 2.25.1 From nobody Wed Dec 4 09:06:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Xie" , "Ayan Kumar Halder" Subject: [PATCH v1 2/4] xen/arm: mpu: Define Xen start address for MPU systems Date: Fri, 23 Aug 2024 17:31:25 +0100 Message-ID: <20240823163127.3443404-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240823163127.3443404-1-ayan.kumar.halder@amd.com> References: <20240823163127.3443404-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB04.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CF:EE_|PH7PR12MB6812:EE_ X-MS-Office365-Filtering-Correlation-Id: a5601d19-ca2f-46f3-d9a5-08dcc3911580 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ARmCeBXfk6QRFpEG4jk0AIjOUPHmrXb0p+E30Mj7a1K2tFxRiJtMQ/3MD9dJ?= =?us-ascii?Q?fF8QDWR69s+cBuSpyloRiCAB8TMkcClsPpplcL7lykHYjRTFX9cwqP6FDuUr?= =?us-ascii?Q?F1w447t/1KUktXFjsNJkHXfY5Oattz9FsFLT0CgqrgTWaiT63bCscLG0VetV?= =?us-ascii?Q?33RFdNoJpIjM96gA188aKYpAYhWyQqx19ZdQ+U8BFc52QGsFyaUwuoCPADom?= =?us-ascii?Q?BN7Yg3qrqdgIXyjoHMojXXqrX7wShL9VuYCcWHPndfKajdGCKQpg4M9UItBA?= =?us-ascii?Q?Bhv+v7ISdodHSibwbXp9DT/LbxxMgzE0eGd+HpnE1d3/0bDa3IPNMvTOQ3DB?= =?us-ascii?Q?/xnO6j9/08jte0V3npyM18BvXYcLXRWTDBc2m9Z3fMYqfDjVBN6xVS536lkr?= =?us-ascii?Q?F2nNMJq0eVMv/sii9WqSadGLjqdmNkgnApwk5d72qPFrS5RqbLYPgRZ12+p/?= =?us-ascii?Q?GcVwmaGP/cfXR6bcUL2R9hG34Jn+hV7UANF/TJp6rMVqkREZDWZjRJX6Ju9b?= =?us-ascii?Q?ToD0sDNTZOKfeFea+sWVwNUQURQ4sM6Nc8zqX2QYiBvOu5j7MJfsc3RrFOxh?= =?us-ascii?Q?E0JShs4q/We6P3IZkuO9U/bG907qf7rSnt+ckgrsmQvTeqOgOlBd9YeKoD1y?= =?us-ascii?Q?KNbaZ4D/rdh45YGoEvf/PDKs3miH0iQiJBDBcQR7n2TO1WbkL+SfQEfE9lZY?= =?us-ascii?Q?TOGm7U/j2hIKYwA69SN89ceFL3lb3uWCb9nmBmfz+8sXDijI7DFGBJVZWF1d?= =?us-ascii?Q?HR0dk482vODG9XDBC/3zCNmiM3g7wzBLczajYaI7ewx/6JnyUwKrHv24MukK?= =?us-ascii?Q?5Ixm009qxXRurnOsvtAfUfGN37mtz9s4Ci9UMX44XLq1OMeVtQhGT/pyGnfA?= =?us-ascii?Q?lZYO121MnSGxjGp4E8+idzJ1C93UPfHGTm8yy/vq3KUv9WtHoZpUvSbEhsrG?= =?us-ascii?Q?UaS4ZCB8CNabMbwfmzTbp75YsEmkktuM82WRxwh1h80GHm8fsJHRSROTnoIE?= =?us-ascii?Q?t2j7hpE5N/CZFgWyHWLlMPV7u02uq1wEeTWK7yZvuz1IB31lwy2HdmVscwTW?= =?us-ascii?Q?UQDluyVPsMKVdMN82snWBW2qxLrtoAHaZChTBmqwzNf4PFcXcE9xJ5/xQ4+j?= =?us-ascii?Q?kQubf8a51oqmcCRTtf8h9hAl3A0HGSFM0/InrQax5qafTYO2eCu+9i7E/UQz?= =?us-ascii?Q?r3N5YYpbZve75gcbqwxj1hxTYHcwrox1HDPp9FF/15bCnDt/9gxEwENNc4Lr?= =?us-ascii?Q?/wmIq8x9VtVOwQ1tVOG5FXRvJXiPVvDmFWqiFOA3Vvkvb1YqfEEPLmQmJOdG?= =?us-ascii?Q?dAI4wYGd+dL7Np2EYnpChsVMHGeF3Kasm64Etyjp/1GisKCqnkgginyNJ+0N?= =?us-ascii?Q?uq24XozqtUoa2R+zmKWg+SUaMPzp9hbBSZPSDzhcglSwvfLiAI+amaz+cPnf?= =?us-ascii?Q?bdaYP/bB4nfESq29pQgP7FOZs57hLL1/?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Aug 2024 16:31:47.6645 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5601d19-ca2f-46f3-d9a5-08dcc3911580 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6812 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1724430738085116600 Content-Type: text/plain; charset="utf-8" From: Wei Chen On Armv8-A, Xen has a fixed virtual start address (link address too) for all Armv8-A platforms. In an MMU based system, Xen can map its loaded address to this virtual start address. So, on Armv8-A platforms, the Xen start address does not need to be configurable. But on Armv8-R platforms, there is no MMU to map loaded address to a fixed virtual address and different platforms will have very different address space layout. So Xen cannot use a fixed physical address on MPU based system and need to have it configurable. So in this patch, we reuse the existing arm/platforms to store Armv8-R platforms' parameters. And `XEN_START_ADDRESS` is one kind of MPU based platform's parameters. So we define default `XEN_START_ADDRESS` in the MPU specific header file. We also introduce one Kconfig option for users to override the default Xen start address of selected platform, if they think the default address doesn't suit their scenarios. For this Kconfig option, we use an unaligned address "0xffffffff" as the default value to indicate that users haven't used a customized Xen start address. Signed-off-by: Wei Chen Signed-off-by: Jiamei.Xie Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/Kconfig | 11 +++++++++++ xen/arch/arm/include/asm/mpu/layout.h | 25 +++++++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 xen/arch/arm/include/asm/mpu/layout.h diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 686948cefd..d722ca690c 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -23,6 +23,17 @@ config ARCH_DEFCONFIG default "arch/arm/configs/arm32_defconfig" if ARM_32 default "arch/arm/configs/arm64_defconfig" if ARM_64 =20 +config XEN_START_ADDRESS + hex "Xen start address: keep default to use platform defined address" + default 0xFFFFFFFF + depends on MPU + help + This option is allowed to set customized address at which Xen will be + linked on MPU systems. This address must be aligned to a page size. + Use 0xFFFFFFFF as the default value to indicate that user hasn't + customized this address, and Xen use use the default value that has + been defined in platform files. + menu "Architecture Features" =20 choice diff --git a/xen/arch/arm/include/asm/mpu/layout.h b/xen/arch/arm/include/a= sm/mpu/layout.h new file mode 100644 index 0000000000..82a74b8b5b --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/layout.h @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * config_mpu.h: A Linux-style configuration list for Arm MPU systems, + * only can be included by config.h + */ + +#ifndef __ARM_CONFIG_MPU_H__ +#define __ARM_CONFIG_MPU_H__ + + +#define XEN_START_ADDRESS CONFIG_XEN_START_ADDRESS + +/* + * All MPU platforms need to provide a XEN_START_ADDRESS for linker. This + * address indicates where Xen image will be loaded and run from. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Aug 2024 16:31:52.5668 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 706a318d-5ef2-49a3-932d-08dcc391185e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5740 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1724430734098116600 Content-Type: text/plain; charset="utf-8" Define enable_boot_cpu_mm() for the AArch64-V8R system. Like boot-time page table in MMU system, we need a boot-time MPU protection region configuration in MPU system so Xen can fetch code and data from normal memory. START_ADDRESS + 2MB memory is mapped to contain the text and data required for early boot of Xen. One can refer to ARM DDI 0600B.a ID062922 G1.3 "General System Control Registers", to get the definitions of PRBAR_EL2, PRLAR_EL2 and PRSELR_EL2 registers. Also, refer to G1.2 "Accessing MPU memory region registers", the following ``` The MPU provides two register interfaces to program the MPU regions: - Access to any of the MPU regions via PRSELR_ELx, PRBAR_ELx, and PRLAR_ELx. ``` We use the above mechanism to configure the MPU memory regions. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/Makefile | 1 + xen/arch/arm/arm64/mpu/Makefile | 1 + xen/arch/arm/arm64/mpu/head.S | 70 ++++++++++++++++++++++++ xen/arch/arm/include/asm/arm64/sysregs.h | 50 +++++++++++++++++ xen/arch/arm/include/asm/mpu/arm64/mm.h | 13 +++++ xen/arch/arm/include/asm/mpu/mm.h | 18 ++++++ 6 files changed, 153 insertions(+) create mode 100644 xen/arch/arm/arm64/mpu/Makefile create mode 100644 xen/arch/arm/arm64/mpu/head.S create mode 100644 xen/arch/arm/include/asm/mpu/arm64/mm.h create mode 100644 xen/arch/arm/include/asm/mpu/mm.h diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 7792bff597..aebccec63a 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_ARM_32) +=3D arm32/ obj-$(CONFIG_ARM_64) +=3D arm64/ obj-$(CONFIG_MMU) +=3D mmu/ +obj-$(CONFIG_MPU) +=3D mpu/ obj-$(CONFIG_ACPI) +=3D acpi/ obj-$(CONFIG_HAS_PCI) +=3D pci/ ifneq ($(CONFIG_NO_PLAT),y) diff --git a/xen/arch/arm/arm64/mpu/Makefile b/xen/arch/arm/arm64/mpu/Makef= ile new file mode 100644 index 0000000000..3340058c08 --- /dev/null +++ b/xen/arch/arm/arm64/mpu/Makefile @@ -0,0 +1 @@ +obj-y +=3D head.o diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S new file mode 100644 index 0000000000..2b023c346a --- /dev/null +++ b/xen/arch/arm/arm64/mpu/head.S @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Start-of-day code for an Armv8-R MPU system. + */ + +#include +#include +#include + +/* + * From the requirements of head.S we know that Xen image should + * be linked at XEN_START_ADDRESS, and all of text + data + bss + * must fit in 2MB. On MPU systems, XEN_START_ADDRESS is also the + * address that Xen image should be loaded at. So for initial MPU + * regions setup, we use 2MB for Xen data memory to setup boot + * region, or the create boot regions code below will need adjustment. + */ +#define XEN_START_MEM_SIZE 0x200000 + +/* + * In boot stage, we will use 1 MPU region: + * Region#0: Normal memory for Xen text + data + bss (2MB) + */ +#define BOOT_NORMAL_REGION_IDX 0x0 + +/* MPU normal memory attributes. */ +#define PRBAR_NORMAL_MEM 0x30 /* SH=3D11 AP=3D00 XN=3D00 */ +#define PRLAR_NORMAL_MEM 0x0f /* NS=3D0 ATTR=3D111 EN=3D1 */ + +.macro write_pr, sel, prbar, prlar + msr PRSELR_EL2, \sel + dsb sy + msr PRBAR_EL2, \prbar + msr PRLAR_EL2, \prlar + dsb sy + isb +.endm + +.section .text.header, "ax", %progbits + +/* + * Static start-of-day EL2 MPU memory layout. + * + * It has a very simple structure, including: + * - 2MB normal memory mappings of xen at XEN_START_ADDRESS, which + * is the address where Xen was loaded by the bootloader. + */ +ENTRY(enable_boot_cpu_mm) + /* Map Xen start memory to a normal memory region. */ + mov x0, #BOOT_NORMAL_REGION_IDX + ldr x1, =3DXEN_START_ADDRESS + and x1, x1, #MPU_REGION_MASK + mov x3, #PRBAR_NORMAL_MEM + orr x1, x1, x3 + + ldr x2, =3DXEN_START_ADDRESS + mov x3, #(XEN_START_MEM_SIZE - 1) + add x2, x2, x3 + and x2, x2, #MPU_REGION_MASK + mov x3, #PRLAR_NORMAL_MEM + orr x2, x2, x3 + + /* + * Write to MPU protection region: + * x0 for pr_sel, x1 for prbar x2 for prlar + */ + write_pr x0, x1, x2 + + ret +ENDPROC(enable_boot_cpu_mm) diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/includ= e/asm/arm64/sysregs.h index b593e4028b..0d122e1fa6 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,56 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff =20 +/* System registers for AArch64 with PMSA */ +#ifdef CONFIG_MPU + +/* EL2 MPU Protection Region Base Address Register encode */ +#define PRBAR_EL2 S3_4_C6_C8_0 +#define PRBAR1_EL2 S3_4_C6_C8_4 +#define PRBAR2_EL2 S3_4_C6_C9_0 +#define PRBAR3_EL2 S3_4_C6_C9_4 +#define PRBAR4_EL2 S3_4_C6_C10_0 +#define PRBAR5_EL2 S3_4_C6_C10_4 +#define PRBAR6_EL2 S3_4_C6_C11_0 +#define PRBAR7_EL2 S3_4_C6_C11_4 +#define PRBAR8_EL2 S3_4_C6_C12_0 +#define PRBAR9_EL2 S3_4_C6_C12_4 +#define PRBAR10_EL2 S3_4_C6_C13_0 +#define PRBAR11_EL2 S3_4_C6_C13_4 +#define PRBAR12_EL2 S3_4_C6_C14_0 +#define PRBAR13_EL2 S3_4_C6_C14_4 +#define PRBAR14_EL2 S3_4_C6_C15_0 +#define PRBAR15_EL2 S3_4_C6_C15_4 + +/* EL2 MPU Protection Region Limit Address Register encode */ +#define PRLAR_EL2 S3_4_C6_C8_1 +#define PRLAR1_EL2 S3_4_C6_C8_5 +#define PRLAR2_EL2 S3_4_C6_C9_1 +#define PRLAR3_EL2 S3_4_C6_C9_5 +#define PRLAR4_EL2 S3_4_C6_C10_1 +#define PRLAR5_EL2 S3_4_C6_C10_5 +#define PRLAR6_EL2 S3_4_C6_C11_1 +#define PRLAR7_EL2 S3_4_C6_C11_5 +#define PRLAR8_EL2 S3_4_C6_C12_1 +#define PRLAR9_EL2 S3_4_C6_C12_5 +#define PRLAR10_EL2 S3_4_C6_C13_1 +#define PRLAR11_EL2 S3_4_C6_C13_5 +#define PRLAR12_EL2 S3_4_C6_C14_1 +#define PRLAR13_EL2 S3_4_C6_C14_5 +#define PRLAR14_EL2 S3_4_C6_C15_1 +#define PRLAR15_EL2 S3_4_C6_C15_5 + +/* MPU Protection Region Enable Register encode */ +#define PRENR_EL2 S3_4_C6_C1_1 + +/* MPU Protection Region Selection Register encode */ +#define PRSELR_EL2 S3_4_C6_C2_1 + +/* MPU Type registers encode */ +#define MPUIR_EL2 S3_4_C0_C0_4 + +#endif + /* Access to system registers */ =20 #define WRITE_SYSREG64(v, name) do { \ diff --git a/xen/arch/arm/include/asm/mpu/arm64/mm.h b/xen/arch/arm/include= /asm/mpu/arm64/mm.h new file mode 100644 index 0000000000..d209eef6db --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/arm64/mm.h @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * mpu.h: Arm Memory Protection Unit definitions. + */ + +#ifndef __ARM64_MPU_H__ +#define __ARM64_MPU_H__ + +#define MPU_REGION_SHIFT 6 +#define MPU_REGION_ALIGN (_AC(1, UL) << MPU_REGION_SHIFT) +#define MPU_REGION_MASK (~(MPU_REGION_ALIGN - 1)) + +#endif /* __ARM64_MPU_H__ */ diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/m= pu/mm.h new file mode 100644 index 0000000000..f5ebca8261 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/mm.h @@ -0,0 +1,18 @@ +#ifndef __ARCH_ARM_MPU__ +#define __ARCH_ARM_MPU__ + +#if defined(CONFIG_ARM_64) +# include +#else +# error "unknown ARM variant" +#endif + +#endif /* __ARCH_ARM_MPU__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.25.1 From nobody Wed Dec 4 09:06:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Aug 2024 16:31:57.9220 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68002031-1f55-4867-dcb0-08dcc3911b96 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8896 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1724430746105116600 Content-Type: text/plain; charset="utf-8" Secondary cpus are put in WFE state. We do not support SMP at this time. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/arm64/mpu/head.S | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index 2b023c346a..1579ac0408 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -68,3 +68,12 @@ ENTRY(enable_boot_cpu_mm) =20 ret ENDPROC(enable_boot_cpu_mm) + +/* + * Secondary cpu has not yet been supported on MPU systems. We will block = the + * secondary cpu bringup at this stage. + */ +ENTRY(enable_secondary_cpu_mm) +1: wfe + b 1b +ENDPROC(enable_secondary_cpu_mm) --=20 2.25.1