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X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?iMFINjeaRhphnzIhdQ8+XbUmpPzE8dHzYcTwRERtE1wuA/qlYjtX4e+poJSM?= =?us-ascii?Q?CCVwnmA7JXiVb5mIiiVOYJnMqGs59k9EXi+Sq/3hrNqmfX08TkTh2o01iWRQ?= =?us-ascii?Q?M2YqrURrPpe4EUWB0bFN5Xhkpbo911LQCogrXzx4c8/WVvdiwMWp33/wAkOg?= =?us-ascii?Q?Iiq+bNXFKHcmpJ/vHSc8Wgggm9FB7nOyL/0JEownpHRrDg5SsL2C0rNWEFCR?= =?us-ascii?Q?tcLaBaenCj5LW4Xy27WmS4tqewoklgynw6fvgar6j5RNdazwSzdoSIcyGVIv?= =?us-ascii?Q?kLsletkW8rwYInyoZ9HOniO9+ZZLuQ4Mg8z85DjFIMxhq3yq0+0IMPFCIPn1?= =?us-ascii?Q?E0GEYyArgOBO5guYQCSfUs6SlW5ZTFs815zQr2ey+48cp5Oa4WRH+NRiKgpr?= =?us-ascii?Q?pTIazFF8k/p98S20eFKW8vAzUG4j4CCWPEw0MuHk7GpWQcjmfM1Xw95kDLZs?= =?us-ascii?Q?HF0n4j14zIJD82g7VE65FAn03ORy2vhERYraTCDa8kmlTpK1PR1TohZ/yFbl?= =?us-ascii?Q?oTUMpPnx99NpLyGY7SoruE/aH/A3DMg1IBgqt98nJoyAM4qJCxRk7IU3n6S8?= =?us-ascii?Q?/ir2nnEMOx6koYrYhgFH0GNY6iHhh0E60WceaYX6uol4QmaHqWOdh2SS256N?= =?us-ascii?Q?PfLapAlQhsZQfvIjvjrpPv5tW2jOfxVbhTp1+Ih2AlKnahlp+pJRerrK5yeJ?= =?us-ascii?Q?fDf1FPFJ3O3EDPTbOphhbE6XKZPAECnXHxglZYkRDkBYgycyUYSyUXQIO2cC?= =?us-ascii?Q?9/K0KL7xYU088TZRseIsQyry9VNrq7o4HnQtOk2MRLQ8NGO+w04H47Wam8AP?= =?us-ascii?Q?o49UQF24E9zUkPaSi2nQLbz4s2BRXZf8LzWSXMP68hQa7ivQq8DfMid4VbhY?= =?us-ascii?Q?/1QpPaKN9+z2mTXVa7LK1iO+FUd/J+LtK55h3DXZwO9KAn8kZGQK8cnBjyYs?= =?us-ascii?Q?QWeqxi72GpyV9fZ7jYieo4Tot38/1sHCLmeXxBeX3gI9nfwDm5loPVO0fDHX?= =?us-ascii?Q?u0n1+CfrTaTIVMPBa8c8e0k1Bd2taHxvL6H10CvHsUfb6jiPHWVbnyRlngFs?= =?us-ascii?Q?8oYsV4oO6YIlaQE7muyZ/OibDV9QIGPXa+wjBffnwLqMOWQdNUVrtgEHzBIQ?= =?us-ascii?Q?/06KS1u/acFzr1eh5Tqwj7nsRMOLqgrHthtcjM3r1/ufkpcN3nMOFGn/CsSD?= =?us-ascii?Q?V7tVjtyrNtYaNXhSp36s2Ydt8tOHQY0CEXxatPEVkjDP9DCxsd8szcwd4kM7?= =?us-ascii?Q?vyq3r8rcBlPdljcBIXJgYRhsHpKxnQY/yQIHPMitkQaw9AP1aKqQ3/tMIbTF?= =?us-ascii?Q?4sakFYtmZoniEPOZQPkG8gvmmey1MtC2tv6c7gaQfmmi3B+OY8Imwn1tno41?= =?us-ascii?Q?WgrpGV5xJ/qTgfvKOSrRmRZft4MkBCj/7oyYfluDh+je5OWZdPIbQ2EW9JN6?= =?us-ascii?Q?CozlBzp3IG+Cr/gd8zIRUgcjNS3Q/J6B?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2024 12:09:51.2956 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba38611a-041f-4eda-b6a3-08dcb7a30190 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB51.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9346 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1723119019534116600 Content-Type: text/plain; charset="utf-8" update_boot_mapping() invokes update_identity_mapping() for the MMU specific code. Later when the MPU code is added, update_boot_mapping() would invoke the equivalent. The common code now invokes update_boot_mapping() instead of update_identity_mapping(). So, that there is clear abstraction between the common and MMU/MPU specific logic. This is in continuation to commit f661a20aa880: "Extract MMU-specific MM code". Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. Introduced update_boot_mapping() which invokes update_identity_mapping() in MMU specific code. xen/arch/arm/arm64/mmu/mm.c | 5 +++++ xen/arch/arm/arm64/smpboot.c | 6 +++--- xen/arch/arm/include/asm/mm.h | 2 ++ 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/arm64/mmu/mm.c b/xen/arch/arm/arm64/mmu/mm.c index 293acb67e0..72e089a339 100644 --- a/xen/arch/arm/arm64/mmu/mm.c +++ b/xen/arch/arm/arm64/mmu/mm.c @@ -125,6 +125,11 @@ void update_identity_mapping(bool enable) BUG_ON(rc); } =20 +void update_boot_mapping(bool enable) +{ + update_identity_mapping(enable); +} + extern void switch_ttbr_id(uint64_t ttbr); =20 typedef void (switch_ttbr_fn)(uint64_t ttbr); diff --git a/xen/arch/arm/arm64/smpboot.c b/xen/arch/arm/arm64/smpboot.c index a225fae64d..789f352ab6 100644 --- a/xen/arch/arm/arm64/smpboot.c +++ b/xen/arch/arm/arm64/smpboot.c @@ -112,18 +112,18 @@ int arch_cpu_up(int cpu) if ( !smp_enable_ops[cpu].prepare_cpu ) return -ENODEV; =20 - update_identity_mapping(true); + update_boot_mapping(true); =20 rc =3D smp_enable_ops[cpu].prepare_cpu(cpu); if ( rc ) - update_identity_mapping(false); + update_boot_mapping(false); =20 return rc; } =20 void arch_cpu_up_finish(void) { - update_identity_mapping(false); + update_boot_mapping(false); } =20 /* diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index f6ba611f01..e769d2d3b3 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -426,6 +426,8 @@ static inline void page_set_xenheap_gfn(struct page_inf= o *p, gfn_t gfn) } while ( (y =3D cmpxchg(&p->u.inuse.type_info, x, nx)) !=3D x ); } =20 +void update_boot_mapping(bool enable); + #endif /* __ARCH_ARM_MM__ */ /* * Local variables: --=20 2.25.1 From nobody Sun Nov 24 00:43:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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bh=BwnutoGseyOzPvX5xpU7euJ358TBpCesIKsrFcbDnqU=; b=syPB84+sX6kqZLMHisPRl9eo+E3JxK2hol2sw2rqvjn5XAA2Ng6Fcde+5lWl4YQxNtG055Zu+UrJK2An1ik33CH4rv34th9smBfB1pmdW1RS1UkN0vH3dgAAkKbx9D8Td4dSUV82BWT9mqTfHMrw68gPo/qNTDqNcdvnihpzw38= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: , , , , , CC: , Penny Zheng , "Wei Chen" Subject: [PATCH v2 2/4] xen: arm: make VMAP only support in MMU system Date: Thu, 8 Aug 2024 13:09:34 +0100 Message-ID: <20240808120936.3299937-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240808120936.3299937-1-ayan.kumar.halder@amd.com> References: <20240808120936.3299937-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AA:EE_|MN2PR12MB4469:EE_ X-MS-Office365-Filtering-Correlation-Id: bbe88be2-003a-4d26-2cc1-08dcb7a2ffb7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2024 12:09:47.3953 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bbe88be2-003a-4d26-2cc1-08dcb7a2ffb7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4469 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1723119025539116600 Content-Type: text/plain; charset="utf-8" From: Penny Zheng VMAP is widely used in ALTERNATIVE feature to remap a range of memory with new memory attributes. Since this is highly dependent on virtual address translation, we choose to fold VMAP in MMU system. In this patch, we introduce a new Kconfig CONFIG_HAS_VMAP, and make it only support in MMU system on ARM architecture. And ALTERNATIVE now depend on VMAP. HARDEN_BRANCH_PREDICTOR is now gated on HAS_VMAP as speculative attacks are not possible on non MMU based systems (ie Cortex-R52, R82). See https://developer.arm.com/Arm%20Security%20Center/Speculative%20Process= or%20Vulnerability. Split "https://patchwork.kernel.org/project/xen-devel/patch/20230626033443.= 2943270-16-Penny.Zheng@arm.com/" into Arm specific Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. HARDEN_BRANCH_PREDICTOR is now gated on HAS_VMAP. 2. cpuerrata.c is not gated on HAS_VMAP. xen/arch/arm/Kconfig | 7 ++++++- xen/arch/arm/setup.c | 2 ++ xen/include/xen/vmap.h | 2 ++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 21d03d9f44..7d1dde89d7 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -12,7 +12,7 @@ config ARM_64 config ARM def_bool y select FUNCTION_ALIGNMENT_4B - select HAS_ALTERNATIVE + select HAS_ALTERNATIVE if HAS_VMAP select HAS_DEVICE_TREE select HAS_PASSTHROUGH select HAS_UBSAN @@ -58,9 +58,13 @@ config PADDR_BITS default 40 if ARM_PA_BITS_40 default 48 if ARM_64 =20 +config HAS_VMAP + def_bool y + config MMU def_bool y select HAS_PMAP + select HAS_VMAP =20 source "arch/Kconfig" =20 @@ -171,6 +175,7 @@ config ARM_SSBD =20 config HARDEN_BRANCH_PREDICTOR bool "Harden the branch predictor against aliasing attacks" if EXPERT + depends on HAS_VMAP default y help Speculation attacks against some high-performance processors rely on diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index cb2c0a16b8..7f686d2cca 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -447,7 +447,9 @@ void asmlinkage __init start_xen(unsigned long boot_phy= s_offset, * It needs to be called after do_initcalls to be able to use * stop_machine (tasklets initialized via an initcall). */ +#ifdef CONFIG_HAS_ALTERNATIVE apply_alternatives_all(); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2024 12:09:47.9986 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6608c8f-ae3a-4c6e-06ee-08dcb7a2ff9c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB51.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7985 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1723119021482116600 Content-Type: text/plain; charset="utf-8" domain_page.c has been moved to mmu/domain_page.c. The reason being this file implements MMU specific logic for mapping, unmapping, etc domain page. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/mmu/Makefile | 1 + xen/arch/arm/{ =3D> mmu}/domain_page.c | 0 2 files changed, 1 insertion(+) rename xen/arch/arm/{ =3D> mmu}/domain_page.c (100%) diff --git a/xen/arch/arm/mmu/Makefile b/xen/arch/arm/mmu/Makefile index 67475fcd80..2cb44b857d 100644 --- a/xen/arch/arm/mmu/Makefile +++ b/xen/arch/arm/mmu/Makefile @@ -2,3 +2,4 @@ obj-y +=3D p2m.o obj-y +=3D pt.o obj-y +=3D setup.o obj-y +=3D smpboot.o +obj-$(CONFIG_ARCH_MAP_DOMAIN_PAGE) +=3D domain_page.o diff --git a/xen/arch/arm/domain_page.c b/xen/arch/arm/mmu/domain_page.c similarity index 100% rename from xen/arch/arm/domain_page.c rename to xen/arch/arm/mmu/domain_page.c --=20 2.25.1 From nobody Sun Nov 24 00:43:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2024 12:09:51.8237 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68d8ef76-460a-41db-5f86-08dcb7a301f4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4305 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1723119015682116600 Content-Type: text/plain; charset="utf-8" All the EL2 MMU specific registers are enclosed within CONFIG_MMU. Signed-off-by: Ayan Kumar Halder --- Changes from v1 :- 1. 'vttbr_el2' field is enclosed with ifdef. 2. No movement of code. xen/arch/arm/traps.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index aac6c599f8..f51e1424cb 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -720,8 +720,10 @@ struct reg_ctxt { uint32_t ifsr32_el2; #endif =20 +#ifdef CONFIG_MMU /* Hypervisor-side state */ uint64_t vttbr_el2; +#endif }; =20 static const char *mode_string(register_t cpsr) @@ -919,12 +921,16 @@ static void _show_registers(const struct cpu_user_reg= s *regs, #endif } printk(" VTCR_EL2: %"PRIregister"\n", READ_SYSREG(VTCR_EL2)); +#ifdef CONFIG_MMU printk(" VTTBR_EL2: %016"PRIx64"\n", ctxt->vttbr_el2); +#endif printk("\n"); =20 printk(" SCTLR_EL2: %"PRIregister"\n", READ_SYSREG(SCTLR_EL2)); printk(" HCR_EL2: %"PRIregister"\n", READ_SYSREG(HCR_EL2)); +#ifdef CONFIG_MMU printk(" TTBR0_EL2: %016"PRIx64"\n", READ_SYSREG64(TTBR0_EL2)); +#endif printk("\n"); printk(" ESR_EL2: %"PRIregister"\n", regs->hsr); printk(" HPFAR_EL2: %"PRIregister"\n", READ_SYSREG(HPFAR_EL2)); --=20 2.25.1