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Fri, 26 Jul 2024 08:31:28 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH 01/22] x86/mm: drop l{1,2,3,4}e_write_atomic() Date: Fri, 26 Jul 2024 17:21:45 +0200 Message-ID: <20240726152206.28411-2-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722007917543116600 The l{1,2,3,4}e_write_atomic() and non _atomic suffixed helpers share the s= ame implementation, so it seems pointless and possibly confusing to have both. Remove the l{1,2,3,4}e_write_atomic() helpers and switch it's user to l{1,2,3,4}e_write(), as that's also atomic. While there also remove pte_write{,_atomic}() and just use write_atomic() in the wrappers. No functional change intended. Signed-off-by: Roger Pau Monn=C3=A9 Reviewed-by: Jan Beulich --- xen/arch/x86/include/asm/page.h | 21 +++----------- xen/arch/x86/include/asm/x86_64/page.h | 2 -- xen/arch/x86/mm.c | 39 +++++++++++--------------- 3 files changed, 20 insertions(+), 42 deletions(-) diff --git a/xen/arch/x86/include/asm/page.h b/xen/arch/x86/include/asm/pag= e.h index 350d1fb1100f..3d20ee507a33 100644 --- a/xen/arch/x86/include/asm/page.h +++ b/xen/arch/x86/include/asm/page.h @@ -26,27 +26,14 @@ l4e_from_intpte(pte_read_atomic(&l4e_get_intpte(*(l4ep)))) =20 /* Write a pte atomically to memory. */ -#define l1e_write_atomic(l1ep, l1e) \ - pte_write_atomic(&l1e_get_intpte(*(l1ep)), l1e_get_intpte(l1e)) -#define l2e_write_atomic(l2ep, l2e) \ - pte_write_atomic(&l2e_get_intpte(*(l2ep)), l2e_get_intpte(l2e)) -#define l3e_write_atomic(l3ep, l3e) \ - pte_write_atomic(&l3e_get_intpte(*(l3ep)), l3e_get_intpte(l3e)) -#define l4e_write_atomic(l4ep, l4e) \ - pte_write_atomic(&l4e_get_intpte(*(l4ep)), l4e_get_intpte(l4e)) - -/* - * Write a pte safely but non-atomically to memory. - * The PTE may become temporarily not-present during the update. - */ #define l1e_write(l1ep, l1e) \ - pte_write(&l1e_get_intpte(*(l1ep)), l1e_get_intpte(l1e)) + write_atomic(&l1e_get_intpte(*(l1ep)), l1e_get_intpte(l1e)) #define l2e_write(l2ep, l2e) \ - pte_write(&l2e_get_intpte(*(l2ep)), l2e_get_intpte(l2e)) + write_atomic(&l2e_get_intpte(*(l2ep)), l2e_get_intpte(l2e)) #define l3e_write(l3ep, l3e) \ - pte_write(&l3e_get_intpte(*(l3ep)), l3e_get_intpte(l3e)) + write_atomic(&l3e_get_intpte(*(l3ep)), l3e_get_intpte(l3e)) #define l4e_write(l4ep, l4e) \ - pte_write(&l4e_get_intpte(*(l4ep)), l4e_get_intpte(l4e)) + write_atomic(&l4e_get_intpte(*(l4ep)), l4e_get_intpte(l4e)) =20 /* Get direct integer representation of a pte's contents (intpte_t). */ #define l1e_get_intpte(x) ((x).l1) diff --git a/xen/arch/x86/include/asm/x86_64/page.h b/xen/arch/x86/include/= asm/x86_64/page.h index 19ca64d79223..03fcce61c052 100644 --- a/xen/arch/x86/include/asm/x86_64/page.h +++ b/xen/arch/x86/include/asm/x86_64/page.h @@ -70,8 +70,6 @@ typedef l4_pgentry_t root_pgentry_t; #endif /* !__ASSEMBLY__ */ =20 #define pte_read_atomic(ptep) read_atomic(ptep) -#define pte_write_atomic(ptep, pte) write_atomic(ptep, pte) -#define pte_write(ptep, pte) write_atomic(ptep, pte) =20 /* Given a virtual address, get an entry offset into a linear page table. = */ #define l1_linear_offset(_a) (((_a) & VADDR_MASK) >> L1_PAGETABLE_SHIFT) diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 95795567f2a5..fab2de5fae27 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -5253,7 +5253,7 @@ int map_pages_to_xen( !(flags & (_PAGE_PAT | MAP_SMALL_PAGES)) ) { /* 1GB-page mapping. */ - l3e_write_atomic(pl3e, l3e_from_mfn(mfn, l1f_to_lNf(flags))); + l3e_write(pl3e, l3e_from_mfn(mfn, l1f_to_lNf(flags))); =20 if ( (l3e_get_flags(ol3e) & _PAGE_PRESENT) ) { @@ -5353,8 +5353,7 @@ int map_pages_to_xen( if ( (l3e_get_flags(*pl3e) & _PAGE_PRESENT) && (l3e_get_flags(*pl3e) & _PAGE_PSE) ) { - l3e_write_atomic(pl3e, - l3e_from_mfn(l2mfn, __PAGE_HYPERVISOR)); + l3e_write(pl3e, l3e_from_mfn(l2mfn, __PAGE_HYPERVISOR)); l2mfn =3D INVALID_MFN; } if ( locking ) @@ -5375,7 +5374,7 @@ int map_pages_to_xen( { /* Super-page mapping. */ ol2e =3D *pl2e; - l2e_write_atomic(pl2e, l2e_from_mfn(mfn, l1f_to_lNf(flags))); + l2e_write(pl2e, l2e_from_mfn(mfn, l1f_to_lNf(flags))); =20 if ( (l2e_get_flags(ol2e) & _PAGE_PRESENT) ) { @@ -5457,8 +5456,7 @@ int map_pages_to_xen( if ( (l2e_get_flags(*pl2e) & _PAGE_PRESENT) && (l2e_get_flags(*pl2e) & _PAGE_PSE) ) { - l2e_write_atomic(pl2e, l2e_from_mfn(l1mfn, - __PAGE_HYPERVISOR)= ); + l2e_write(pl2e, l2e_from_mfn(l1mfn, __PAGE_HYPERVISOR)= ); l1mfn =3D INVALID_MFN; } if ( locking ) @@ -5471,7 +5469,7 @@ int map_pages_to_xen( if ( !pl1e ) pl1e =3D map_l1t_from_l2e(*pl2e) + l1_table_offset(virt); ol1e =3D *pl1e; - l1e_write_atomic(pl1e, l1e_from_mfn(mfn, flags)); + l1e_write(pl1e, l1e_from_mfn(mfn, flags)); UNMAP_DOMAIN_PAGE(pl1e); if ( (l1e_get_flags(ol1e) & _PAGE_PRESENT) ) { @@ -5524,8 +5522,7 @@ int map_pages_to_xen( UNMAP_DOMAIN_PAGE(l1t); if ( i =3D=3D L1_PAGETABLE_ENTRIES ) { - l2e_write_atomic(pl2e, l2e_from_pfn(base_mfn, - l1f_to_lNf(flags))= ); + l2e_write(pl2e, l2e_from_pfn(base_mfn, l1f_to_lNf(flag= s))); if ( locking ) spin_unlock(&map_pgdir_lock); flush_area(virt - PAGE_SIZE, @@ -5574,8 +5571,7 @@ int map_pages_to_xen( UNMAP_DOMAIN_PAGE(l2t); if ( i =3D=3D L2_PAGETABLE_ENTRIES ) { - l3e_write_atomic(pl3e, l3e_from_pfn(base_mfn, - l1f_to_lNf(flags))); + l3e_write(pl3e, l3e_from_pfn(base_mfn, l1f_to_lNf(flags))); if ( locking ) spin_unlock(&map_pgdir_lock); flush_area(virt - PAGE_SIZE, @@ -5674,7 +5670,7 @@ int modify_xen_mappings(unsigned long s, unsigned lon= g e, unsigned int nf) : l3e_from_pfn(l3e_get_pfn(*pl3e), (l3e_get_flags(*pl3e) & ~FLAGS_MASK) | = nf); =20 - l3e_write_atomic(pl3e, nl3e); + l3e_write(pl3e, nl3e); v +=3D 1UL << L3_PAGETABLE_SHIFT; continue; } @@ -5696,8 +5692,7 @@ int modify_xen_mappings(unsigned long s, unsigned lon= g e, unsigned int nf) if ( (l3e_get_flags(*pl3e) & _PAGE_PRESENT) && (l3e_get_flags(*pl3e) & _PAGE_PSE) ) { - l3e_write_atomic(pl3e, - l3e_from_mfn(l2mfn, __PAGE_HYPERVISOR)); + l3e_write(pl3e, l3e_from_mfn(l2mfn, __PAGE_HYPERVISOR)); l2mfn =3D INVALID_MFN; } if ( locking ) @@ -5732,7 +5727,7 @@ int modify_xen_mappings(unsigned long s, unsigned lon= g e, unsigned int nf) : l2e_from_pfn(l2e_get_pfn(*pl2e), (l2e_get_flags(*pl2e) & ~FLAGS_MASK) | = nf); =20 - l2e_write_atomic(pl2e, nl2e); + l2e_write(pl2e, nl2e); v +=3D 1UL << L2_PAGETABLE_SHIFT; } else @@ -5755,8 +5750,7 @@ int modify_xen_mappings(unsigned long s, unsigned lon= g e, unsigned int nf) if ( (l2e_get_flags(*pl2e) & _PAGE_PRESENT) && (l2e_get_flags(*pl2e) & _PAGE_PSE) ) { - l2e_write_atomic(pl2e, l2e_from_mfn(l1mfn, - __PAGE_HYPERVISOR)= ); + l2e_write(pl2e, l2e_from_mfn(l1mfn, __PAGE_HYPERVISOR)= ); l1mfn =3D INVALID_MFN; } if ( locking ) @@ -5785,7 +5779,7 @@ int modify_xen_mappings(unsigned long s, unsigned lon= g e, unsigned int nf) : l1e_from_pfn(l1e_get_pfn(*pl1e), (l1e_get_flags(*pl1e) & ~FLAGS_MASK) | nf); =20 - l1e_write_atomic(pl1e, nl1e); + l1e_write(pl1e, nl1e); UNMAP_DOMAIN_PAGE(pl1e); v +=3D PAGE_SIZE; =20 @@ -5824,7 +5818,7 @@ int modify_xen_mappings(unsigned long s, unsigned lon= g e, unsigned int nf) if ( i =3D=3D L1_PAGETABLE_ENTRIES ) { /* Empty: zap the L2E and free the L1 page. */ - l2e_write_atomic(pl2e, l2e_empty()); + l2e_write(pl2e, l2e_empty()); if ( locking ) spin_unlock(&map_pgdir_lock); flush_area(NULL, FLUSH_TLB_GLOBAL); /* flush before free */ @@ -5868,7 +5862,7 @@ int modify_xen_mappings(unsigned long s, unsigned lon= g e, unsigned int nf) if ( i =3D=3D L2_PAGETABLE_ENTRIES ) { /* Empty: zap the L3E and free the L2 page. */ - l3e_write_atomic(pl3e, l3e_empty()); + l3e_write(pl3e, l3e_empty()); if ( locking ) spin_unlock(&map_pgdir_lock); flush_area(NULL, FLUSH_TLB_GLOBAL); /* flush before free */ @@ -5940,7 +5934,7 @@ void init_or_livepatch modify_xen_mappings_lite( { ASSERT(IS_ALIGNED(v, 1UL << L2_PAGETABLE_SHIFT)); =20 - l2e_write_atomic(pl2e, l2e_from_intpte((l2e.l2 & ~fm) | flags)= ); + l2e_write(pl2e, l2e_from_intpte((l2e.l2 & ~fm) | flags)); =20 v +=3D 1UL << L2_PAGETABLE_SHIFT; continue; @@ -5958,8 +5952,7 @@ void init_or_livepatch modify_xen_mappings_lite( =20 ASSERT(l1f & _PAGE_PRESENT); =20 - l1e_write_atomic(pl1e, - l1e_from_intpte((l1e.l1 & ~fm) | flags)); + l1e_write(pl1e, l1e_from_intpte((l1e.l1 & ~fm) | flags)); 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Fri, 26 Jul 2024 08:31:30 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH 02/22] x86/mm: rename l{1,2,3,4}e_read_atomic() Date: Fri, 26 Jul 2024 17:21:46 +0200 Message-ID: <20240726152206.28411-3-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722007915549116600 There's no l{1,2,3,4}e_read() implementation, so drop the _atomic suffix fr= om the read helpers. This allows unifying the naming with the write helpers, which are also atomic but don't have the suffix already: l{1,2,3,4}e_write(= ). No functional change intended. Signed-off-by: Roger Pau Monn=C3=A9 Reviewed-by: Jan Beulich --- xen/arch/x86/include/asm/page.h | 16 ++++++++-------- xen/arch/x86/include/asm/x86_64/page.h | 2 -- xen/arch/x86/mm.c | 12 ++++++------ xen/arch/x86/traps.c | 8 ++++---- 4 files changed, 18 insertions(+), 20 deletions(-) diff --git a/xen/arch/x86/include/asm/page.h b/xen/arch/x86/include/asm/pag= e.h index 3d20ee507a33..e48571de9332 100644 --- a/xen/arch/x86/include/asm/page.h +++ b/xen/arch/x86/include/asm/page.h @@ -16,14 +16,14 @@ #include =20 /* Read a pte atomically from memory. */ -#define l1e_read_atomic(l1ep) \ - l1e_from_intpte(pte_read_atomic(&l1e_get_intpte(*(l1ep)))) -#define l2e_read_atomic(l2ep) \ - l2e_from_intpte(pte_read_atomic(&l2e_get_intpte(*(l2ep)))) -#define l3e_read_atomic(l3ep) \ - l3e_from_intpte(pte_read_atomic(&l3e_get_intpte(*(l3ep)))) -#define l4e_read_atomic(l4ep) \ - l4e_from_intpte(pte_read_atomic(&l4e_get_intpte(*(l4ep)))) +#define l1e_read(l1ep) \ + l1e_from_intpte(read_atomic(&l1e_get_intpte(*(l1ep)))) +#define l2e_read(l2ep) \ + l2e_from_intpte(read_atomic(&l2e_get_intpte(*(l2ep)))) +#define l3e_read(l3ep) \ + l3e_from_intpte(read_atomic(&l3e_get_intpte(*(l3ep)))) +#define l4e_read(l4ep) \ + l4e_from_intpte(read_atomic(&l4e_get_intpte(*(l4ep)))) =20 /* Write a pte atomically to memory. */ #define l1e_write(l1ep, l1e) \ diff --git a/xen/arch/x86/include/asm/x86_64/page.h b/xen/arch/x86/include/= asm/x86_64/page.h index 03fcce61c052..465a70731214 100644 --- a/xen/arch/x86/include/asm/x86_64/page.h +++ b/xen/arch/x86/include/asm/x86_64/page.h @@ -69,8 +69,6 @@ typedef l4_pgentry_t root_pgentry_t; =20 #endif /* !__ASSEMBLY__ */ =20 -#define pte_read_atomic(ptep) read_atomic(ptep) - /* Given a virtual address, get an entry offset into a linear page table. = */ #define l1_linear_offset(_a) (((_a) & VADDR_MASK) >> L1_PAGETABLE_SHIFT) #define l2_linear_offset(_a) (((_a) & VADDR_MASK) >> L2_PAGETABLE_SHIFT) diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index fab2de5fae27..6ffacab341ad 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -2147,7 +2147,7 @@ static int mod_l1_entry(l1_pgentry_t *pl1e, l1_pgentr= y_t nl1e, struct vcpu *pt_vcpu, struct domain *pg_dom) { bool preserve_ad =3D (cmd =3D=3D MMU_PT_UPDATE_PRESERVE_AD); - l1_pgentry_t ol1e =3D l1e_read_atomic(pl1e); + l1_pgentry_t ol1e =3D l1e_read(pl1e); struct domain *pt_dom =3D pt_vcpu->domain; int rc =3D 0; =20 @@ -2270,7 +2270,7 @@ static int mod_l2_entry(l2_pgentry_t *pl2e, return -EPERM; } =20 - ol2e =3D l2e_read_atomic(pl2e); + ol2e =3D l2e_read(pl2e); =20 if ( l2e_get_flags(nl2e) & _PAGE_PRESENT ) { @@ -2332,7 +2332,7 @@ static int mod_l3_entry(l3_pgentry_t *pl3e, if ( pgentry_ptr_to_slot(pl3e) >=3D 3 && is_pv_32bit_domain(d) ) return -EINVAL; =20 - ol3e =3D l3e_read_atomic(pl3e); + ol3e =3D l3e_read(pl3e); =20 if ( l3e_get_flags(nl3e) & _PAGE_PRESENT ) { @@ -2394,7 +2394,7 @@ static int mod_l4_entry(l4_pgentry_t *pl4e, return -EINVAL; } =20 - ol4e =3D l4e_read_atomic(pl4e); + ol4e =3D l4e_read(pl4e); =20 if ( l4e_get_flags(nl4e) & _PAGE_PRESENT ) { @@ -5925,7 +5925,7 @@ void init_or_livepatch modify_xen_mappings_lite( while ( v < e ) { l2_pgentry_t *pl2e =3D &l2_xenmap[l2_table_offset(v)]; - l2_pgentry_t l2e =3D l2e_read_atomic(pl2e); + l2_pgentry_t l2e =3D l2e_read(pl2e); unsigned int l2f =3D l2e_get_flags(l2e); =20 ASSERT(l2f & _PAGE_PRESENT); @@ -5947,7 +5947,7 @@ void init_or_livepatch modify_xen_mappings_lite( while ( v < e ) { l1_pgentry_t *pl1e =3D &pl1t[l1_table_offset(v)]; - l1_pgentry_t l1e =3D l1e_read_atomic(pl1e); + l1_pgentry_t l1e =3D l1e_read(pl1e); unsigned int l1f =3D l1e_get_flags(l1e); =20 ASSERT(l1f & _PAGE_PRESENT); diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index ee91fc56b125..b4fb95917023 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1450,7 +1450,7 @@ static enum pf_type __page_fault_type(unsigned long a= ddr, mfn =3D cr3 >> PAGE_SHIFT; =20 l4t =3D map_domain_page(_mfn(mfn)); - l4e =3D l4e_read_atomic(&l4t[l4_table_offset(addr)]); + l4e =3D l4e_read(&l4t[l4_table_offset(addr)]); mfn =3D l4e_get_pfn(l4e); unmap_domain_page(l4t); if ( ((l4e_get_flags(l4e) & required_flags) !=3D required_flags) || @@ -1459,7 +1459,7 @@ static enum pf_type __page_fault_type(unsigned long a= ddr, page_user &=3D l4e_get_flags(l4e); =20 l3t =3D map_domain_page(_mfn(mfn)); - l3e =3D l3e_read_atomic(&l3t[l3_table_offset(addr)]); + l3e =3D l3e_read(&l3t[l3_table_offset(addr)]); mfn =3D l3e_get_pfn(l3e); unmap_domain_page(l3t); if ( ((l3e_get_flags(l3e) & required_flags) !=3D required_flags) || @@ -1470,7 +1470,7 @@ static enum pf_type __page_fault_type(unsigned long a= ddr, goto leaf; =20 l2t =3D map_domain_page(_mfn(mfn)); - l2e =3D l2e_read_atomic(&l2t[l2_table_offset(addr)]); + l2e =3D l2e_read(&l2t[l2_table_offset(addr)]); mfn =3D l2e_get_pfn(l2e); unmap_domain_page(l2t); if ( ((l2e_get_flags(l2e) & required_flags) !=3D required_flags) || @@ -1481,7 +1481,7 @@ static enum pf_type __page_fault_type(unsigned long a= ddr, goto leaf; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722007913800116600 The PVH dom0 builder doesn't switch page tables and has no need to run with SMAP disabled. Put the SMAP disabling close to the code region where it's necessary, as it then becomes obvious why switch_cr3_cr4() is required instead of write_ptbase(). Note removing SMAP from cr4_pv32_mask is not required, as we never jump into guest context, and hence updating the value of cr4_pv32_mask is not relevan= t. Signed-off-by: Roger Pau Monn=C3=A9 Reviewed-by: Jan Beulich --- xen/arch/x86/pv/dom0_build.c | 13 ++++++++++--- xen/arch/x86/setup.c | 17 ----------------- 2 files changed, 10 insertions(+), 20 deletions(-) diff --git a/xen/arch/x86/pv/dom0_build.c b/xen/arch/x86/pv/dom0_build.c index d8043fa58a27..41772dbe80bf 100644 --- a/xen/arch/x86/pv/dom0_build.c +++ b/xen/arch/x86/pv/dom0_build.c @@ -370,6 +370,7 @@ int __init dom0_construct_pv(struct domain *d, unsigned long alloc_epfn; unsigned long initrd_pfn =3D -1, initrd_mfn =3D 0; unsigned long count; + unsigned long cr4; struct page_info *page =3D NULL; unsigned int flush_flags =3D 0; start_info_t *si; @@ -814,8 +815,14 @@ int __init dom0_construct_pv(struct domain *d, /* Set up CR3 value for switch_cr3_cr4(). */ update_cr3(v); =20 + /* + * Temporarily clear SMAP in CR4 to allow user-accesses when running w= ith + * the dom0 page-tables. Cache the value of CR4 so it can be restored. + */ + cr4 =3D read_cr4(); + /* We run on dom0's page tables for the final part of the build proces= s. */ - switch_cr3_cr4(cr3_pa(v->arch.cr3), read_cr4()); + switch_cr3_cr4(cr3_pa(v->arch.cr3), cr4 & ~X86_CR4_SMAP); mapcache_override_current(v); =20 /* Copy the OS image and free temporary buffer. */ @@ -836,7 +843,7 @@ int __init dom0_construct_pv(struct domain *d, (parms.virt_hypercall >=3D v_end) ) { mapcache_override_current(NULL); - switch_cr3_cr4(current->arch.cr3, read_cr4()); + switch_cr3_cr4(current->arch.cr3, cr4); printk("Invalid HYPERCALL_PAGE field in ELF notes.\n"); return -EINVAL; } @@ -978,7 +985,7 @@ int __init dom0_construct_pv(struct domain *d, =20 /* Return to idle domain's page tables. */ mapcache_override_current(NULL); - switch_cr3_cr4(current->arch.cr3, read_cr4()); + switch_cr3_cr4(current->arch.cr3, cr4); =20 update_domain_wallclock_time(d); =20 diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index eee20bb1753c..bc387d96b519 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -955,26 +955,9 @@ static struct domain *__init create_dom0(const module_= t *image, } } =20 - /* - * Temporarily clear SMAP in CR4 to allow user-accesses in construct_d= om0(). - * This saves a large number of corner cases interactions with - * copy_from_user(). - */ - if ( cpu_has_smap ) - { - cr4_pv32_mask &=3D ~X86_CR4_SMAP; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722007919573116600 The idle_pg_table L4 is cloned to create all the other L4 Xen uses, and hen= ce it shouldn't be modified once further L4 are created. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/mm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 6ffacab341ad..01380fd82c9d 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -5023,6 +5023,12 @@ static l3_pgentry_t *virt_to_xen_l3e(unsigned long v) mfn_t l3mfn; l3_pgentry_t *l3t =3D alloc_mapped_pagetable(&l3mfn); =20 + /* + * dom0 is build at smp_boot, at which point we already create new= L4s + * based on idle_pg_table. + */ + BUG_ON(system_state >=3D SYS_STATE_smp_boot); + if ( !l3t ) return NULL; UNMAP_DOMAIN_PAGE(l3t); --=20 2.45.2 From nobody Thu Dec 26 22:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Fri, 26 Jul 2024 08:31:37 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH 05/22] x86/mm: make virt_to_xen_l1e() static Date: Fri, 26 Jul 2024 17:21:49 +0200 Message-ID: <20240726152206.28411-6-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722007925572116600 There are no callers outside the translation unit where it's defined, so ma= ke the function static. No functional change intended. Signed-off-by: Roger Pau Monn=C3=A9 Acked-by: Andrew Cooper --- xen/arch/x86/include/asm/mm.h | 2 -- xen/arch/x86/mm.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/xen/arch/x86/include/asm/mm.h b/xen/arch/x86/include/asm/mm.h index 98b66edaca5e..b3853ae734fa 100644 --- a/xen/arch/x86/include/asm/mm.h +++ b/xen/arch/x86/include/asm/mm.h @@ -567,8 +567,6 @@ mfn_t alloc_xen_pagetable(void); void free_xen_pagetable(mfn_t mfn); void *alloc_mapped_pagetable(mfn_t *pmfn); =20 -l1_pgentry_t *virt_to_xen_l1e(unsigned long v); - int __sync_local_execstate(void); =20 /* Arch-specific portion of memory_op hypercall. */ diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 01380fd82c9d..ca3d116b0e05 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -5087,7 +5087,7 @@ static l2_pgentry_t *virt_to_xen_l2e(unsigned long v) return map_l2t_from_l3e(l3e) + l2_table_offset(v); } =20 -l1_pgentry_t *virt_to_xen_l1e(unsigned long v) +static l1_pgentry_t *virt_to_xen_l1e(unsigned long v) { l2_pgentry_t *pl2e, l2e; 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Fri, 26 Jul 2024 08:31:39 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH 06/22] x86/mm: introduce a local domain variable to write_ptbase() Date: Fri, 26 Jul 2024 17:21:50 +0200 Message-ID: <20240726152206.28411-7-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722007919572116600 This reduces the repeated accessing of v->domain. No functional change intended. Signed-off-by: Roger Pau Monn=C3=A9 Acked-by: Andrew Cooper --- xen/arch/x86/mm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index ca3d116b0e05..a792a300a866 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -517,13 +517,14 @@ void make_cr3(struct vcpu *v, mfn_t mfn) =20 void write_ptbase(struct vcpu *v) { + const struct domain *d =3D v->domain; struct cpu_info *cpu_info =3D get_cpu_info(); unsigned long new_cr4; =20 - new_cr4 =3D (is_pv_vcpu(v) && !is_idle_vcpu(v)) + new_cr4 =3D (is_pv_domain(d) && !is_idle_domain(d)) ? pv_make_cr4(v) : mmu_cr4_features; =20 - if ( is_pv_vcpu(v) && v->domain->arch.pv.xpti ) + if ( is_pv_domain(d) && d->arch.pv.xpti ) { cpu_info->root_pgt_changed =3D true; cpu_info->pv_cr3 =3D __pa(this_cpu(root_pgt)); --=20 2.45.2 From nobody Thu Dec 26 22:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Fri, 26 Jul 2024 08:31:41 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH 07/22] x86/spec-ctrl: initialize per-domain XPTI in spec_ctrl_init_domain() Date: Fri, 26 Jul 2024 17:21:51 +0200 Message-ID: <20240726152206.28411-8-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722007925576116600 XPTI being a speculation mitigation feels better to be initialized in spec_ctrl_init_domain(). No functional change intended, although the call to spec_ctrl_init_domain()= in arch_domain_create() needs to be moved ahead of pv_domain_initialise() for d->->arch.pv.xpti to be correctly set. Move it ahead of most of the initialization functions, since spec_ctrl_init_domain() doesn't depend on any member in the struct domain b= eing set. Signed-off-by: Roger Pau Monn=C3=A9 Reviewed-by: Jan Beulich --- xen/arch/x86/domain.c | 4 ++-- xen/arch/x86/pv/domain.c | 2 -- xen/arch/x86/spec_ctrl.c | 4 ++++ 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index ccadfe0c9e70..3d3c14dbb5ae 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -842,6 +842,8 @@ int arch_domain_create(struct domain *d, is_pv_domain(d) ? __HYPERVISOR_COMPAT_VIRT_START : ~0u; #endif =20 + spec_ctrl_init_domain(d); + if ( (rc =3D paging_domain_init(d)) !=3D 0 ) goto fail; paging_initialised =3D true; @@ -908,8 +910,6 @@ int arch_domain_create(struct domain *d, =20 d->arch.msr_relaxed =3D config->arch.misc_flags & XEN_X86_MSR_RELAXED; =20 - spec_ctrl_init_domain(d); - return 0; =20 fail: diff --git a/xen/arch/x86/pv/domain.c b/xen/arch/x86/pv/domain.c index 2a445bb17b99..86b74fb372d5 100644 --- a/xen/arch/x86/pv/domain.c +++ b/xen/arch/x86/pv/domain.c @@ -383,8 +383,6 @@ int pv_domain_initialise(struct domain *d) =20 d->arch.ctxt_switch =3D &pv_csw; =20 - d->arch.pv.xpti =3D is_hardware_domain(d) ? opt_xpti_hwdom : opt_xpti_= domu; - if ( !is_pv_32bit_domain(d) && use_invpcid && cpu_has_pcid ) switch ( ACCESS_ONCE(opt_pcid) ) { diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 40f6ae017010..5dc7a17b9354 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -1769,6 +1769,10 @@ void spec_ctrl_init_domain(struct domain *d) (ibpb ? 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722007927586116600 In preparation for the function being called from contexts where no domain = is present. No functional change intended. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/include/asm/mm.h | 4 +++- xen/arch/x86/mm.c | 24 +++++++++++++----------- xen/arch/x86/mm/hap/hap.c | 3 ++- xen/arch/x86/mm/shadow/hvm.c | 3 ++- xen/arch/x86/mm/shadow/multi.c | 7 +++++-- xen/arch/x86/pv/dom0_build.c | 3 ++- xen/arch/x86/pv/domain.c | 3 ++- 7 files changed, 29 insertions(+), 18 deletions(-) diff --git a/xen/arch/x86/include/asm/mm.h b/xen/arch/x86/include/asm/mm.h index b3853ae734fa..076e7009dc99 100644 --- a/xen/arch/x86/include/asm/mm.h +++ b/xen/arch/x86/include/asm/mm.h @@ -375,7 +375,9 @@ int devalidate_page(struct page_info *page, unsigned lo= ng type, =20 void init_xen_pae_l2_slots(l2_pgentry_t *l2t, const struct domain *d); void init_xen_l4_slots(l4_pgentry_t *l4t, mfn_t l4mfn, - const struct domain *d, mfn_t sl4mfn, bool ro_mpt); + mfn_t sl4mfn, const struct page_info *perdomain_l3, + bool ro_mpt, bool maybe_compat, bool short_directma= p); + bool fill_ro_mpt(mfn_t mfn); void zap_ro_mpt(mfn_t mfn); =20 diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index a792a300a866..c01b6712143e 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -1645,14 +1645,9 @@ static int promote_l3_table(struct page_info *page) * extended directmap. */ void init_xen_l4_slots(l4_pgentry_t *l4t, mfn_t l4mfn, - const struct domain *d, mfn_t sl4mfn, bool ro_mpt) + mfn_t sl4mfn, const struct page_info *perdomain_l3, + bool ro_mpt, bool maybe_compat, bool short_directma= p) { - /* - * PV vcpus need a shortened directmap. HVM and Idle vcpus get the fu= ll - * directmap. - */ - bool short_directmap =3D !paging_mode_external(d); - /* Slot 256: RO M2P (if applicable). */ l4t[l4_table_offset(RO_MPT_VIRT_START)] =3D ro_mpt ? idle_pg_table[l4_table_offset(RO_MPT_VIRT_START)] @@ -1673,13 +1668,14 @@ void init_xen_l4_slots(l4_pgentry_t *l4t, mfn_t l4m= fn, l4e_from_mfn(sl4mfn, __PAGE_HYPERVISOR_RW); =20 /* Slot 260: Per-domain mappings. */ - l4t[l4_table_offset(PERDOMAIN_VIRT_START)] =3D - l4e_from_page(d->arch.perdomain_l3_pg, __PAGE_HYPERVISOR_RW); + if ( perdomain_l3 ) + l4t[l4_table_offset(PERDOMAIN_VIRT_START)] =3D + l4e_from_page(perdomain_l3, __PAGE_HYPERVISOR_RW); =20 /* Slot 4: Per-domain mappings mirror. */ BUILD_BUG_ON(IS_ENABLED(CONFIG_PV32) && !l4_table_offset(PERDOMAIN_ALT_VIRT_START)); - if ( !is_pv_64bit_domain(d) ) + if ( perdomain_l3 && maybe_compat ) l4t[l4_table_offset(PERDOMAIN_ALT_VIRT_START)] =3D l4t[l4_table_offset(PERDOMAIN_VIRT_START)]; =20 @@ -1710,6 +1706,10 @@ void init_xen_l4_slots(l4_pgentry_t *l4t, mfn_t l4mf= n, else #endif { + /* + * PV vcpus need a shortened directmap. HVM and Idle vcpus get th= e full + * directmap. + */ unsigned int slots =3D (short_directmap ? ROOT_PAGETABLE_PV_XEN_SLOTS : ROOT_PAGETABLE_XEN_SLOTS); @@ -1830,7 +1830,9 @@ static int promote_l4_table(struct page_info *page) if ( !rc ) { init_xen_l4_slots(pl4e, l4mfn, - d, INVALID_MFN, VM_ASSIST(d, m2p_strict)); + INVALID_MFN, d->arch.perdomain_l3_pg, + VM_ASSIST(d, m2p_strict), !is_pv_64bit_domain(d), + true); atomic_inc(&d->arch.pv.nr_l4_pages); } unmap_domain_page(pl4e); diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index d2011fde2462..c8514ca0e917 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -402,7 +402,8 @@ static mfn_t hap_make_monitor_table(struct vcpu *v) m4mfn =3D page_to_mfn(pg); l4e =3D map_domain_page(m4mfn); =20 - init_xen_l4_slots(l4e, m4mfn, d, INVALID_MFN, false); + init_xen_l4_slots(l4e, m4mfn, INVALID_MFN, d->arch.perdomain_l3_pg, + false, true, false); unmap_domain_page(l4e); =20 return m4mfn; diff --git a/xen/arch/x86/mm/shadow/hvm.c b/xen/arch/x86/mm/shadow/hvm.c index c16f3b3adf32..93922a71e511 100644 --- a/xen/arch/x86/mm/shadow/hvm.c +++ b/xen/arch/x86/mm/shadow/hvm.c @@ -758,7 +758,8 @@ mfn_t sh_make_monitor_table(const struct vcpu *v, unsig= ned int shadow_levels) * shadow-linear mapping will either be inserted below when creating * lower level monitor tables, or later in sh_update_cr3(). */ - init_xen_l4_slots(l4e, m4mfn, d, INVALID_MFN, false); + init_xen_l4_slots(l4e, m4mfn, INVALID_MFN, d->arch.perdomain_l3_pg, + false, true, false); =20 if ( shadow_levels < 4 ) { diff --git a/xen/arch/x86/mm/shadow/multi.c b/xen/arch/x86/mm/shadow/multi.c index 376f6823cd44..0def0c073ca8 100644 --- a/xen/arch/x86/mm/shadow/multi.c +++ b/xen/arch/x86/mm/shadow/multi.c @@ -973,8 +973,11 @@ sh_make_shadow(struct vcpu *v, mfn_t gmfn, u32 shadow_= type) =20 BUILD_BUG_ON(sizeof(l4_pgentry_t) !=3D sizeof(shadow_l4e_t)); =20 - init_xen_l4_slots(l4t, gmfn, d, smfn, (!is_pv_32bit_domain(d) = && - VM_ASSIST(d, m2p_strict= ))); + init_xen_l4_slots(l4t, gmfn, smfn, + d->arch.perdomain_l3_pg, + (!is_pv_32bit_domain(d) && + VM_ASSIST(d, m2p_strict)), + !is_pv_64bit_domain(d), true); unmap_domain_page(l4t); } break; diff --git a/xen/arch/x86/pv/dom0_build.c b/xen/arch/x86/pv/dom0_build.c index 41772dbe80bf..6a6689f402bb 100644 --- a/xen/arch/x86/pv/dom0_build.c +++ b/xen/arch/x86/pv/dom0_build.c @@ -711,7 +711,8 @@ int __init dom0_construct_pv(struct domain *d, l4start =3D l4tab =3D __va(mpt_alloc); mpt_alloc +=3D PAGE_SIZE; clear_page(l4tab); init_xen_l4_slots(l4tab, _mfn(virt_to_mfn(l4start)), - d, INVALID_MFN, true); + INVALID_MFN, d->arch.perdomain_l3_pg, + true, !is_pv_64bit_domain(d), true); v->arch.guest_table =3D pagetable_from_paddr(__pa(l4start)); } else diff --git a/xen/arch/x86/pv/domain.c b/xen/arch/x86/pv/domain.c index 86b74fb372d5..6ff71f14a2f2 100644 --- a/xen/arch/x86/pv/domain.c +++ b/xen/arch/x86/pv/domain.c @@ -124,7 +124,8 @@ static int setup_compat_l4(struct vcpu *v) mfn =3D page_to_mfn(pg); l4tab =3D map_domain_page(mfn); clear_page(l4tab); - init_xen_l4_slots(l4tab, mfn, v->domain, INVALID_MFN, false); + init_xen_l4_slots(l4tab, mfn, INVALID_MFN, v->domain->arch.perdomain_l= 3_pg, + false, true, true); unmap_domain_page(l4tab); =20 /* This page needs to look like a pagetable so that it can be shadowed= */ --=20 2.45.2 From nobody Thu Dec 26 22:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Fri, 26 Jul 2024 08:31:46 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH 09/22] x86/pv: untie issuing FLUSH_ROOT_PGTBL from XPTI Date: Fri, 26 Jul 2024 17:21:53 +0200 Message-ID: <20240726152206.28411-10-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722007933613116600 The current logic gates issuing flush TLB requests with the FLUSH_ROOT_PGTBL flag to XPTI being enabled. In preparation for FLUSH_ROOT_PGTBL also being needed when not using XPTI, untie it from the xpti domain boolean and instead introduce a new flush_roo= t_pt field. No functional change intended, as flush_root_pt =3D=3D xpti. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/include/asm/domain.h | 2 ++ xen/arch/x86/include/asm/flushtlb.h | 2 +- xen/arch/x86/mm.c | 2 +- xen/arch/x86/pv/domain.c | 2 ++ 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/d= omain.h index f5daeb182baa..9dd2e047f4de 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -283,6 +283,8 @@ struct pv_domain bool pcid; /* Mitigate L1TF with shadow/crashing? */ bool check_l1tf; + /* Issue FLUSH_ROOT_PGTBL for root page-table changes. */ + bool flush_root_pt; =20 /* map_domain_page() mapping cache. */ struct mapcache_domain mapcache; diff --git a/xen/arch/x86/include/asm/flushtlb.h b/xen/arch/x86/include/asm= /flushtlb.h index bb0ad58db49b..1b98d03decdc 100644 --- a/xen/arch/x86/include/asm/flushtlb.h +++ b/xen/arch/x86/include/asm/flushtlb.h @@ -177,7 +177,7 @@ void flush_area_mask(const cpumask_t *mask, const void = *va, =20 #define flush_root_pgtbl_domain(d) \ { \ - if ( is_pv_domain(d) && (d)->arch.pv.xpti ) \ + if ( is_pv_domain(d) && (d)->arch.pv.flush_root_pt ) \ flush_mask((d)->dirty_cpumask, FLUSH_ROOT_PGTBL); \ } =20 diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index c01b6712143e..a1ac7bdc5b44 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -4167,7 +4167,7 @@ long do_mmu_update( cmd =3D=3D MMU_PT_UPDATE_PRESERVE_AD= , v); if ( !rc ) flush_linear_pt =3D true; - if ( !rc && pt_owner->arch.pv.xpti ) + if ( !rc && pt_owner->arch.pv.flush_root_pt ) { bool local_in_use =3D false; =20 diff --git a/xen/arch/x86/pv/domain.c b/xen/arch/x86/pv/domain.c index 6ff71f14a2f2..46ee10a8a4c2 100644 --- a/xen/arch/x86/pv/domain.c +++ b/xen/arch/x86/pv/domain.c @@ -384,6 +384,8 @@ int pv_domain_initialise(struct domain *d) =20 d->arch.ctxt_switch =3D &pv_csw; =20 + d->arch.pv.flush_root_pt =3D d->arch.pv.xpti; + if ( !is_pv_32bit_domain(d) && use_invpcid && cpu_has_pcid ) switch ( ACCESS_ONCE(opt_pcid) ) { --=20 2.45.2 From nobody Thu Dec 26 22:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Fri, 26 Jul 2024 08:31:48 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH 10/22] x86/mm: move FLUSH_ROOT_PGTBL handling before TLB flush Date: Fri, 26 Jul 2024 17:21:54 +0200 Message-ID: <20240726152206.28411-11-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722007929585116600 Move the handling of FLUSH_ROOT_PGTBL in flush_area_local() ahead of the lo= gic that does the TLB flushing, in preparation for further changes requiring the TLB flush to be strictly done after having handled FLUSH_ROOT_PGTBL. No functional change intended. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/flushtlb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c index 18748b2bc805..fd5ed16ffb57 100644 --- a/xen/arch/x86/flushtlb.c +++ b/xen/arch/x86/flushtlb.c @@ -191,6 +191,9 @@ unsigned int flush_area_local(const void *va, unsigned = int flags) { unsigned int order =3D (flags - 1) & FLUSH_ORDER_MASK; =20 + if ( flags & FLUSH_ROOT_PGTBL ) + get_cpu_info()->root_pgt_changed =3D true; + if ( flags & (FLUSH_TLB|FLUSH_TLB_GLOBAL) ) { if ( order =3D=3D 0 ) @@ -254,9 +257,6 @@ unsigned int flush_area_local(const void *va, unsigned = int flags) } } =20 - if ( flags & FLUSH_ROOT_PGTBL ) - get_cpu_info()->root_pgt_changed =3D true; - return flags; } =20 --=20 2.45.2 From nobody Thu Dec 26 22:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Fri, 26 Jul 2024 08:31:50 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH 11/22] x86/mm: split setup of the per-domain slot on context switch Date: Fri, 26 Jul 2024 17:21:55 +0200 Message-ID: <20240726152206.28411-12-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722007937641116600 It's currently only used for XPTI. Move the code to a separate helper in preparation for it gaining more logic. While there switch to using l4e_write(): in the current context the L4 is not active when modified, but that could change. No functional change intended. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/domain.c | 4 +--- xen/arch/x86/include/asm/mm.h | 3 +++ xen/arch/x86/mm.c | 7 +++++++ 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 3d3c14dbb5ae..9cfcf0dc63f3 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1918,9 +1918,7 @@ void cf_check paravirt_ctxt_switch_to(struct vcpu *v) root_pgentry_t *root_pgt =3D this_cpu(root_pgt); =20 if ( root_pgt ) - root_pgt[root_table_offset(PERDOMAIN_VIRT_START)] =3D - l4e_from_page(v->domain->arch.perdomain_l3_pg, - __PAGE_HYPERVISOR_RW); + setup_perdomain_slot(v, root_pgt); =20 if ( unlikely(v->arch.dr7 & DR7_ACTIVE_MASK) ) activate_debugregs(v); diff --git a/xen/arch/x86/include/asm/mm.h b/xen/arch/x86/include/asm/mm.h index 076e7009dc99..2c309f7b1444 100644 --- a/xen/arch/x86/include/asm/mm.h +++ b/xen/arch/x86/include/asm/mm.h @@ -630,4 +630,7 @@ static inline bool arch_mfns_in_directmap(unsigned long= mfn, unsigned long nr) return (mfn + nr) <=3D (virt_to_mfn(eva - 1) + 1); } =20 +/* Setup the per-domain slot in the root page table pointer. */ +void setup_perdomain_slot(const struct vcpu *v, root_pgentry_t *root_pgt); + #endif /* __ASM_X86_MM_H__ */ diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index a1ac7bdc5b44..35e929057d21 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -6362,6 +6362,13 @@ unsigned long get_upper_mfn_bound(void) return min(max_mfn, 1UL << (paddr_bits - PAGE_SHIFT)) - 1; } =20 +void setup_perdomain_slot(const struct vcpu *v, root_pgentry_t *root_pgt) +{ + l4e_write(&root_pgt[root_table_offset(PERDOMAIN_VIRT_START)], + l4e_from_page(v->domain->arch.perdomain_l3_pg, + __PAGE_HYPERVISOR_RW)); +} + static void __init __maybe_unused build_assertions(void) { /* --=20 2.45.2 From nobody Thu Dec 26 22:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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Fri, 26 Jul 2024 08:31:52 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH 12/22] x86/spec-ctrl: introduce Address Space Isolation command line option Date: Fri, 26 Jul 2024 17:21:56 +0200 Message-ID: <20240726152206.28411-13-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722007937679116600 No functional change, as the option is not used. Introduced new so newly added functionality is keyed on the option being enabled, even if the feature is non-functional. Signed-off-by: Roger Pau Monn=C3=A9 --- docs/misc/xen-command-line.pandoc | 15 ++++-- xen/arch/x86/include/asm/domain.h | 3 ++ xen/arch/x86/include/asm/spec_ctrl.h | 2 + xen/arch/x86/spec_ctrl.c | 74 +++++++++++++++++++++++++--- 4 files changed, 81 insertions(+), 13 deletions(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line= .pandoc index 98a45211556b..0ddc330428d9 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -2387,7 +2387,7 @@ By default SSBD will be mitigated at runtime (i.e `ss= bd=3Druntime`). =20 ### spec-ctrl (x86) > `=3D List of [ , xen=3D, {pv,hvm}=3D, -> {msr-sc,rsb,verw,{ibpb,bhb}-entry}=3D|{pv,hvm}=3D, +> {msr-sc,rsb,verw,{ibpb,bhb}-entry,asi}=3D|{pv,hvm}=3D= , > bti-thunk=3Dretpoline|lfence|jmp,bhb-seq=3Dshort|tsx|long, > {ibrs,ibpb,ssbd,psfd, > eager-fpu,l1d-flush,branch-harden,srb-lock, @@ -2414,10 +2414,10 @@ in place for guests to use. =20 Use of a positive boolean value for either of these options is invalid. =20 -The `pv=3D`, `hvm=3D`, `msr-sc=3D`, `rsb=3D`, `verw=3D`, `ibpb-entry=3D` a= nd `bhb-entry=3D` -options offer fine grained control over the primitives by Xen. These impa= ct -Xen's ability to protect itself, and/or Xen's ability to virtualise support -for guests to use. +The `pv=3D`, `hvm=3D`, `msr-sc=3D`, `rsb=3D`, `verw=3D`, `ibpb-entry=3D`, = `bhb-entry=3D` and +`asi=3D` options offer fine grained control over the primitives by Xen. T= hese +impact Xen's ability to protect itself, and/or Xen's ability to virtualise +support for guests to use. =20 * `pv=3D` and `hvm=3D` offer control over all suboptions for PV and HVM gu= ests respectively. @@ -2449,6 +2449,11 @@ for guests to use. is not available (see `bhi-dis-s`). The choice of scrubbing sequence ca= n be selected using the `bhb-seq=3D` option. If it is necessary to protect d= om0 too, boot with `spec-ctrl=3Dbhb-entry`. +* `asi=3D` offers control over whether the hypervisor will engage in Addre= ss + Space Isolation, by not having sensitive information mapped in the VMM + page-tables. Not having sensitive information on the page-tables avoids + having to perform some mitigations for speculative attacks when + context-switching to the hypervisor. =20 If Xen was compiled with `CONFIG_INDIRECT_THUNK` support, `bti-thunk=3D` c= an be used to select which of the thunks gets patched into the diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/d= omain.h index 9dd2e047f4de..8c366be8c75f 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -458,6 +458,9 @@ struct arch_domain /* Don't unconditionally inject #GP for unhandled MSRs. */ bool msr_relaxed; =20 + /* Run the guest without sensitive information in the VMM page-tables.= */ + bool asi; + /* Emulated devices enabled bitmap. */ uint32_t emulation_flags; } __cacheline_aligned; diff --git a/xen/arch/x86/include/asm/spec_ctrl.h b/xen/arch/x86/include/as= m/spec_ctrl.h index 72347ef2b959..39963c004312 100644 --- a/xen/arch/x86/include/asm/spec_ctrl.h +++ b/xen/arch/x86/include/asm/spec_ctrl.h @@ -88,6 +88,8 @@ extern uint8_t default_scf; =20 extern int8_t opt_xpti_hwdom, opt_xpti_domu; =20 +extern int8_t opt_asi_pv, opt_asi_hwdom, opt_asi_hvm; + extern bool cpu_has_bug_l1tf; extern int8_t opt_pv_l1tf_hwdom, opt_pv_l1tf_domu; =20 diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 5dc7a17b9354..2e403aad791c 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -84,6 +84,11 @@ static bool __ro_after_init opt_verw_mmio; static int8_t __initdata opt_gds_mit =3D -1; static int8_t __initdata opt_div_scrub =3D -1; =20 +/* Address Space Isolation for PV/HVM. */ +int8_t __ro_after_init opt_asi_pv =3D -1; +int8_t __ro_after_init opt_asi_hwdom =3D -1; +int8_t __ro_after_init opt_asi_hvm =3D -1; + static int __init cf_check parse_spec_ctrl(const char *s) { const char *ss; @@ -143,6 +148,10 @@ static int __init cf_check parse_spec_ctrl(const char = *s) opt_unpriv_mmio =3D false; opt_gds_mit =3D 0; opt_div_scrub =3D 0; + + opt_asi_pv =3D 0; + opt_asi_hwdom =3D 0; + opt_asi_hvm =3D 0; } else if ( val > 0 ) rc =3D -EINVAL; @@ -162,6 +171,7 @@ static int __init cf_check parse_spec_ctrl(const char *= s) opt_verw_pv =3D val; opt_ibpb_entry_pv =3D val; opt_bhb_entry_pv =3D val; + opt_asi_pv =3D val; } else if ( (val =3D parse_boolean("hvm", s, ss)) >=3D 0 ) { @@ -170,6 +180,7 @@ static int __init cf_check parse_spec_ctrl(const char *= s) opt_verw_hvm =3D val; opt_ibpb_entry_hvm =3D val; opt_bhb_entry_hvm =3D val; + opt_asi_hvm =3D val; } else if ( (val =3D parse_boolean("msr-sc", s, ss)) !=3D -1 ) { @@ -279,6 +290,27 @@ static int __init cf_check parse_spec_ctrl(const char = *s) break; } } + else if ( (val =3D parse_boolean("asi", s, ss)) !=3D -1 ) + { + switch ( val ) + { + case 0: + case 1: + opt_asi_pv =3D opt_asi_hwdom =3D opt_asi_hvm =3D val; + break; + + case -2: + s +=3D strlen("asi=3D"); + if ( (val =3D parse_boolean("pv", s, ss)) >=3D 0 ) + opt_asi_pv =3D val; + else if ( (val =3D parse_boolean("hvm", s, ss)) >=3D 0 ) + opt_asi_hvm =3D val; + else + default: + rc =3D -EINVAL; + break; + } + } =20 /* Xen's speculative sidechannel mitigation settings. */ else if ( !strncmp(s, "bti-thunk=3D", 10) ) @@ -378,6 +410,13 @@ int8_t __ro_after_init opt_xpti_domu =3D -1; =20 static __init void xpti_init_default(void) { + ASSERT(opt_asi_pv >=3D 0 && opt_asi_hwdom >=3D 0); + if ( (opt_xpti_hwdom =3D=3D 1 || opt_xpti_domu =3D=3D 1) && opt_asi_pv= =3D=3D 1 ) + { + printk(XENLOG_ERR + "XPTI is incompatible with Address Space Isolation - disabl= ing ASI\n"); + opt_asi_pv =3D 0; + } if ( (boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) = || cpu_has_rdcl_no ) { @@ -389,9 +428,9 @@ static __init void xpti_init_default(void) else { if ( opt_xpti_hwdom < 0 ) - opt_xpti_hwdom =3D 1; + opt_xpti_hwdom =3D !opt_asi_hwdom; if ( opt_xpti_domu < 0 ) - opt_xpti_domu =3D 1; + opt_xpti_domu =3D !opt_asi_pv; } } =20 @@ -630,12 +669,13 @@ static void __init print_details(enum ind_thunk thunk) * mitigation support for guests. */ #ifdef CONFIG_HVM - printk(" Support for HVM VMs:%s%s%s%s%s%s%s%s\n", + printk(" Support for HVM VMs:%s%s%s%s%s%s%s%s%s\n", (boot_cpu_has(X86_FEATURE_SC_MSR_HVM) || boot_cpu_has(X86_FEATURE_SC_RSB_HVM) || boot_cpu_has(X86_FEATURE_IBPB_ENTRY_HVM) || opt_bhb_entry_hvm || amd_virt_spec_ctrl || - opt_eager_fpu || opt_verw_hvm) ? "" : = " None", + opt_eager_fpu || opt_verw_hvm || + opt_asi_hvm) ? "" : = " None", boot_cpu_has(X86_FEATURE_SC_MSR_HVM) ? " MSR_SPEC_CTRL" : = "", (boot_cpu_has(X86_FEATURE_SC_MSR_HVM) || amd_virt_spec_ctrl) ? " MSR_VIRT_SPEC_CTR= L" : "", @@ -643,22 +683,24 @@ static void __init print_details(enum ind_thunk thunk) opt_eager_fpu ? " EAGER_FPU" : = "", opt_verw_hvm ? " VERW" : = "", boot_cpu_has(X86_FEATURE_IBPB_ENTRY_HVM) ? " IBPB-entry" : = "", - opt_bhb_entry_hvm ? " BHB-entry" : = ""); + opt_bhb_entry_hvm ? " BHB-entry" : = "", + opt_asi_hvm ? " ASI" : = ""); =20 #endif #ifdef CONFIG_PV - printk(" Support for PV VMs:%s%s%s%s%s%s%s\n", + printk(" Support for PV VMs:%s%s%s%s%s%s%s%s\n", (boot_cpu_has(X86_FEATURE_SC_MSR_PV) || boot_cpu_has(X86_FEATURE_SC_RSB_PV) || boot_cpu_has(X86_FEATURE_IBPB_ENTRY_PV) || - opt_bhb_entry_pv || + opt_bhb_entry_pv || opt_asi_pv || opt_eager_fpu || opt_verw_pv) ? "" : = " None", boot_cpu_has(X86_FEATURE_SC_MSR_PV) ? " MSR_SPEC_CTRL" : = "", boot_cpu_has(X86_FEATURE_SC_RSB_PV) ? " RSB" : = "", opt_eager_fpu ? " EAGER_FPU" : = "", opt_verw_pv ? " VERW" : = "", boot_cpu_has(X86_FEATURE_IBPB_ENTRY_PV) ? " IBPB-entry" : = "", - opt_bhb_entry_pv ? " BHB-entry" : = ""); + opt_bhb_entry_pv ? " BHB-entry" : = "", + opt_asi_pv ? " ASI" : = ""); =20 printk(" XPTI (64-bit PV only): Dom0 %s, DomU %s (with%s PCID)\n", opt_xpti_hwdom ? "enabled" : "disabled", @@ -1773,6 +1815,9 @@ void spec_ctrl_init_domain(struct domain *d) if ( pv ) d->arch.pv.xpti =3D is_hardware_domain(d) ? opt_xpti_hwdom : opt_xpti_domu; + + d->arch.asi =3D is_hardware_domain(d) ? opt_asi_hwdom + : pv ? opt_asi_pv : opt_asi_hvm; } =20 void __init init_speculation_mitigations(void) @@ -2069,6 +2114,19 @@ void __init init_speculation_mitigations(void) hw_smt_enabled && default_xen_spec_ctrl ) setup_force_cpu_cap(X86_FEATURE_SC_MSR_IDLE); =20 + /* Disable ASI by default until feature is finished. */ + if ( opt_asi_pv =3D=3D -1 ) + opt_asi_pv =3D 0; + if ( opt_asi_hwdom =3D=3D -1 ) + opt_asi_hwdom =3D 0; + if ( opt_asi_hvm =3D=3D -1 ) + opt_asi_hvm =3D 0; + + if ( opt_asi_pv || opt_asi_hvm ) + warning_add( + "Address Space Isolation is not functional, this option is\n" + "intended to be used only for development purposes.\n"); + xpti_init_default(); =20 l1tf_calculations(); --=20 2.45.2 From nobody Thu Dec 26 22:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Fri, 26 Jul 2024 08:31:54 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH 13/22] x86/hvm: use a per-pCPU monitor table in HAP mode Date: Fri, 26 Jul 2024 17:21:57 +0200 Message-ID: <20240726152206.28411-14-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722007947717116600 Instead of allocating a monitor table for each vCPU when running in HVM HAP mode, use a per-pCPU monitor table, which gets the per-domain slot updated = on guest context switch. This limits the amount of memory used for HVM HAP monitor tables to the amo= unt of active pCPUs, rather than to the number of vCPUs. It also simplifies vC= PU allocation and teardown, since the monitor table handling is removed from there. Note the switch to using a per-CPU monitor table is done regardless of whet= her Address Space Isolation is enabled or not. Partly for the memory usage reduction, and also because it allows to simplify the VM tear down path by = not having to cleanup the per-vCPU monitor tables. Signed-off-by: Roger Pau Monn=C3=A9 --- Note the monitor table is not made static because uses outside of the file where it's defined will be added by further patches. --- xen/arch/x86/hvm/hvm.c | 60 ++++++++++++++++++++++++ xen/arch/x86/hvm/svm/svm.c | 5 ++ xen/arch/x86/hvm/vmx/vmcs.c | 1 + xen/arch/x86/hvm/vmx/vmx.c | 4 ++ xen/arch/x86/include/asm/hap.h | 1 - xen/arch/x86/include/asm/hvm/hvm.h | 8 ++++ xen/arch/x86/mm.c | 8 ++++ xen/arch/x86/mm/hap/hap.c | 75 ------------------------------ xen/arch/x86/mm/paging.c | 4 +- 9 files changed, 87 insertions(+), 79 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 7f4b627b1f5f..3f771bc65677 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -104,6 +104,54 @@ static const char __initconst warning_hvm_fep[] =3D static bool __initdata opt_altp2m_enabled; boolean_param("altp2m", opt_altp2m_enabled); =20 +DEFINE_PER_CPU(root_pgentry_t *, monitor_pgt); + +static int allocate_cpu_monitor_table(unsigned int cpu) +{ + root_pgentry_t *pgt =3D alloc_xenheap_page(); + + if ( !pgt ) + return -ENOMEM; + + clear_page(pgt); + + init_xen_l4_slots(pgt, _mfn(virt_to_mfn(pgt)), INVALID_MFN, NULL, + false, true, false); + + ASSERT(!per_cpu(monitor_pgt, cpu)); + per_cpu(monitor_pgt, cpu) =3D pgt; + + return 0; +} + +static void free_cpu_monitor_table(unsigned int cpu) +{ + root_pgentry_t *pgt =3D per_cpu(monitor_pgt, cpu); + + if ( !pgt ) + return; + + per_cpu(monitor_pgt, cpu) =3D NULL; + free_xenheap_page(pgt); +} + +void hvm_set_cpu_monitor_table(struct vcpu *v) +{ + root_pgentry_t *pgt =3D this_cpu(monitor_pgt); + + ASSERT(pgt); + + setup_perdomain_slot(v, pgt); + + make_cr3(v, _mfn(virt_to_mfn(pgt))); +} + +void hvm_clear_cpu_monitor_table(struct vcpu *v) +{ + /* Poison %cr3, it will be updated when the vCPU is scheduled. */ + make_cr3(v, INVALID_MFN); +} + static int cf_check cpu_callback( struct notifier_block *nfb, unsigned long action, void *hcpu) { @@ -113,6 +161,9 @@ static int cf_check cpu_callback( switch ( action ) { case CPU_UP_PREPARE: + rc =3D allocate_cpu_monitor_table(cpu); + if ( rc ) + break; rc =3D alternative_call(hvm_funcs.cpu_up_prepare, cpu); break; case CPU_DYING: @@ -121,6 +172,7 @@ static int cf_check cpu_callback( case CPU_UP_CANCELED: case CPU_DEAD: alternative_vcall(hvm_funcs.cpu_dead, cpu); + free_cpu_monitor_table(cpu); break; default: break; @@ -154,6 +206,7 @@ static bool __init hap_supported(struct hvm_function_ta= ble *fns) static int __init cf_check hvm_enable(void) { const struct hvm_function_table *fns =3D NULL; + int rc; =20 if ( cpu_has_vmx ) fns =3D start_vmx(); @@ -205,6 +258,13 @@ static int __init cf_check hvm_enable(void) =20 register_cpu_notifier(&cpu_nfb); =20 + rc =3D allocate_cpu_monitor_table(0); + if ( rc ) + { + printk(XENLOG_ERR "Error %d setting up HVM monitor page tables\n",= rc); + return rc; + } + return 0; } presmp_initcall(hvm_enable); diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 988250dbc154..a3fc033c0100 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -902,6 +902,8 @@ static void cf_check svm_ctxt_switch_from(struct vcpu *= v) if ( unlikely((read_efer() & EFER_SVME) =3D=3D 0) ) return; =20 + hvm_clear_cpu_monitor_table(v); + if ( !v->arch.fully_eager_fpu ) svm_fpu_leave(v); =20 @@ -957,6 +959,8 @@ static void cf_check svm_ctxt_switch_to(struct vcpu *v) ASSERT(v->domain->arch.cpuid->extd.virt_ssbd); amd_set_legacy_ssbd(true); } + + hvm_set_cpu_monitor_table(v); } =20 static void noreturn cf_check svm_do_resume(void) @@ -990,6 +994,7 @@ static void noreturn cf_check svm_do_resume(void) hvm_migrate_pirqs(v); /* Migrating to another ASID domain. Request a new ASID. */ hvm_asid_flush_vcpu(v); + hvm_update_host_cr3(v); } =20 if ( !vcpu_guestmode && !vlapic_hw_disabled(vlapic) ) diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 9b6dc51f36ab..5d67c8157825 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -1957,6 +1957,7 @@ void cf_check vmx_do_resume(void) v->arch.hvm.vmx.hostenv_migrated =3D 1; =20 hvm_asid_flush_vcpu(v); + hvm_update_host_cr3(v); } =20 debug_state =3D v->domain->debugger_attached diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index cbe91c679807..5863c57b2d4a 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -1153,6 +1153,8 @@ static void cf_check vmx_ctxt_switch_from(struct vcpu= *v) if ( unlikely(!this_cpu(vmxon)) ) return; =20 + hvm_clear_cpu_monitor_table(v); + if ( !v->is_running ) { /* @@ -1182,6 +1184,8 @@ static void cf_check vmx_ctxt_switch_to(struct vcpu *= v) =20 if ( v->domain->arch.hvm.pi_ops.flags & PI_CSW_TO ) vmx_pi_switch_to(v); + + hvm_set_cpu_monitor_table(v); } =20 =20 diff --git a/xen/arch/x86/include/asm/hap.h b/xen/arch/x86/include/asm/hap.h index f01ce73fb4f3..ae6760bc2bf5 100644 --- a/xen/arch/x86/include/asm/hap.h +++ b/xen/arch/x86/include/asm/hap.h @@ -24,7 +24,6 @@ int hap_domctl(struct domain *d, struct xen_domctl_shad= ow_op *sc, XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl); int hap_enable(struct domain *d, u32 mode); void hap_final_teardown(struct domain *d); -void hap_vcpu_teardown(struct vcpu *v); void hap_teardown(struct domain *d, bool *preempted); void hap_vcpu_init(struct vcpu *v); int hap_track_dirty_vram(struct domain *d, diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/= hvm/hvm.h index 1c01e22c8e62..6d9a1ae04feb 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -550,6 +550,14 @@ static inline void hvm_invlpg(struct vcpu *v, unsigned= long linear) (1U << X86_EXC_AC) | \ (1U << X86_EXC_MC)) =20 +/* + * Setup the per-domain slots of the per-cpu monitor table and update the = vCPU + * cr3 to use it. + */ +DECLARE_PER_CPU(root_pgentry_t *, monitor_pgt); +void hvm_set_cpu_monitor_table(struct vcpu *v); +void hvm_clear_cpu_monitor_table(struct vcpu *v); + /* Called in boot/resume paths. Must cope with no HVM support. */ static inline int hvm_cpu_up(void) { diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 35e929057d21..7f2666adaef4 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -6367,6 +6367,14 @@ void setup_perdomain_slot(const struct vcpu *v, root= _pgentry_t *root_pgt) l4e_write(&root_pgt[root_table_offset(PERDOMAIN_VIRT_START)], l4e_from_page(v->domain->arch.perdomain_l3_pg, __PAGE_HYPERVISOR_RW)); + + if ( !is_pv_64bit_vcpu(v) ) + /* + * HVM guests always have the compatibility L4 per-domain area bec= ause + * bitness is not know, and can change at runtime. + */ + l4e_write(&root_pgt[root_table_offset(PERDOMAIN_ALT_VIRT_START)], + root_pgt[root_table_offset(PERDOMAIN_VIRT_START)]); } =20 static void __init __maybe_unused build_assertions(void) diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index c8514ca0e917..3279aafcd7d8 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -387,46 +387,6 @@ int hap_set_allocation(struct domain *d, unsigned int = pages, bool *preempted) return 0; } =20 -static mfn_t hap_make_monitor_table(struct vcpu *v) -{ - struct domain *d =3D v->domain; - struct page_info *pg; - l4_pgentry_t *l4e; - mfn_t m4mfn; - - ASSERT(pagetable_get_pfn(v->arch.hvm.monitor_table) =3D=3D 0); - - if ( (pg =3D hap_alloc(d)) =3D=3D NULL ) - goto oom; - - m4mfn =3D page_to_mfn(pg); - l4e =3D map_domain_page(m4mfn); - - init_xen_l4_slots(l4e, m4mfn, INVALID_MFN, d->arch.perdomain_l3_pg, - false, true, false); - unmap_domain_page(l4e); - - return m4mfn; - - oom: - if ( !d->is_dying && - (!d->is_shutting_down || d->shutdown_code !=3D SHUTDOWN_crash) ) - { - printk(XENLOG_G_ERR "%pd: out of memory building monitor pagetable= \n", - d); - domain_crash(d); - } - return INVALID_MFN; -} - -static void hap_destroy_monitor_table(struct vcpu* v, mfn_t mmfn) -{ - struct domain *d =3D v->domain; - - /* Put the memory back in the pool */ - hap_free(d, mmfn); -} - /************************************************/ /* HAP DOMAIN LEVEL FUNCTIONS */ /************************************************/ @@ -548,25 +508,6 @@ void hap_final_teardown(struct domain *d) } } =20 -void hap_vcpu_teardown(struct vcpu *v) -{ - struct domain *d =3D v->domain; - mfn_t mfn; - - paging_lock(d); - - if ( !paging_mode_hap(d) || !v->arch.paging.mode ) - goto out; - - mfn =3D pagetable_get_mfn(v->arch.hvm.monitor_table); - if ( mfn_x(mfn) ) - hap_destroy_monitor_table(v, mfn); - v->arch.hvm.monitor_table =3D pagetable_null(); - - out: - paging_unlock(d); -} - void hap_teardown(struct domain *d, bool *preempted) { struct vcpu *v; @@ -575,10 +516,6 @@ void hap_teardown(struct domain *d, bool *preempted) ASSERT(d->is_dying); ASSERT(d !=3D current->domain); =20 - /* TODO - Remove when the teardown path is better structured. */ - for_each_vcpu ( d, v ) - hap_vcpu_teardown(v); - /* Leave the root pt in case we get further attempts to modify the p2m= . */ if ( hvm_altp2m_supported() ) { @@ -782,21 +719,9 @@ static void cf_check hap_update_paging_modes(struct vc= pu *v) =20 v->arch.paging.mode =3D hap_paging_get_mode(v); =20 - if ( pagetable_is_null(v->arch.hvm.monitor_table) ) - { - mfn_t mmfn =3D hap_make_monitor_table(v); - - if ( mfn_eq(mmfn, INVALID_MFN) ) - goto unlock; - v->arch.hvm.monitor_table =3D pagetable_from_mfn(mmfn); - make_cr3(v, mmfn); - hvm_update_host_cr3(v); - } - /* CR3 is effectively updated by a mode change. Flush ASIDs, etc. */ hap_update_cr3(v, false); =20 - unlock: paging_unlock(d); put_gfn(d, cr3_gfn); } diff --git a/xen/arch/x86/mm/paging.c b/xen/arch/x86/mm/paging.c index bca320fffabf..8ba105b5cb0c 100644 --- a/xen/arch/x86/mm/paging.c +++ b/xen/arch/x86/mm/paging.c @@ -794,9 +794,7 @@ long do_paging_domctl_cont( =20 void paging_vcpu_teardown(struct vcpu *v) { - if ( hap_enabled(v->domain) ) - hap_vcpu_teardown(v); - else + if ( !hap_enabled(v->domain) ) shadow_vcpu_teardown(v); } =20 --=20 2.45.2 From nobody Thu Dec 26 22:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Fri, 26 Jul 2024 08:31:57 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper , Tim Deegan Subject: [PATCH 14/22] x86/hvm: use a per-pCPU monitor table in shadow mode Date: Fri, 26 Jul 2024 17:21:58 +0200 Message-ID: <20240726152206.28411-15-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722008511964116600 Instead of allocating a monitor table for each vCPU when running in HVM sha= dow mode, use a per-pCPU monitor table, which gets the per-domain slot updated = on guest context switch. Signed-off-by: Roger Pau Monn=C3=A9 --- I've tested this manually, but XenServer builds disable shadow support, so = it possibly hasn't been given the same level of testing as the rest of the changes. --- xen/arch/x86/hvm/hvm.c | 7 +++ xen/arch/x86/include/asm/hvm/vcpu.h | 6 ++- xen/arch/x86/include/asm/paging.h | 18 ++++++++ xen/arch/x86/mm.c | 6 +++ xen/arch/x86/mm/shadow/common.c | 42 +++++++----------- xen/arch/x86/mm/shadow/hvm.c | 65 ++++++++++++---------------- xen/arch/x86/mm/shadow/multi.c | 66 ++++++++++++++++++----------- xen/arch/x86/mm/shadow/private.h | 4 +- 8 files changed, 120 insertions(+), 94 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 3f771bc65677..419d78a79c51 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -141,6 +141,7 @@ void hvm_set_cpu_monitor_table(struct vcpu *v) =20 ASSERT(pgt); =20 + paging_set_cpu_monitor_table(v); setup_perdomain_slot(v, pgt); =20 make_cr3(v, _mfn(virt_to_mfn(pgt))); @@ -150,6 +151,8 @@ void hvm_clear_cpu_monitor_table(struct vcpu *v) { /* Poison %cr3, it will be updated when the vCPU is scheduled. */ make_cr3(v, INVALID_MFN); + + paging_clear_cpu_monitor_table(v); } =20 static int cf_check cpu_callback( @@ -1645,6 +1648,10 @@ int hvm_vcpu_initialise(struct vcpu *v) int rc; struct domain *d =3D v->domain; =20 +#ifdef CONFIG_SHADOW_PAGING + v->arch.hvm.shadow_linear_l3 =3D INVALID_MFN; +#endif + hvm_asid_flush_vcpu(v); =20 spin_lock_init(&v->arch.hvm.tm_lock); diff --git a/xen/arch/x86/include/asm/hvm/vcpu.h b/xen/arch/x86/include/asm= /hvm/vcpu.h index 64c7a6fedea9..f7faaaa21521 100644 --- a/xen/arch/x86/include/asm/hvm/vcpu.h +++ b/xen/arch/x86/include/asm/hvm/vcpu.h @@ -149,8 +149,10 @@ struct hvm_vcpu { uint16_t p2midx; } fast_single_step; =20 - /* (MFN) hypervisor page table */ - pagetable_t monitor_table; +#ifdef CONFIG_SHADOW_PAGING + /* Reference to the linear L3 page table. */ + mfn_t shadow_linear_l3; +#endif =20 struct hvm_vcpu_asid n1asid; =20 diff --git a/xen/arch/x86/include/asm/paging.h b/xen/arch/x86/include/asm/p= aging.h index 8a2a0af40874..c1e188bcd3c0 100644 --- a/xen/arch/x86/include/asm/paging.h +++ b/xen/arch/x86/include/asm/paging.h @@ -117,6 +117,8 @@ struct paging_mode { unsigned long cr3, paddr_t ga, uint32_t *pfec, unsigned int *page_order); + void (*set_cpu_monitor_table )(struct vcpu *v); + void (*clear_cpu_monitor_table)(struct vcpu *v); #endif pagetable_t (*update_cr3 )(struct vcpu *v, bool noflush); =20 @@ -288,6 +290,22 @@ static inline bool paging_flush_tlb(const unsigned lon= g *vcpu_bitmap) return current->domain->arch.paging.flush_tlb(vcpu_bitmap); } =20 +static inline void paging_set_cpu_monitor_table(struct vcpu *v) +{ + const struct paging_mode *mode =3D paging_get_hostmode(v); + + if ( mode->set_cpu_monitor_table ) + mode->set_cpu_monitor_table(v); +} + +static inline void paging_clear_cpu_monitor_table(struct vcpu *v) +{ + const struct paging_mode *mode =3D paging_get_hostmode(v); + + if ( mode->clear_cpu_monitor_table ) + mode->clear_cpu_monitor_table(v); +} + #endif /* CONFIG_HVM */ =20 /* Update all the things that are derived from the guest's CR3. diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 7f2666adaef4..13aa15f4db22 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -534,6 +534,12 @@ void write_ptbase(struct vcpu *v) } else { + ASSERT(!is_hvm_domain(d) || !d->arch.asi +#ifdef CONFIG_HVM + || mfn_eq(maddr_to_mfn(v->arch.cr3), + virt_to_mfn(this_cpu(monitor_pgt))) +#endif + ); /* Make sure to clear use_pv_cr3 and xen_cr3 before pv_cr3. */ cpu_info->use_pv_cr3 =3D false; cpu_info->xen_cr3 =3D 0; diff --git a/xen/arch/x86/mm/shadow/common.c b/xen/arch/x86/mm/shadow/commo= n.c index 0176e33bc9c7..d31c1db8a1ab 100644 --- a/xen/arch/x86/mm/shadow/common.c +++ b/xen/arch/x86/mm/shadow/common.c @@ -2413,16 +2413,12 @@ static void sh_update_paging_modes(struct vcpu *v) &SHADOW_INTERNAL_NAME(sh_paging_mode, 2); } =20 - if ( pagetable_is_null(v->arch.hvm.monitor_table) ) + if ( mfn_eq(v->arch.hvm.shadow_linear_l3, INVALID_MFN) ) { - mfn_t mmfn =3D sh_make_monitor_table( - v, v->arch.paging.mode->shadow.shadow_levels); - - if ( mfn_eq(mmfn, INVALID_MFN) ) + if ( sh_update_monitor_table( + v, v->arch.paging.mode->shadow.shadow_levels) ) return; =20 - v->arch.hvm.monitor_table =3D pagetable_from_mfn(mmfn); - make_cr3(v, mmfn); hvm_update_host_cr3(v); } =20 @@ -2440,8 +2436,8 @@ static void sh_update_paging_modes(struct vcpu *v) (v->arch.paging.mode->shadow.shadow_levels !=3D old_mode->shadow.shadow_levels) ) { - /* Need to make a new monitor table for the new mode */ - mfn_t new_mfn, old_mfn; + /* Might need to make a new L3 linear table for the new mo= de */ + mfn_t old_mfn; =20 if ( v !=3D current && vcpu_runnable(v) ) { @@ -2455,24 +2451,21 @@ static void sh_update_paging_modes(struct vcpu *v) return; } =20 - old_mfn =3D pagetable_get_mfn(v->arch.hvm.monitor_table); - v->arch.hvm.monitor_table =3D pagetable_null(); - new_mfn =3D sh_make_monitor_table( - v, v->arch.paging.mode->shadow.shadow_levels= ); - if ( mfn_eq(new_mfn, INVALID_MFN) ) + old_mfn =3D v->arch.hvm.shadow_linear_l3; + v->arch.hvm.shadow_linear_l3 =3D INVALID_MFN; + if ( sh_update_monitor_table( + v, v->arch.paging.mode->shadow.shadow_levels) ) { sh_destroy_monitor_table(v, old_mfn, old_mode->shadow.shadow_level= s); return; } - v->arch.hvm.monitor_table =3D pagetable_from_mfn(new_mfn); - SHADOW_PRINTK("new monitor table %"PRI_mfn "\n", - mfn_x(new_mfn)); + SHADOW_PRINTK("new L3 linear table %"PRI_mfn "\n", + mfn_x(v->arch.hvm.shadow_linear_l3)); =20 /* Don't be running on the old monitor table when we * pull it down! Switch CR3, and warn the HVM code that * its host cr3 has changed. */ - make_cr3(v, new_mfn); if ( v =3D=3D current ) write_ptbase(v); hvm_update_host_cr3(v); @@ -2781,16 +2774,13 @@ void shadow_vcpu_teardown(struct vcpu *v) =20 sh_detach_old_tables(v); #ifdef CONFIG_HVM - if ( shadow_mode_external(d) ) + if ( shadow_mode_external(d) && + !mfn_eq(v->arch.hvm.shadow_linear_l3, INVALID_MFN) ) { - mfn_t mfn =3D pagetable_get_mfn(v->arch.hvm.monitor_table); - - if ( mfn_x(mfn) ) - sh_destroy_monitor_table( - v, mfn, + sh_destroy_monitor_table( + v, v->arch.hvm.shadow_linear_l3, v->arch.paging.mode->shadow.shadow_levels); - - v->arch.hvm.monitor_table =3D pagetable_null(); + v->arch.hvm.shadow_linear_l3 =3D INVALID_MFN; } #endif =20 diff --git a/xen/arch/x86/mm/shadow/hvm.c b/xen/arch/x86/mm/shadow/hvm.c index 93922a71e511..15c75cf766bb 100644 --- a/xen/arch/x86/mm/shadow/hvm.c +++ b/xen/arch/x86/mm/shadow/hvm.c @@ -736,30 +736,15 @@ bool cf_check shadow_flush_tlb(const unsigned long *v= cpu_bitmap) return true; } =20 -mfn_t sh_make_monitor_table(const struct vcpu *v, unsigned int shadow_leve= ls) +int sh_update_monitor_table(struct vcpu *v, unsigned int shadow_levels) { struct domain *d =3D v->domain; - mfn_t m4mfn; - l4_pgentry_t *l4e; =20 - ASSERT(!pagetable_get_pfn(v->arch.hvm.monitor_table)); + ASSERT(mfn_eq(v->arch.hvm.shadow_linear_l3, INVALID_MFN)); =20 /* Guarantee we can get the memory we need */ - if ( !shadow_prealloc(d, SH_type_monitor_table, CONFIG_PAGING_LEVELS) ) - return INVALID_MFN; - - m4mfn =3D shadow_alloc(d, SH_type_monitor_table, 0); - mfn_to_page(m4mfn)->shadow_flags =3D 4; - - l4e =3D map_domain_page(m4mfn); - - /* - * Create a self-linear mapping, but no shadow-linear mapping. A - * shadow-linear mapping will either be inserted below when creating - * lower level monitor tables, or later in sh_update_cr3(). - */ - init_xen_l4_slots(l4e, m4mfn, INVALID_MFN, d->arch.perdomain_l3_pg, - false, true, false); + if ( !shadow_prealloc(d, SH_type_monitor_table, CONFIG_PAGING_LEVELS -= 1) ) + return -ENOMEM; =20 if ( shadow_levels < 4 ) { @@ -773,52 +758,54 @@ mfn_t sh_make_monitor_table(const struct vcpu *v, uns= igned int shadow_levels) */ m3mfn =3D shadow_alloc(d, SH_type_monitor_table, 0); mfn_to_page(m3mfn)->shadow_flags =3D 3; - l4e[l4_table_offset(SH_LINEAR_PT_VIRT_START)] - =3D l4e_from_mfn(m3mfn, __PAGE_HYPERVISOR_RW); =20 m2mfn =3D shadow_alloc(d, SH_type_monitor_table, 0); mfn_to_page(m2mfn)->shadow_flags =3D 2; l3e =3D map_domain_page(m3mfn); l3e[0] =3D l3e_from_mfn(m2mfn, __PAGE_HYPERVISOR_RW); unmap_domain_page(l3e); - } =20 - unmap_domain_page(l4e); + v->arch.hvm.shadow_linear_l3 =3D m3mfn; + + /* + * If the vCPU is not the current one the L4 entry will be updated= on + * context switch. + */ + if ( v =3D=3D current ) + this_cpu(monitor_pgt)[l4_table_offset(SH_LINEAR_PT_VIRT_START)] + =3D l4e_from_mfn(m3mfn, __PAGE_HYPERVISOR_RW); + } + else if ( v =3D=3D current ) + /* The shadow linear mapping will be inserted in sh_update_cr3(). = */ + this_cpu(monitor_pgt)[l4_table_offset(SH_LINEAR_PT_VIRT_START)] + =3D l4e_empty(); =20 - return m4mfn; + return 0; } =20 -void sh_destroy_monitor_table(const struct vcpu *v, mfn_t mmfn, +void sh_destroy_monitor_table(const struct vcpu *v, mfn_t m3mfn, unsigned int shadow_levels) { struct domain *d =3D v->domain; =20 - ASSERT(mfn_to_page(mmfn)->u.sh.type =3D=3D SH_type_monitor_table); - if ( shadow_levels < 4 ) { - mfn_t m3mfn; - l4_pgentry_t *l4e =3D map_domain_page(mmfn); - l3_pgentry_t *l3e; - unsigned int linear_slot =3D l4_table_offset(SH_LINEAR_PT_VIRT_STA= RT); + l3_pgentry_t *l3e =3D map_domain_page(m3mfn); + + ASSERT(!mfn_eq(m3mfn, INVALID_MFN)); + ASSERT(mfn_to_page(m3mfn)->u.sh.type =3D=3D SH_type_monitor_table); =20 /* * Need to destroy the l3 and l2 monitor pages used * for the linear map. */ - ASSERT(l4e_get_flags(l4e[linear_slot]) & _PAGE_PRESENT); - m3mfn =3D l4e_get_mfn(l4e[linear_slot]); - l3e =3D map_domain_page(m3mfn); ASSERT(l3e_get_flags(l3e[0]) & _PAGE_PRESENT); shadow_free(d, l3e_get_mfn(l3e[0])); unmap_domain_page(l3e); shadow_free(d, m3mfn); - - unmap_domain_page(l4e); } - - /* Put the memory back in the pool */ - shadow_free(d, mmfn); + else + ASSERT(mfn_eq(m3mfn, INVALID_MFN)); } =20 /*************************************************************************= */ diff --git a/xen/arch/x86/mm/shadow/multi.c b/xen/arch/x86/mm/shadow/multi.c index 0def0c073ca8..68c59233794f 100644 --- a/xen/arch/x86/mm/shadow/multi.c +++ b/xen/arch/x86/mm/shadow/multi.c @@ -3007,6 +3007,32 @@ static unsigned long cf_check sh_gva_to_gfn( return gfn_x(gfn); } =20 +static void cf_check set_cpu_monitor_table(struct vcpu *v) +{ + root_pgentry_t *pgt =3D this_cpu(monitor_pgt); + + virt_to_page(pgt)->shadow_flags =3D 4; + + /* Setup linear L3 entry. */ + if ( !mfn_eq(v->arch.hvm.shadow_linear_l3, INVALID_MFN) ) + pgt[l4_table_offset(SH_LINEAR_PT_VIRT_START)] =3D + l4e_from_mfn(v->arch.hvm.shadow_linear_l3, __PAGE_HYPERVISOR_R= W); + else + pgt[l4_table_offset(SH_LINEAR_PT_VIRT_START)] =3D + l4e_from_pfn( + pagetable_get_pfn(v->arch.paging.shadow.shadow_table[0]), + __PAGE_HYPERVISOR_RW); +} + +static void cf_check clear_cpu_monitor_table(struct vcpu *v) +{ + root_pgentry_t *pgt =3D this_cpu(monitor_pgt); + + virt_to_page(pgt)->shadow_flags =3D 0; + + pgt[l4_table_offset(SH_LINEAR_PT_VIRT_START)] =3D l4e_empty(); +} + #endif /* CONFIG_HVM */ =20 static inline void @@ -3033,8 +3059,11 @@ sh_update_linear_entries(struct vcpu *v) */ =20 /* Don't try to update the monitor table if it doesn't exist */ - if ( !shadow_mode_external(d) || - pagetable_get_pfn(v->arch.hvm.monitor_table) =3D=3D 0 ) + if ( !shadow_mode_external(d) +#if SHADOW_PAGING_LEVELS =3D=3D 3 + || mfn_eq(v->arch.hvm.shadow_linear_l3, INVALID_MFN) +#endif + ) return; =20 #if !defined(CONFIG_HVM) @@ -3051,17 +3080,6 @@ sh_update_linear_entries(struct vcpu *v) pagetable_get_pfn(v->arch.paging.shadow.shadow_table[0]), __PAGE_HYPERVISOR_RW); } - else - { - l4_pgentry_t *ml4e; - - ml4e =3D map_domain_page(pagetable_get_mfn(v->arch.hvm.monitor_tab= le)); - ml4e[l4_table_offset(SH_LINEAR_PT_VIRT_START)] =3D - l4e_from_pfn( - pagetable_get_pfn(v->arch.paging.shadow.shadow_table[0]), - __PAGE_HYPERVISOR_RW); - unmap_domain_page(ml4e); - } =20 #elif SHADOW_PAGING_LEVELS =3D=3D 3 =20 @@ -3087,16 +3105,8 @@ sh_update_linear_entries(struct vcpu *v) + l2_linear_offset(SH_LINEAR_PT_VIRT_START); else { - mfn_t l3mfn, l2mfn; - l4_pgentry_t *ml4e; - l3_pgentry_t *ml3e; - int linear_slot =3D shadow_l4_table_offset(SH_LINEAR_PT_VIRT_S= TART); - ml4e =3D map_domain_page(pagetable_get_mfn(v->arch.hvm.monitor= _table)); - - ASSERT(l4e_get_flags(ml4e[linear_slot]) & _PAGE_PRESENT); - l3mfn =3D l4e_get_mfn(ml4e[linear_slot]); - ml3e =3D map_domain_page(l3mfn); - unmap_domain_page(ml4e); + mfn_t l2mfn; + l3_pgentry_t *ml3e =3D map_domain_page(v->arch.hvm.shadow_line= ar_l3); =20 ASSERT(l3e_get_flags(ml3e[0]) & _PAGE_PRESENT); l2mfn =3D l3e_get_mfn(ml3e[0]); @@ -3341,9 +3351,13 @@ static pagetable_t cf_check sh_update_cr3(struct vcp= u *v, bool noflush) /// /// v->arch.cr3 /// - if ( shadow_mode_external(d) ) + if ( shadow_mode_external(d) && v =3D=3D current ) { - make_cr3(v, pagetable_get_mfn(v->arch.hvm.monitor_table)); +#ifdef CONFIG_HVM + make_cr3(v, _mfn(virt_to_mfn(this_cpu(monitor_pgt)))); +#else + ASSERT_UNREACHABLE(); +#endif } #if SHADOW_PAGING_LEVELS =3D=3D 4 else // not shadow_mode_external... @@ -4106,6 +4120,8 @@ const struct paging_mode sh_paging_mode =3D { .invlpg =3D sh_invlpg, #ifdef CONFIG_HVM .gva_to_gfn =3D sh_gva_to_gfn, + .set_cpu_monitor_table =3D set_cpu_monitor_table, + .clear_cpu_monitor_table =3D clear_cpu_monitor_table, #endif .update_cr3 =3D sh_update_cr3, .guest_levels =3D GUEST_PAGING_LEVELS, diff --git a/xen/arch/x86/mm/shadow/private.h b/xen/arch/x86/mm/shadow/priv= ate.h index a5fc3a7676eb..6743aeefe12e 100644 --- a/xen/arch/x86/mm/shadow/private.h +++ b/xen/arch/x86/mm/shadow/private.h @@ -420,8 +420,8 @@ void shadow_unhook_mappings(struct domain *d, mfn_t smf= n, int user_only); * sh_{make,destroy}_monitor_table() depend only on the number of shadow * levels. */ -mfn_t sh_make_monitor_table(const struct vcpu *v, unsigned int shadow_leve= ls); -void sh_destroy_monitor_table(const struct vcpu *v, mfn_t mmfn, +int sh_update_monitor_table(struct vcpu *v, unsigned int shadow_levels); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722008256997116600 Introduce support for possibly using a different L4 across the idle vCPUs. This change only introduces support for loading a per-pPCU idle L4, but even with the per-CPU idle page-table enabled it should still be a clone of idle_pg_table, hence no functional change expected. Note the idle L4 is not changed after Xen has reached the SYS_STATE_smp_boot state, hence there are no need to synchronize the contents of the L4 once t= he CPUs are started. Using a per-CPU idle page-table is not strictly required for the Address Sp= ace Isolation work, as idle page tables are never used when running guests. However it simplifies memory management of the per-CPU mappings, as creating per-CPU mappings only require using the idle page-table of the CPU where the mappings should be created. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/boot/x86_64.S | 11 +++++++++++ xen/arch/x86/domain.c | 20 +++++++++++++++++++- xen/arch/x86/domain_page.c | 2 +- xen/arch/x86/include/asm/setup.h | 1 + xen/arch/x86/setup.c | 3 +++ xen/arch/x86/smpboot.c | 7 +++++++ 6 files changed, 42 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S index 04bb62ae8680..af7854820185 100644 --- a/xen/arch/x86/boot/x86_64.S +++ b/xen/arch/x86/boot/x86_64.S @@ -15,6 +15,17 @@ ENTRY(__high_start) mov $XEN_MINIMAL_CR4,%rcx mov %rcx,%cr4 =20 + /* + * Possibly switch to the per-CPU idle page-tables. Note we cannot + * switch earlier as the per-CPU page-tables might be above 4G, and + * hence need to load them from 64bit code. + */ + mov ap_cr3(%rip), %rax + test %rax, %rax + jz .L_skip_cr3 + mov %rax, %cr3 +.L_skip_cr3: + mov stack_start(%rip),%rsp =20 /* Reset EFLAGS (subsumes CLI and CLD). */ diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 9cfcf0dc63f3..b62c4311da6c 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -555,6 +555,7 @@ void arch_vcpu_regs_init(struct vcpu *v) int arch_vcpu_create(struct vcpu *v) { struct domain *d =3D v->domain; + root_pgentry_t *pgt =3D NULL; int rc; =20 v->arch.flags =3D TF_kernel_mode; @@ -589,7 +590,23 @@ int arch_vcpu_create(struct vcpu *v) else { /* Idle domain */ - v->arch.cr3 =3D __pa(idle_pg_table); + if ( (opt_asi_pv || opt_asi_hvm) && v->vcpu_id ) + { + pgt =3D alloc_xenheap_page(); + + /* + * For the idle vCPU 0 (the BSP idle vCPU) use idle_pg_table + * directly, there's no need to create yet another copy. + */ + rc =3D -ENOMEM; + if ( !pgt ) + goto fail; + + copy_page(pgt, idle_pg_table); + v->arch.cr3 =3D __pa(pgt); + } + else + v->arch.cr3 =3D __pa(idle_pg_table); rc =3D 0; v->arch.msrs =3D ZERO_BLOCK_PTR; /* Catch stray misuses */ } @@ -611,6 +628,7 @@ int arch_vcpu_create(struct vcpu *v) vcpu_destroy_fpu(v); xfree(v->arch.msrs); v->arch.msrs =3D NULL; + free_xenheap_page(pgt); =20 return rc; } diff --git a/xen/arch/x86/domain_page.c b/xen/arch/x86/domain_page.c index eac5e3304fb8..99b78af90fd3 100644 --- a/xen/arch/x86/domain_page.c +++ b/xen/arch/x86/domain_page.c @@ -51,7 +51,7 @@ static inline struct vcpu *mapcache_current_vcpu(void) if ( (v =3D idle_vcpu[smp_processor_id()]) =3D=3D current ) sync_local_execstate(); /* We must now be running on the idle page table. */ - ASSERT(cr3_pa(read_cr3()) =3D=3D __pa(idle_pg_table)); + ASSERT(cr3_pa(read_cr3()) =3D=3D cr3_pa(v->arch.cr3)); } =20 return v; diff --git a/xen/arch/x86/include/asm/setup.h b/xen/arch/x86/include/asm/se= tup.h index d75589178b91..a8452fce8f05 100644 --- a/xen/arch/x86/include/asm/setup.h +++ b/xen/arch/x86/include/asm/setup.h @@ -14,6 +14,7 @@ extern unsigned long xenheap_initial_phys_start; extern uint64_t boot_tsc_stamp; =20 extern void *stack_start; +extern unsigned long ap_cr3; =20 void early_cpu_init(bool verbose); void early_time_init(void); diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index bc387d96b519..c5a13b30daf4 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -158,6 +158,9 @@ char asmlinkage __section(".init.bss.stack_aligned") __= aligned(STACK_SIZE) /* Used by the BSP/AP paths to find the higher half stack mapping to use. = */ void *stack_start =3D cpu0_stack + STACK_SIZE - sizeof(struct cpu_info); =20 +/* cr3 value for the AP to load on boot. */ +unsigned long ap_cr3; + /* Used by the boot asm to stash the relocated multiboot info pointer. */ unsigned int asmlinkage __initdata multiboot_ptr; =20 diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index 8aa621533f3d..e07add36b1b6 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -581,6 +581,13 @@ static int do_boot_cpu(int apicid, int cpu) =20 stack_start =3D stack_base[cpu] + STACK_SIZE - sizeof(struct cpu_info); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722008257006116600 So far L4 slot 260 has always been per-domain, in other words: all vCPUs of= a domain share the same L3 entry. Currently only 3 slots are used in that L3 table, which leaves plenty of room. Introduce a per-CPU L3 that's used the the domain has Address Space Isolati= on enabled. Such per-CPU L3 gets currently populated using the same L3 entries present on the per-domain L3 (d->arch.perdomain_l3_pg). No functional change expected, as the per-CPU L3 is always a copy of the contents of d->arch.perdomain_l3_pg. Note that all the per-domain L3 entries are populated at domain create, and hence there's no need to sync the state of the per-CPU L3 as the domain won= 't yet be running when the L3 is modified. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/include/asm/domain.h | 2 + xen/arch/x86/include/asm/mm.h | 4 ++ xen/arch/x86/mm.c | 80 +++++++++++++++++++++++++++++-- xen/arch/x86/setup.c | 8 ++++ xen/arch/x86/smpboot.c | 4 ++ 5 files changed, 95 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/d= omain.h index 8c366be8c75f..7620a352b9e3 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -313,6 +313,8 @@ struct arch_domain { struct page_info *perdomain_l3_pg; =20 + struct page_info *perdomain_l2_pgs[PERDOMAIN_SLOTS]; + #ifdef CONFIG_PV32 unsigned int hv_compat_vstart; #endif diff --git a/xen/arch/x86/include/asm/mm.h b/xen/arch/x86/include/asm/mm.h index 2c309f7b1444..34407fb0af06 100644 --- a/xen/arch/x86/include/asm/mm.h +++ b/xen/arch/x86/include/asm/mm.h @@ -633,4 +633,8 @@ static inline bool arch_mfns_in_directmap(unsigned long= mfn, unsigned long nr) /* Setup the per-domain slot in the root page table pointer. */ void setup_perdomain_slot(const struct vcpu *v, root_pgentry_t *root_pgt); =20 +/* Allocate a per-CPU local L3 table to use in the per-domain slot. */ +int allocate_perdomain_local_l3(unsigned int cpu); +void free_perdomain_local_l3(unsigned int cpu); + #endif /* __ASM_X86_MM_H__ */ diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 13aa15f4db22..1367f3361ffe 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -6079,6 +6079,12 @@ int create_perdomain_mapping(struct domain *d, unsig= ned long va, l2tab =3D __map_domain_page(pg); clear_page(l2tab); l3tab[l3_table_offset(va)] =3D l3e_from_page(pg, __PAGE_HYPERVISOR= _RW); + /* + * Keep a reference to the per-domain L3 entries in case a per-CPU= L3 + * is in use (as opposed to using perdomain_l3_pg). + */ + ASSERT(!d->creation_finished); + d->arch.perdomain_l2_pgs[l3_table_offset(va)] =3D pg; } else l2tab =3D map_l2t_from_l3e(l3tab[l3_table_offset(va)]); @@ -6368,11 +6374,79 @@ unsigned long get_upper_mfn_bound(void) return min(max_mfn, 1UL << (paddr_bits - PAGE_SHIFT)) - 1; } =20 +static DEFINE_PER_CPU(l3_pgentry_t *, local_l3); + +static void populate_perdomain(const struct domain *d, l4_pgentry_t *l4, + l3_pgentry_t *l3) +{ + unsigned int i; + + /* Populate the per-CPU L3 with the per-domain entries. */ + for ( i =3D 0; i < ARRAY_SIZE(d->arch.perdomain_l2_pgs); i++ ) + { + const struct page_info *pg =3D d->arch.perdomain_l2_pgs[i]; + + BUILD_BUG_ON(ARRAY_SIZE(d->arch.perdomain_l2_pgs) > + L3_PAGETABLE_ENTRIES); + l3e_write(&l3[i], pg ? l3e_from_page(pg, __PAGE_HYPERVISOR_RW) + : l3e_empty()); + } + + l4e_write(&l4[l4_table_offset(PERDOMAIN_VIRT_START)], + l4e_from_mfn(virt_to_mfn(l3), __PAGE_HYPERVISOR_RW)); +} + +int allocate_perdomain_local_l3(unsigned int cpu) +{ + const struct domain *d =3D idle_vcpu[cpu]->domain; + l3_pgentry_t *l3; + root_pgentry_t *root_pgt =3D maddr_to_virt(idle_vcpu[cpu]->arch.cr3); + + ASSERT(!per_cpu(local_l3, cpu)); + + if ( !opt_asi_pv && !opt_asi_hvm ) + return 0; + + l3 =3D alloc_xenheap_page(); + if ( !l3 ) + return -ENOMEM; + + clear_page(l3); + + /* Setup the idle domain slots (current domain) in the L3. */ + populate_perdomain(d, root_pgt, l3); + + per_cpu(local_l3, cpu) =3D l3; + + return 0; +} + +void free_perdomain_local_l3(unsigned int cpu) +{ + l3_pgentry_t *l3 =3D per_cpu(local_l3, cpu); + + if ( !l3 ) + return; + + per_cpu(local_l3, cpu) =3D NULL; + free_xenheap_page(l3); +} + void setup_perdomain_slot(const struct vcpu *v, root_pgentry_t *root_pgt) { - l4e_write(&root_pgt[root_table_offset(PERDOMAIN_VIRT_START)], - l4e_from_page(v->domain->arch.perdomain_l3_pg, - __PAGE_HYPERVISOR_RW)); + const struct domain *d =3D v->domain; + + if ( d->arch.asi ) + { + l3_pgentry_t *l3 =3D this_cpu(local_l3); + + ASSERT(l3); + populate_perdomain(d, root_pgt, l3); + } + else if ( is_hvm_domain(d) || d->arch.pv.xpti ) + l4e_write(&root_pgt[root_table_offset(PERDOMAIN_VIRT_START)], + l4e_from_page(v->domain->arch.perdomain_l3_pg, + __PAGE_HYPERVISOR_RW)); =20 if ( !is_pv_64bit_vcpu(v) ) /* diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index c5a13b30daf4..5bf81b81b46f 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -1961,6 +1961,14 @@ void asmlinkage __init noreturn __start_xen(unsigned= long mbi_p) =20 alternative_branches(); =20 + /* + * Setup the local per-domain L3 for the BSP also, so it matches the s= tate + * of the APs. + */ + ret =3D allocate_perdomain_local_l3(0); + if ( ret ) + panic("Error %d setting up local per-domain L3\n", ret); + /* * NB: when running as a PV shim VCPUOP_up/down is wired to the shim * physical cpu_add/remove functions, so launch the guest with only diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index e07add36b1b6..40cc14799252 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -986,6 +986,7 @@ static void cpu_smpboot_free(unsigned int cpu, bool rem= ove) } =20 cleanup_cpu_root_pgt(cpu); + free_perdomain_local_l3(cpu); =20 if ( per_cpu(stubs.addr, cpu) ) { @@ -1100,6 +1101,9 @@ static int cpu_smpboot_alloc(unsigned int cpu) per_cpu(stubs.addr, cpu) =3D stub_page + STUB_BUF_CPU_OFFS(cpu); =20 rc =3D setup_cpu_root_pgt(cpu); + if ( rc ) + goto out; + rc =3D allocate_perdomain_local_l3(cpu); if ( rc ) goto out; rc =3D -ENOMEM; --=20 2.45.2 From nobody Thu Dec 26 22:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Fri, 26 Jul 2024 08:32:03 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH 17/22] x86/mm: introduce support to populate a per-CPU page-table region Date: Fri, 26 Jul 2024 17:22:01 +0200 Message-ID: <20240726152206.28411-18-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722008341300116600 Add logic in map_pages_to_xen() and modify_xen_mappings() so that TLB flush= es are only performed locally when dealing with entries in the per-CPU area of= the page-tables. No functional change intended, as there are no callers added that create or modify per-CPU mappings, nor is the per-CPU area still properly setup in the page-tables yet. Note that the removed flush_area() ended up calling flush_area_mask() throu= gh the flush_area_all() alias. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/include/asm/config.h | 4 ++ xen/arch/x86/include/asm/flushtlb.h | 1 - xen/arch/x86/mm.c | 64 +++++++++++++++++++---------- 3 files changed, 47 insertions(+), 22 deletions(-) diff --git a/xen/arch/x86/include/asm/config.h b/xen/arch/x86/include/asm/c= onfig.h index 2a260a2581fd..c24d735a0cee 100644 --- a/xen/arch/x86/include/asm/config.h +++ b/xen/arch/x86/include/asm/config.h @@ -204,6 +204,10 @@ extern unsigned char boot_edid_info[128]; #define PERDOMAIN_SLOTS 3 #define PERDOMAIN_VIRT_SLOT(s) (PERDOMAIN_VIRT_START + (s) * \ (PERDOMAIN_SLOT_MBYTES << 20)) +#define PERCPU_VIRT_START PERDOMAIN_VIRT_SLOT(PERDOMAIN_SLOTS) +#define PERCPU_SLOTS 1 +#define PERCPU_VIRT_SLOT(s) (PERCPU_VIRT_START + (s) * \ + (PERDOMAIN_SLOT_MBYTES << 20)) /* Slot 4: mirror of per-domain mappings (for compat xlat area accesses). = */ #define PERDOMAIN_ALT_VIRT_START PML4_ADDR(4) /* Slot 261: machine-to-phys conversion table (256GB). */ diff --git a/xen/arch/x86/include/asm/flushtlb.h b/xen/arch/x86/include/asm= /flushtlb.h index 1b98d03decdc..affe944d1a5b 100644 --- a/xen/arch/x86/include/asm/flushtlb.h +++ b/xen/arch/x86/include/asm/flushtlb.h @@ -146,7 +146,6 @@ void flush_area_mask(const cpumask_t *mask, const void = *va, #define flush_mask(mask, flags) flush_area_mask(mask, NULL, flags) =20 /* Flush all CPUs' TLBs/caches */ -#define flush_area_all(va, flags) flush_area_mask(&cpu_online_map, va, fla= gs) #define flush_all(flags) flush_mask(&cpu_online_map, flags) =20 /* Flush local TLBs */ diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 1367f3361ffe..c468b46a9d1b 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -5023,9 +5023,13 @@ static DEFINE_SPINLOCK(map_pgdir_lock); */ static l3_pgentry_t *virt_to_xen_l3e(unsigned long v) { + unsigned int cpu =3D smp_processor_id(); + /* Called before idle_vcpu is populated, fallback to idle_pg_table. */ + root_pgentry_t *root_pgt =3D idle_vcpu[cpu] ? + maddr_to_virt(idle_vcpu[cpu]->arch.cr3) : idle_pg_table; l4_pgentry_t *pl4e; =20 - pl4e =3D &idle_pg_table[l4_table_offset(v)]; + pl4e =3D &root_pgt[l4_table_offset(v)]; if ( !(l4e_get_flags(*pl4e) & _PAGE_PRESENT) ) { bool locking =3D system_state > SYS_STATE_boot; @@ -5138,8 +5142,8 @@ static l1_pgentry_t *virt_to_xen_l1e(unsigned long v) #define l1f_to_lNf(f) (((f) & _PAGE_PRESENT) ? ((f) | _PAGE_PSE) : (f)) #define lNf_to_l1f(f) (((f) & _PAGE_PRESENT) ? ((f) & ~_PAGE_PSE) : (f)) =20 -/* flush_area_all() can be used prior to any other CPU being online. */ -#define flush_area(v, f) flush_area_all((const void *)(v), f) +/* flush_area_mask() can be used prior to any other CPU being online. */ +#define flush_area_mask(m, v, f) flush_area_mask(m, (const void *)(v), f) =20 #define L3T_INIT(page) (page) =3D ZERO_BLOCK_PTR =20 @@ -5222,7 +5226,11 @@ int map_pages_to_xen( unsigned long nr_mfns, unsigned int flags) { - bool locking =3D system_state > SYS_STATE_boot; + bool global =3D virt < PERCPU_VIRT_START || + virt >=3D PERCPU_VIRT_SLOT(PERCPU_SLOTS); + bool locking =3D system_state > SYS_STATE_boot && global; + const cpumask_t *flush_mask =3D global ? &cpu_online_map + : cpumask_of(smp_processor_id()); l3_pgentry_t *pl3e =3D NULL, ol3e; l2_pgentry_t *pl2e =3D NULL, ol2e; l1_pgentry_t *pl1e, ol1e; @@ -5244,6 +5252,11 @@ int map_pages_to_xen( } \ } while (0) =20 + /* Ensure it's a global mapping or it's only modifying the per-CPU are= a. */ + ASSERT(global || + (virt + nr_mfns * PAGE_SIZE >=3D PERCPU_VIRT_START && + virt + nr_mfns * PAGE_SIZE < PERCPU_VIRT_SLOT(PERCPU_SLOTS))); + L3T_INIT(current_l3page); =20 while ( nr_mfns !=3D 0 ) @@ -5278,7 +5291,7 @@ int map_pages_to_xen( if ( l3e_get_flags(ol3e) & _PAGE_PSE ) { flush_flags(lNf_to_l1f(l3e_get_flags(ol3e))); - flush_area(virt, flush_flags); + flush_area_mask(flush_mask, virt, flush_flags); } else { @@ -5301,7 +5314,7 @@ int map_pages_to_xen( unmap_domain_page(l1t); } } - flush_area(virt, flush_flags); + flush_area_mask(flush_mask, virt, flush_flags); for ( i =3D 0; i < L2_PAGETABLE_ENTRIES; i++ ) { ol2e =3D l2t[i]; @@ -5373,7 +5386,7 @@ int map_pages_to_xen( } if ( locking ) spin_unlock(&map_pgdir_lock); - flush_area(virt, flush_flags); + flush_area_mask(flush_mask, virt, flush_flags); =20 free_xen_pagetable(l2mfn); } @@ -5399,7 +5412,7 @@ int map_pages_to_xen( if ( l2e_get_flags(ol2e) & _PAGE_PSE ) { flush_flags(lNf_to_l1f(l2e_get_flags(ol2e))); - flush_area(virt, flush_flags); + flush_area_mask(flush_mask, virt, flush_flags); } else { @@ -5407,7 +5420,7 @@ int map_pages_to_xen( =20 for ( i =3D 0; i < L1_PAGETABLE_ENTRIES; i++ ) flush_flags(l1e_get_flags(l1t[i])); - flush_area(virt, flush_flags); + flush_area_mask(flush_mask, virt, flush_flags); unmap_domain_page(l1t); free_xen_pagetable(l2e_get_mfn(ol2e)); } @@ -5476,7 +5489,7 @@ int map_pages_to_xen( } if ( locking ) spin_unlock(&map_pgdir_lock); - flush_area(virt, flush_flags); + flush_area_mask(flush_mask, virt, flush_flags); =20 free_xen_pagetable(l1mfn); } @@ -5491,7 +5504,7 @@ int map_pages_to_xen( unsigned int flush_flags =3D FLUSH_TLB | FLUSH_ORDER(0); =20 flush_flags(l1e_get_flags(ol1e)); - flush_area(virt, flush_flags); + flush_area_mask(flush_mask, virt, flush_flags); } =20 virt +=3D 1UL << L1_PAGETABLE_SHIFT; @@ -5540,9 +5553,9 @@ int map_pages_to_xen( l2e_write(pl2e, l2e_from_pfn(base_mfn, l1f_to_lNf(flag= s))); if ( locking ) spin_unlock(&map_pgdir_lock); - flush_area(virt - PAGE_SIZE, - FLUSH_TLB_GLOBAL | - FLUSH_ORDER(PAGETABLE_ORDER)); + flush_area_mask(flush_mask, virt - PAGE_SIZE, + FLUSH_TLB_GLOBAL | + FLUSH_ORDER(PAGETABLE_ORDER)); free_xen_pagetable(l2e_get_mfn(ol2e)); } else if ( locking ) @@ -5589,9 +5602,9 @@ int map_pages_to_xen( l3e_write(pl3e, l3e_from_pfn(base_mfn, l1f_to_lNf(flags))); if ( locking ) spin_unlock(&map_pgdir_lock); - flush_area(virt - PAGE_SIZE, - FLUSH_TLB_GLOBAL | - FLUSH_ORDER(2*PAGETABLE_ORDER)); + flush_area_mask(flush_mask, virt - PAGE_SIZE, + FLUSH_TLB_GLOBAL | + FLUSH_ORDER(2*PAGETABLE_ORDER)); free_xen_pagetable(l3e_get_mfn(ol3e)); } else if ( locking ) @@ -5629,7 +5642,11 @@ int __init populate_pt_range(unsigned long virt, uns= igned long nr_mfns) */ int modify_xen_mappings(unsigned long s, unsigned long e, unsigned int nf) { - bool locking =3D system_state > SYS_STATE_boot; + bool global =3D s < PERCPU_VIRT_START || + s >=3D PERCPU_VIRT_SLOT(PERCPU_SLOTS); + bool locking =3D system_state > SYS_STATE_boot && global; + const cpumask_t *flush_mask =3D global ? &cpu_online_map + : cpumask_of(smp_processor_id()); l3_pgentry_t *pl3e =3D NULL; l2_pgentry_t *pl2e =3D NULL; l1_pgentry_t *pl1e; @@ -5638,6 +5655,9 @@ int modify_xen_mappings(unsigned long s, unsigned lon= g e, unsigned int nf) int rc =3D -ENOMEM; struct page_info *current_l3page; =20 + ASSERT(global || + (e >=3D PERCPU_VIRT_START && e < PERCPU_VIRT_SLOT(PERCPU_SLOTS)= )); + /* Set of valid PTE bits which may be altered. */ #define FLAGS_MASK (_PAGE_NX|_PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_RW|_PAGE_PRE= SENT) nf &=3D FLAGS_MASK; @@ -5836,7 +5856,8 @@ int modify_xen_mappings(unsigned long s, unsigned lon= g e, unsigned int nf) l2e_write(pl2e, l2e_empty()); if ( locking ) spin_unlock(&map_pgdir_lock); - flush_area(NULL, FLUSH_TLB_GLOBAL); /* flush before free */ + /* flush before free */ + flush_area_mask(flush_mask, NULL, FLUSH_TLB_GLOBAL); free_xen_pagetable(l1mfn); } else if ( locking ) @@ -5880,7 +5901,8 @@ int modify_xen_mappings(unsigned long s, unsigned lon= g e, unsigned int nf) l3e_write(pl3e, l3e_empty()); if ( locking ) spin_unlock(&map_pgdir_lock); - flush_area(NULL, FLUSH_TLB_GLOBAL); /* flush before free */ + /* flush before free */ + flush_area_mask(flush_mask, NULL, FLUSH_TLB_GLOBAL); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722008445695116600 Add support for modifying the per-CPU page-tables entries of remote CPUs, t= his will be required in order to setup the page-tables of CPUs before bringing = them up. A restriction is added so that remote page-tables can only be modified= as long as the remote CPU is not yet online. Non functional change, as there's no user introduced that modifies remote page-tables. Signed-off-by: Roger Pau Monn=C3=A9 --- Can be merged with previous patch? --- xen/arch/x86/include/asm/mm.h | 15 ++++++++++ xen/arch/x86/mm.c | 55 ++++++++++++++++++++++++++--------- 2 files changed, 56 insertions(+), 14 deletions(-) diff --git a/xen/arch/x86/include/asm/mm.h b/xen/arch/x86/include/asm/mm.h index 34407fb0af06..f883468b1a7c 100644 --- a/xen/arch/x86/include/asm/mm.h +++ b/xen/arch/x86/include/asm/mm.h @@ -637,4 +637,19 @@ void setup_perdomain_slot(const struct vcpu *v, root_p= gentry_t *root_pgt); int allocate_perdomain_local_l3(unsigned int cpu); void free_perdomain_local_l3(unsigned int cpu); =20 +/* Specify the CPU idle root page-table to use for modifications. */ +int map_pages_to_xen_cpu( + unsigned long virt, + mfn_t mfn, + unsigned long nr_mfns, + unsigned int flags, + unsigned int cpu); +int modify_xen_mappings_cpu(unsigned long s, unsigned long e, unsigned int= nf, + unsigned int cpu); +static inline int destroy_xen_mappings_cpu(unsigned long s, unsigned long = e, + unsigned int cpu) +{ + return modify_xen_mappings_cpu(s, e, _PAGE_NONE, cpu); +} + #endif /* __ASM_X86_MM_H__ */ diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index c468b46a9d1b..faf2d42745d1 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -5021,9 +5021,8 @@ static DEFINE_SPINLOCK(map_pgdir_lock); * For virt_to_xen_lXe() functions, they take a linear address and return a * pointer to Xen's LX entry. Caller needs to unmap the pointer. */ -static l3_pgentry_t *virt_to_xen_l3e(unsigned long v) +static l3_pgentry_t *virt_to_xen_l3e_cpu(unsigned long v, unsigned int cpu) { - unsigned int cpu =3D smp_processor_id(); /* Called before idle_vcpu is populated, fallback to idle_pg_table. */ root_pgentry_t *root_pgt =3D idle_vcpu[cpu] ? maddr_to_virt(idle_vcpu[cpu]->arch.cr3) : idle_pg_table; @@ -5062,11 +5061,16 @@ static l3_pgentry_t *virt_to_xen_l3e(unsigned long = v) return map_l3t_from_l4e(*pl4e) + l3_table_offset(v); } =20 -static l2_pgentry_t *virt_to_xen_l2e(unsigned long v) +static l3_pgentry_t *virt_to_xen_l3e(unsigned long v) +{ + return virt_to_xen_l3e_cpu(v, smp_processor_id()); +} + +static l2_pgentry_t *virt_to_xen_l2e_cpu(unsigned long v, unsigned int cpu) { l3_pgentry_t *pl3e, l3e; =20 - pl3e =3D virt_to_xen_l3e(v); + pl3e =3D virt_to_xen_l3e_cpu(v, cpu); if ( !pl3e ) return NULL; =20 @@ -5100,11 +5104,11 @@ static l2_pgentry_t *virt_to_xen_l2e(unsigned long = v) return map_l2t_from_l3e(l3e) + l2_table_offset(v); } =20 -static l1_pgentry_t *virt_to_xen_l1e(unsigned long v) +static l1_pgentry_t *virt_to_xen_l1e_cpu(unsigned long v, unsigned int cpu) { l2_pgentry_t *pl2e, l2e; =20 - pl2e =3D virt_to_xen_l2e(v); + pl2e =3D virt_to_xen_l2e_cpu(v, cpu); if ( !pl2e ) return NULL; =20 @@ -5220,17 +5224,18 @@ mfn_t xen_map_to_mfn(unsigned long va) return ret; } =20 -int map_pages_to_xen( +int map_pages_to_xen_cpu( unsigned long virt, mfn_t mfn, unsigned long nr_mfns, - unsigned int flags) + unsigned int flags, + unsigned int cpu) { bool global =3D virt < PERCPU_VIRT_START || virt >=3D PERCPU_VIRT_SLOT(PERCPU_SLOTS); bool locking =3D system_state > SYS_STATE_boot && global; const cpumask_t *flush_mask =3D global ? &cpu_online_map - : cpumask_of(smp_processor_id()); + : cpumask_of(cpu); l3_pgentry_t *pl3e =3D NULL, ol3e; l2_pgentry_t *pl2e =3D NULL, ol2e; l1_pgentry_t *pl1e, ol1e; @@ -5257,6 +5262,9 @@ int map_pages_to_xen( (virt + nr_mfns * PAGE_SIZE >=3D PERCPU_VIRT_START && virt + nr_mfns * PAGE_SIZE < PERCPU_VIRT_SLOT(PERCPU_SLOTS))); =20 + /* Only allow modifying remote page-tables if the CPU is not online. */ + ASSERT(cpu =3D=3D smp_processor_id() || !cpu_online(cpu)); + L3T_INIT(current_l3page); =20 while ( nr_mfns !=3D 0 ) @@ -5266,7 +5274,7 @@ int map_pages_to_xen( UNMAP_DOMAIN_PAGE(pl3e); UNMAP_DOMAIN_PAGE(pl2e); =20 - pl3e =3D virt_to_xen_l3e(virt); + pl3e =3D virt_to_xen_l3e_cpu(virt, cpu); if ( !pl3e ) goto out; =20 @@ -5391,7 +5399,7 @@ int map_pages_to_xen( free_xen_pagetable(l2mfn); } =20 - pl2e =3D virt_to_xen_l2e(virt); + pl2e =3D virt_to_xen_l2e_cpu(virt, cpu); if ( !pl2e ) goto out; =20 @@ -5437,7 +5445,7 @@ int map_pages_to_xen( /* Normal page mapping. */ if ( !(l2e_get_flags(*pl2e) & _PAGE_PRESENT) ) { - pl1e =3D virt_to_xen_l1e(virt); + pl1e =3D virt_to_xen_l1e_cpu(virt, cpu); if ( pl1e =3D=3D NULL ) goto out; } @@ -5623,6 +5631,16 @@ int map_pages_to_xen( return rc; } =20 +int map_pages_to_xen( + unsigned long virt, + mfn_t mfn, + unsigned long nr_mfns, + unsigned int flags) +{ + return map_pages_to_xen_cpu(virt, mfn, nr_mfns, flags, smp_processor_i= d()); +} + + int __init populate_pt_range(unsigned long virt, unsigned long nr_mfns) { return map_pages_to_xen(virt, INVALID_MFN, nr_mfns, MAP_SMALL_PAGES); @@ -5640,7 +5658,8 @@ int __init populate_pt_range(unsigned long virt, unsi= gned long nr_mfns) * * It is an error to call with present flags over an unpopulated range. */ -int modify_xen_mappings(unsigned long s, unsigned long e, unsigned int nf) +int modify_xen_mappings_cpu(unsigned long s, unsigned long e, unsigned int= nf, + unsigned int cpu) { bool global =3D s < PERCPU_VIRT_START || s >=3D PERCPU_VIRT_SLOT(PERCPU_SLOTS); @@ -5658,6 +5677,9 @@ int modify_xen_mappings(unsigned long s, unsigned lon= g e, unsigned int nf) ASSERT(global || (e >=3D PERCPU_VIRT_START && e < PERCPU_VIRT_SLOT(PERCPU_SLOTS)= )); =20 + /* Only allow modifying remote page-tables if the CPU is not online. */ + ASSERT(cpu =3D=3D smp_processor_id() || !cpu_online(cpu)); + /* Set of valid PTE bits which may be altered. */ #define FLAGS_MASK (_PAGE_NX|_PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_RW|_PAGE_PRE= SENT) nf &=3D FLAGS_MASK; @@ -5674,7 +5696,7 @@ int modify_xen_mappings(unsigned long s, unsigned lon= g e, unsigned int nf) UNMAP_DOMAIN_PAGE(pl2e); UNMAP_DOMAIN_PAGE(pl3e); =20 - pl3e =3D virt_to_xen_l3e(v); + pl3e =3D virt_to_xen_l3e_cpu(v, cpu); if ( !pl3e ) goto out; =20 @@ -5927,6 +5949,11 @@ int modify_xen_mappings(unsigned long s, unsigned lo= ng e, unsigned int nf) =20 #undef flush_area =20 +int modify_xen_mappings(unsigned long s, unsigned long e, unsigned int nf) +{ + return modify_xen_mappings_cpu(s, e, nf, smp_processor_id()); +} + int destroy_xen_mappings(unsigned long s, unsigned long e) { return modify_xen_mappings(s, e, _PAGE_NONE); --=20 2.45.2 From nobody Thu Dec 26 22:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Fri, 26 Jul 2024 08:32:07 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH 19/22] x86/mm: introduce a per-CPU fixmap area Date: Fri, 26 Jul 2024 17:22:03 +0200 Message-ID: <20240726152206.28411-20-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722008385651116600 Introduce the logic to manage a per-CPU fixmap area. This includes adding a new set of headers that are capable of creating mappings in the per-CPU page-table regions by making use of the map_pages_to_xen_cpu(). This per-CPU fixmap area is currently set to use one L3 slot: 1GiB of linear address space. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/include/asm/fixmap.h | 44 +++++++++++++++++++++++++++++++ xen/arch/x86/mm.c | 16 ++++++++++- 2 files changed, 59 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/include/asm/fixmap.h b/xen/arch/x86/include/asm/f= ixmap.h index 516ec3fa6c95..a456c65072d8 100644 --- a/xen/arch/x86/include/asm/fixmap.h +++ b/xen/arch/x86/include/asm/fixmap.h @@ -118,6 +118,50 @@ extern void __set_fixmap_x( #define __fix_x_to_virt(x) (FIXADDR_X_TOP - ((x) << PAGE_SHIFT)) #define fix_x_to_virt(x) ((void *)__fix_x_to_virt(x)) =20 +/* per-CPU fixmap area. */ +enum percpu_fixed_addresses { + __end_of_percpu_fixed_addresses +}; + +#define PERCPU_FIXADDR_SIZE (__end_of_percpu_fixed_addresses << PAGE_SHIFT) +#define PERCPU_FIXADDR PERCPU_VIRT_SLOT(0) + +static inline void *percpu_fix_to_virt(enum percpu_fixed_addresses idx) +{ + BUG_ON(idx >=3D__end_of_percpu_fixed_addresses); + return (void *)PERCPU_FIXADDR + (idx << PAGE_SHIFT); +} + +static inline void percpu_set_fixmap_remote( + unsigned int cpu, enum percpu_fixed_addresses idx, mfn_t mfn, + unsigned long flags) +{ + map_pages_to_xen_cpu((unsigned long)percpu_fix_to_virt(idx), mfn, 1, f= lags, + cpu); +} + +static inline void percpu_clear_fixmap_remote( + unsigned int cpu, enum percpu_fixed_addresses idx) +{ + /* + * Use map_pages_to_xen_cpu() instead of destroy_xen_mappings_cpu() to + * avoid tearing down the intermediate page-tables if empty. + */ + map_pages_to_xen_cpu((unsigned long)percpu_fix_to_virt(idx), INVALID_M= FN, 1, + 0, cpu); +} + +static inline void percpu_set_fixmap(enum percpu_fixed_addresses idx, mfn_= t mfn, + unsigned long flags) +{ + percpu_set_fixmap_remote(smp_processor_id(), idx, mfn, flags); +} + +static inline void percpu_clear_fixmap(enum percpu_fixed_addresses idx) +{ + percpu_clear_fixmap_remote(smp_processor_id(), idx); +} + #endif /* __ASSEMBLY__ */ =20 #endif diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index faf2d42745d1..937089d203cc 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -6467,7 +6467,17 @@ int allocate_perdomain_local_l3(unsigned int cpu) =20 per_cpu(local_l3, cpu) =3D l3; =20 - return 0; + /* + * Pre-allocate the page-table structures for the per-cpu fixmap. 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Fri, 26 Jul 2024 08:32:10 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH 20/22] x86/pv: allow using a unique per-pCPU root page table (L4) Date: Fri, 26 Jul 2024 17:22:04 +0200 Message-ID: <20240726152206.28411-21-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722008367335116600 When running PV guests it's possible for the guest to use the same root page table (L4) for all vCPUs, which in turn will result in Xen also using the s= ame root page table on all pCPUs that are running any domain vCPU. When using XPTI Xen switches to a per-CPU shadow L4 when running in guest context, switching to the fully populated L4 when in Xen context. Take advantage of this existing shadowing and force the usage of a per-CPU = L4 that shadows the guest selected L4 when Address Space Isolation is requested for PV guests. The mapping of the guest L4 is done with a per-CPU fixmap entry, that howev= er requires that the currently loaded L4 has the per-CPU slot setup. In order= to ensure this switch to the shadow per-CPU L4 with just the Xen slots populat= ed, and then map the guest L4 and copy the contents of the guest controlled slots. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/domain.c | 37 +++++++++++++++++++++ xen/arch/x86/flushtlb.c | 9 ++++++ xen/arch/x86/include/asm/current.h | 15 ++++++--- xen/arch/x86/include/asm/fixmap.h | 1 + xen/arch/x86/include/asm/pv/mm.h | 8 +++++ xen/arch/x86/mm.c | 47 +++++++++++++++++++++++++++ xen/arch/x86/pv/domain.c | 25 ++++++++++++-- xen/arch/x86/pv/mm.c | 52 ++++++++++++++++++++++++++++++ xen/arch/x86/smpboot.c | 20 +++++++++++- 9 files changed, 207 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index b62c4311da6c..94a42ef29cd1 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include #include @@ -2110,11 +2111,47 @@ void context_switch(struct vcpu *prev, struct vcpu = *next) =20 local_irq_disable(); =20 + if ( is_pv_domain(prevd) && prevd->arch.asi ) + { + /* + * Don't leak the L4 shadow mapping in the per-CPU area. Can't be= done + * in paravirt_ctxt_switch_from() because the lazy idle vCPU conte= xt + * switch would otherwise enter an infinite loop in + * mapcache_current_vcpu() with sync_local_execstate(). + * + * Note clearing the fixmpa must strictly be done ahead of changin= g the + * current vCPU and with interrupts disabled, so there's no window + * where current->domain->arch.asi =3D=3D true and PCPU_FIX_PV_L4S= HADOW is + * not mapped. + */ + percpu_clear_fixmap(PCPU_FIX_PV_L4SHADOW); + get_cpu_info()->root_pgt_changed =3D false; + } + set_current(next); =20 if ( (per_cpu(curr_vcpu, cpu) =3D=3D next) || (is_idle_domain(nextd) && cpu_online(cpu)) ) { + if ( is_pv_domain(nextd) && nextd->arch.asi ) + { + /* Signal the fixmap entry must be mapped. */ + get_cpu_info()->new_cr3 =3D true; + if ( get_cpu_info()->root_pgt_changed ) + { + /* + * Map and update the shadow L4 in case we received any + * FLUSH_ROOT_PGTBL request while running on the idle vCPU. + * + * Do it before enabling interrupts so that no flush IPI c= an be + * delivered without having PCPU_FIX_PV_L4SHADOW correctly + * mapped. + */ + pv_update_shadow_l4(next, true); + get_cpu_info()->root_pgt_changed =3D false; + } + } + local_irq_enable(); } else diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c index fd5ed16ffb57..b85ce232abbb 100644 --- a/xen/arch/x86/flushtlb.c +++ b/xen/arch/x86/flushtlb.c @@ -17,6 +17,7 @@ #include #include #include +#include #include =20 /* Debug builds: Wrap frequently to stress-test the wrap logic. */ @@ -192,7 +193,15 @@ unsigned int flush_area_local(const void *va, unsigned= int flags) unsigned int order =3D (flags - 1) & FLUSH_ORDER_MASK; =20 if ( flags & FLUSH_ROOT_PGTBL ) + { + const struct vcpu *curr =3D current; + const struct domain *curr_d =3D curr->domain; + get_cpu_info()->root_pgt_changed =3D true; + if ( is_pv_domain(curr_d) && curr_d->arch.asi ) + /* Update the shadow root page-table ahead of doing TLB flush.= */ + pv_update_shadow_l4(curr, false); + } =20 if ( flags & (FLUSH_TLB|FLUSH_TLB_GLOBAL) ) { diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/= current.h index bcec328c9875..6a021607a1a9 100644 --- a/xen/arch/x86/include/asm/current.h +++ b/xen/arch/x86/include/asm/current.h @@ -60,10 +60,14 @@ struct cpu_info { uint8_t scf; /* SCF_* */ =20 /* - * The following field controls copying of the L4 page table of 64-bit - * PV guests to the per-cpu root page table on entering the guest cont= ext. - * If set the L4 page table is being copied to the root page table and - * the field will be reset. + * For XPTI the following field controls copying of the L4 page table = of + * 64-bit PV guests to the per-cpu root page table on entering the gue= st + * context. If set the L4 page table is being copied to the root page + * table and the field will be reset. + * + * For ASI the field is used to acknowledge whether a FLUSH_ROOT_PGTBL + * request has been received when running the idle vCPU on PV guest + * page-tables (a lazy context switch to the idle vCPU). */ bool root_pgt_changed; =20 @@ -74,6 +78,9 @@ struct cpu_info { */ bool use_pv_cr3; =20 + /* For ASI: per-CPU fixmap of guest L4 is possibly out of sync. */ + bool new_cr3; + /* get_stack_bottom() must be 16-byte aligned */ }; =20 diff --git a/xen/arch/x86/include/asm/fixmap.h b/xen/arch/x86/include/asm/f= ixmap.h index a456c65072d8..bc68a98568ae 100644 --- a/xen/arch/x86/include/asm/fixmap.h +++ b/xen/arch/x86/include/asm/fixmap.h @@ -120,6 +120,7 @@ extern void __set_fixmap_x( =20 /* per-CPU fixmap area. */ enum percpu_fixed_addresses { + PCPU_FIX_PV_L4SHADOW, __end_of_percpu_fixed_addresses }; =20 diff --git a/xen/arch/x86/include/asm/pv/mm.h b/xen/arch/x86/include/asm/pv= /mm.h index 182764542c1f..a7c74898fce0 100644 --- a/xen/arch/x86/include/asm/pv/mm.h +++ b/xen/arch/x86/include/asm/pv/mm.h @@ -23,6 +23,9 @@ bool pv_destroy_ldt(struct vcpu *v); =20 int validate_segdesc_page(struct page_info *page); =20 +void pv_clear_l4_guest_entries(root_pgentry_t *root_pgt); +void pv_update_shadow_l4(const struct vcpu *v, bool flush); + #else =20 #include @@ -44,6 +47,11 @@ static inline bool pv_map_ldt_shadow_page(unsigned int o= ff) { return false; } static inline bool pv_destroy_ldt(struct vcpu *v) { ASSERT_UNREACHABLE(); return false; } =20 +static inline void pv_clear_l4_guest_entries(root_pgentry_t *root_pgt) +{ ASSERT_UNREACHABLE(); } +static inline void pv_update_shadow_l4(const struct vcpu *v, bool flush) +{ ASSERT_UNREACHABLE(); } + #endif =20 #endif /* __X86_PV_MM_H__ */ diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 937089d203cc..8fea7465a9df 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -513,6 +513,8 @@ void make_cr3(struct vcpu *v, mfn_t mfn) v->arch.cr3 =3D mfn_x(mfn) << PAGE_SHIFT; if ( is_pv_domain(d) && d->arch.pv.pcid ) v->arch.cr3 |=3D get_pcid_bits(v, false); + if ( is_pv_domain(d) && d->arch.asi ) + get_cpu_info()->new_cr3 =3D true; } =20 void write_ptbase(struct vcpu *v) @@ -532,6 +534,40 @@ void write_ptbase(struct vcpu *v) cpu_info->pv_cr3 |=3D get_pcid_bits(v, true); switch_cr3_cr4(v->arch.cr3, new_cr4); } + else if ( is_pv_domain(d) && d->arch.asi ) + { + root_pgentry_t *root_pgt =3D this_cpu(root_pgt); + unsigned long cr3 =3D __pa(root_pgt); + + /* + * XPTI and ASI cannot be simultaneously used even by different + * domains at runtime. + */ + ASSERT(!cpu_info->use_pv_cr3 && !cpu_info->xen_cr3 && + !cpu_info->pv_cr3); + + if ( new_cr4 & X86_CR4_PCIDE ) + cr3 |=3D get_pcid_bits(v, false); + + /* + * Zap guest L4 entries ahead of flushing the TLB, so that the CPU + * cannot speculatively populate the TLB with stale mappings. + */ + pv_clear_l4_guest_entries(root_pgt); + + /* + * Switch to the shadow L4 with just the Xen slots populated, the = guest + * slots will be populated by pv_update_shadow_l4() once running o= n the + * shadow L4. + * + * The reason for switching to the per-CPU shadow L4 before updati= ng + * the guest slots is that pv_update_shadow_l4() uses per-CPU mapp= ings, + * and the in-use page-table previous to the switch_cr3_cr4() call + * might not support per-CPU mappings. + */ + switch_cr3_cr4(cr3, new_cr4); + pv_update_shadow_l4(v, false); + } else { ASSERT(!is_hvm_domain(d) || !d->arch.asi @@ -6505,6 +6541,17 @@ void setup_perdomain_slot(const struct vcpu *v, root= _pgentry_t *root_pgt) =20 ASSERT(l3); populate_perdomain(d, root_pgt, l3); + + if ( is_pv_domain(d) ) + { + /* + * Abuse the fact that this function is called on vCPU context + * switch and clean previous guest controlled slots from the s= hadow + * L4. + */ + pv_clear_l4_guest_entries(root_pgt); + get_cpu_info()->new_cr3 =3D true; + } } else if ( is_hvm_domain(d) || d->arch.pv.xpti ) l4e_write(&root_pgt[root_table_offset(PERDOMAIN_VIRT_START)], diff --git a/xen/arch/x86/pv/domain.c b/xen/arch/x86/pv/domain.c index 46ee10a8a4c2..80bf2bf934dd 100644 --- a/xen/arch/x86/pv/domain.c +++ b/xen/arch/x86/pv/domain.c @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 #ifdef CONFIG_PV32 @@ -384,7 +385,7 @@ int pv_domain_initialise(struct domain *d) =20 d->arch.ctxt_switch =3D &pv_csw; =20 - d->arch.pv.flush_root_pt =3D d->arch.pv.xpti; + d->arch.pv.flush_root_pt =3D d->arch.pv.xpti || d->arch.asi; =20 if ( !is_pv_32bit_domain(d) && use_invpcid && cpu_has_pcid ) switch ( ACCESS_ONCE(opt_pcid) ) @@ -446,7 +447,27 @@ static void _toggle_guest_pt(struct vcpu *v) * to release). Switch to the idle page tables in such an event; the * guest will have been crashed already. */ - cr3 =3D v->arch.cr3; + if ( v->domain->arch.asi ) + { + /* + * _toggle_guest_pt() might switch between user and kernel page ta= bles, + * but doesn't use write_ptbase(), and hence needs an explicit cal= l to + * sync the shadow L4. + */ + cr3 =3D __pa(this_cpu(root_pgt)); + if ( v->domain->arch.pv.pcid ) + cr3 |=3D get_pcid_bits(v, false); + /* + * Ensure the current root page table is already the shadow L4, as + * guest user/kernel switches can only happen once the guest is + * running. + */ + ASSERT(read_cr3() =3D=3D cr3); + pv_update_shadow_l4(v, false); + } + else + cr3 =3D v->arch.cr3; + if ( shadow_mode_enabled(v->domain) ) { cr3 &=3D ~X86_CR3_NOFLUSH; diff --git a/xen/arch/x86/pv/mm.c b/xen/arch/x86/pv/mm.c index 24f0d2e4ff7d..c20ce099ae27 100644 --- a/xen/arch/x86/pv/mm.c +++ b/xen/arch/x86/pv/mm.c @@ -11,6 +11,7 @@ #include =20 #include +#include #include =20 #include "mm.h" @@ -103,6 +104,57 @@ void init_xen_pae_l2_slots(l2_pgentry_t *l2t, const st= ruct domain *d) } #endif =20 +void pv_clear_l4_guest_entries(root_pgentry_t *root_pgt) +{ + unsigned int i; + + for ( i =3D 0; i < ROOT_PAGETABLE_FIRST_XEN_SLOT; i++ ) + l4e_write(&root_pgt[i], l4e_empty()); + for ( i =3D ROOT_PAGETABLE_LAST_XEN_SLOT + 1; i < L4_PAGETABLE_ENTRIES= ; i++ ) + l4e_write(&root_pgt[i], l4e_empty()); +} + +void pv_update_shadow_l4(const struct vcpu *v, bool flush) +{ + const root_pgentry_t *guest_pgt =3D percpu_fix_to_virt(PCPU_FIX_PV_L4S= HADOW); + root_pgentry_t *shadow_pgt =3D this_cpu(root_pgt); + + ASSERT(!v->domain->arch.pv.xpti); + ASSERT(is_pv_vcpu(v)); + ASSERT(!is_idle_vcpu(v)); + + if ( get_cpu_info()->new_cr3 ) + { + percpu_set_fixmap(PCPU_FIX_PV_L4SHADOW, maddr_to_mfn(v->arch.cr3), + __PAGE_HYPERVISOR_RO); + get_cpu_info()->new_cr3 =3D false; + } + + if ( is_pv_32bit_vcpu(v) ) + { + l4e_write(&shadow_pgt[0], guest_pgt[0]); + l4e_write(&shadow_pgt[root_table_offset(PERDOMAIN_ALT_VIRT_START)], + shadow_pgt[root_table_offset(PERDOMAIN_VIRT_START)]); + } + else + { + unsigned int i; + + for ( i =3D 0; i < ROOT_PAGETABLE_FIRST_XEN_SLOT; i++ ) + l4e_write(&shadow_pgt[i], guest_pgt[i]); + for ( i =3D ROOT_PAGETABLE_LAST_XEN_SLOT + 1; + i < L4_PAGETABLE_ENTRIES; i++ ) + l4e_write(&shadow_pgt[i], guest_pgt[i]); + + /* The presence of this Xen slot is selected by the guest. */ + l4e_write(&shadow_pgt[l4_table_offset(RO_MPT_VIRT_START)], + guest_pgt[l4_table_offset(RO_MPT_VIRT_START)]); + } + + if ( flush ) + flush_local(FLUSH_TLB_GLOBAL); +} + /* * Local variables: * mode: C diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index 40cc14799252..d9841ed3b663 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -829,7 +829,7 @@ int setup_cpu_root_pgt(unsigned int cpu) unsigned int off; int rc; =20 - if ( !opt_xpti_hwdom && !opt_xpti_domu ) + if ( !opt_xpti_hwdom && !opt_xpti_domu && !opt_asi_pv ) return 0; =20 rpt =3D alloc_xenheap_page(); @@ -839,6 +839,18 @@ int setup_cpu_root_pgt(unsigned int cpu) clear_page(rpt); per_cpu(root_pgt, cpu) =3D rpt; =20 + if ( opt_asi_pv ) + { + /* + * Populate the Xen slots, the guest ones will be copied from the = guest + * root page-table. + */ + init_xen_l4_slots(rpt, _mfn(virt_to_mfn(rpt)), INVALID_MFN, NULL, + false, false, true); + + return 0; + } + rpt[root_table_offset(RO_MPT_VIRT_START)] =3D idle_pg_table[root_table_offset(RO_MPT_VIRT_START)]; /* SH_LINEAR_PT inserted together with guest mappings. */ @@ -892,6 +904,12 @@ static void cleanup_cpu_root_pgt(unsigned int cpu) =20 per_cpu(root_pgt, cpu) =3D NULL; =20 + if ( opt_asi_pv ) + { + free_xenheap_page(rpt); + return; + } + for ( r =3D root_table_offset(DIRECTMAP_VIRT_START); r < root_table_offset(HYPERVISOR_VIRT_END); ++r ) { --=20 2.45.2 From nobody Thu Dec 26 22:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; 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Fri, 26 Jul 2024 08:32:12 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper , Julien Grall , Stefano Stabellini , "Daniel P. Smith" , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= Subject: [PATCH 21/22] x86/mm: switch to a per-CPU mapped stack when using ASI Date: Fri, 26 Jul 2024 17:22:05 +0200 Message-ID: <20240726152206.28411-22-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722008514222116600 When using ASI the CPU stack is mapped using a range of fixmap entries in t= he per-CPU region. This ensures the stack is only accessible by the current C= PU. Note however there's further work required in order to allocate the stack f= rom domheap instead of xenheap, and ensure the stack is not part of the direct map. For domains not running with ASI enabled all the CPU stacks are mapped in t= he per-domain L3, so that the stack is always at the same linear address, regardless of whether ASI is enabled or not for the domain. When calling UEFI runtime methods the current per-domain slot needs to be a= dded to the EFI L4, so that the stack is available in UEFI. Finally, some users of callfunc IPIs pass parameters from the stack, so when handling a callfunc IPI the stack of the caller CPU is mapped into the addr= ess space of the CPU handling the IPI. This needs further work to use a bounce buffer in order to avoid having to map remote CPU stacks. Signed-off-by: Roger Pau Monn=C3=A9 --- There's also further work required in order to avoid mapping remote stack w= hen handling callfunc IPIs. --- xen/arch/x86/domain.c | 12 +++ xen/arch/x86/include/asm/current.h | 5 ++ xen/arch/x86/include/asm/fixmap.h | 5 ++ xen/arch/x86/include/asm/mm.h | 6 +- xen/arch/x86/include/asm/smp.h | 12 +++ xen/arch/x86/mm.c | 125 +++++++++++++++++++++++++++-- xen/arch/x86/setup.c | 27 +++++-- xen/arch/x86/smp.c | 29 +++++++ xen/arch/x86/smpboot.c | 47 ++++++++++- xen/arch/x86/traps.c | 6 +- xen/common/efi/runtime.c | 12 +++ xen/common/smp.c | 10 +++ xen/include/xen/smp.h | 5 ++ 13 files changed, 281 insertions(+), 20 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 94a42ef29cd1..d00ba415877f 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -929,6 +929,18 @@ int arch_domain_create(struct domain *d, =20 d->arch.msr_relaxed =3D config->arch.misc_flags & XEN_X86_MSR_RELAXED; =20 + if ( !d->arch.asi && (opt_asi_hvm || opt_asi_pv ) ) + { + /* + * This domain is not using ASI, but other domains on the system + * possibly are, hence the CPU stacks are on the per-CPU page-table + * region. Add an L3 entry that has all the stacks mapped. + */ + rc =3D map_all_stacks(d); + if ( rc ) + goto fail; + } + return 0; =20 fail: diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/= current.h index 6a021607a1a9..75b9a341f814 100644 --- a/xen/arch/x86/include/asm/current.h +++ b/xen/arch/x86/include/asm/current.h @@ -24,6 +24,11 @@ * 0 - IST Shadow Stacks (4x 1k, read-only) */ =20 +static inline bool is_shstk_slot(unsigned int i) +{ + return (i =3D=3D 0 || i =3D=3D PRIMARY_SHSTK_SLOT); +} + /* * Identify which stack page the stack pointer is on. Returns an index * as per the comment above. diff --git a/xen/arch/x86/include/asm/fixmap.h b/xen/arch/x86/include/asm/f= ixmap.h index bc68a98568ae..d52c1886fcdd 100644 --- a/xen/arch/x86/include/asm/fixmap.h +++ b/xen/arch/x86/include/asm/fixmap.h @@ -120,6 +120,11 @@ extern void __set_fixmap_x( =20 /* per-CPU fixmap area. */ enum percpu_fixed_addresses { + /* For alignment reasons the per-CPU stacks must come first. */ + PCPU_STACK_START, + PCPU_STACK_END =3D PCPU_STACK_START + NR_CPUS * (1U << STACK_ORDER) - = 1, +#define PERCPU_STACK_IDX(c) (PCPU_STACK_START + (c) * (1U << STACK_ORDER)) +#define PERCPU_STACK_ADDR(c) percpu_fix_to_virt(PERCPU_STACK_IDX(c)) PCPU_FIX_PV_L4SHADOW, __end_of_percpu_fixed_addresses }; diff --git a/xen/arch/x86/include/asm/mm.h b/xen/arch/x86/include/asm/mm.h index f883468b1a7c..b4f1e0399275 100644 --- a/xen/arch/x86/include/asm/mm.h +++ b/xen/arch/x86/include/asm/mm.h @@ -521,7 +521,7 @@ extern struct rangeset *mmio_ro_ranges; #define compat_pfn_to_cr3(pfn) (((unsigned)(pfn) << 12) | ((unsigned)(pfn)= >> 20)) #define compat_cr3_to_pfn(cr3) (((unsigned)(cr3) >> 12) | ((unsigned)(cr3)= << 20)) =20 -void memguard_guard_stack(void *p); +void memguard_guard_stack(void *p, unsigned int cpu); void memguard_unguard_stack(void *p); =20 struct mmio_ro_emulate_ctxt { @@ -652,4 +652,8 @@ static inline int destroy_xen_mappings_cpu(unsigned lon= g s, unsigned long e, return modify_xen_mappings_cpu(s, e, _PAGE_NONE, cpu); } =20 +/* Setup a per-domain slot that maps all pCPU stacks. */ +int map_all_stacks(struct domain *d); +int add_stack(const void *stack, unsigned int cpu); + #endif /* __ASM_X86_MM_H__ */ diff --git a/xen/arch/x86/include/asm/smp.h b/xen/arch/x86/include/asm/smp.h index c8c79601343d..a17c609da4b6 100644 --- a/xen/arch/x86/include/asm/smp.h +++ b/xen/arch/x86/include/asm/smp.h @@ -79,6 +79,18 @@ extern bool unaccounted_cpus; =20 void *cpu_alloc_stack(unsigned int cpu); =20 +/* + * Setup the per-CPU area stack mappings. + * + * @dest_cpu: CPU where the mappings are to appear. + * @stack_cpu: CPU whose stacks should be mapped. + */ +void cpu_set_stack_mappings(unsigned int dest_cpu, unsigned int stack_cpu); + +#define HAS_ARCH_SMP_CALLFUNC +void arch_smp_pre_callfunc(unsigned int cpu); +void arch_smp_post_callfunc(unsigned int cpu); + #endif /* !__ASSEMBLY__ */ =20 #endif diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 8fea7465a9df..67ffdebb595e 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -87,6 +87,7 @@ * doing the final put_page(), and remove it from the iommu if so. */ =20 +#include #include #include #include @@ -6352,31 +6353,40 @@ void free_perdomain_mappings(struct domain *d) d->arch.perdomain_l3_pg =3D NULL; } =20 -static void write_sss_token(unsigned long *ptr) +static void write_sss_token(unsigned long *ptr, unsigned long va) { /* * A supervisor shadow stack token is its own linear address, with the * busy bit (0) clear. */ - *ptr =3D (unsigned long)ptr; + *ptr =3D va; } =20 -void memguard_guard_stack(void *p) +void memguard_guard_stack(void *p, unsigned int cpu) { + unsigned long va =3D + (opt_asi_hvm || opt_asi_pv) ? (unsigned long)PERCPU_STACK_ADDR(cpu) + : (unsigned long)p; + /* IST Shadow stacks. 4x 1k in stack page 0. */ if ( IS_ENABLED(CONFIG_XEN_SHSTK) ) { - write_sss_token(p + (IST_MCE * IST_SHSTK_SIZE) - 8); - write_sss_token(p + (IST_NMI * IST_SHSTK_SIZE) - 8); - write_sss_token(p + (IST_DB * IST_SHSTK_SIZE) - 8); - write_sss_token(p + (IST_DF * IST_SHSTK_SIZE) - 8); + write_sss_token(p + (IST_MCE * IST_SHSTK_SIZE) - 8, + va + (IST_MCE * IST_SHSTK_SIZE) - 8); + write_sss_token(p + (IST_NMI * IST_SHSTK_SIZE) - 8, + va + (IST_NMI * IST_SHSTK_SIZE) - 8); + write_sss_token(p + (IST_DB * IST_SHSTK_SIZE) - 8, + va + (IST_DB * IST_SHSTK_SIZE) - 8); + write_sss_token(p + (IST_DF * IST_SHSTK_SIZE) - 8, + va + (IST_DF * IST_SHSTK_SIZE) - 8); } map_pages_to_xen((unsigned long)p, virt_to_mfn(p), 1, PAGE_HYPERVISOR_= SHSTK); =20 /* Primary Shadow Stack. 1x 4k in stack page 5. */ p +=3D PRIMARY_SHSTK_SLOT * PAGE_SIZE; + va +=3D PRIMARY_SHSTK_SLOT * PAGE_SIZE; if ( IS_ENABLED(CONFIG_XEN_SHSTK) ) - write_sss_token(p + PAGE_SIZE - 8); + write_sss_token(p + PAGE_SIZE - 8, va + PAGE_SIZE - 8); =20 map_pages_to_xen((unsigned long)p, virt_to_mfn(p), 1, PAGE_HYPERVISOR_= SHSTK); } @@ -6567,6 +6577,105 @@ void setup_perdomain_slot(const struct vcpu *v, roo= t_pgentry_t *root_pgt) root_pgt[root_table_offset(PERDOMAIN_VIRT_START)]); } =20 +static struct page_info *l2_all_stacks; + +int add_stack(const void *stack, unsigned int cpu) +{ + unsigned long va =3D (unsigned long)PERCPU_STACK_ADDR(cpu); + struct page_info *pg; + l2_pgentry_t *l2tab =3D NULL; + l1_pgentry_t *l1tab =3D NULL; + unsigned int nr; + int rc =3D 0; + + /* + * Assume CPU stack allocation is always serialized, either because it= 's + * done on the BSP during boot, or in case of hotplug, in stop machine + * context. + */ + ASSERT(system_state < SYS_STATE_active || cpu_in_hotplug_context()); + + if ( !opt_asi_hvm && !opt_asi_pv ) + return 0; + + if ( !l2_all_stacks ) + { + l2_all_stacks =3D alloc_domheap_page(NULL, MEMF_no_owner); + if ( !l2_all_stacks ) + return -ENOMEM; + l2tab =3D __map_domain_page(l2_all_stacks); + clear_page(l2tab); + } + else + l2tab =3D __map_domain_page(l2_all_stacks); + + /* code assumes all the stacks can be mapped with a single l2. */ + ASSERT(l3_table_offset((unsigned long)percpu_fix_to_virt(PCPU_STACK_EN= D)) =3D=3D + l3_table_offset((unsigned long)percpu_fix_to_virt(PCPU_STACK_START= ))); + for ( nr =3D 0 ; nr < (1U << STACK_ORDER) ; nr++) + { + l2_pgentry_t *pl2e =3D l2tab + l2_table_offset(va); + + if ( !(l2e_get_flags(*pl2e) & _PAGE_PRESENT) ) + { + pg =3D alloc_domheap_page(NULL, MEMF_no_owner); + if ( !pg ) + { + rc =3D -ENOMEM; + break; + } + l1tab =3D __map_domain_page(pg); + clear_page(l1tab); + l2e_write(pl2e, l2e_from_page(pg, __PAGE_HYPERVISOR_RW)); + } + else if ( !l1tab ) + l1tab =3D map_l1t_from_l2e(*pl2e); + + l1e_write(&l1tab[l1_table_offset(va)], + l1e_from_mfn(virt_to_mfn(stack), + is_shstk_slot(nr) ? __PAGE_HYPERVISOR_SHSTK + : __PAGE_HYPERVISOR_RW)); + + va +=3D PAGE_SIZE; + stack +=3D PAGE_SIZE; + + if ( !l1_table_offset(va) ) + { + unmap_domain_page(l1tab); + l1tab =3D NULL; + } + } + + unmap_domain_page(l1tab); + unmap_domain_page(l2tab); + /* + * Don't care to free the intermediate page-tables on failure, can be = used + * to map other stacks. + */ + + return rc; +} + +int map_all_stacks(struct domain *d) +{ + /* + * Create the per-domain L3. Pass a dummy PERDOMAIN_VIRT_START, but n= ote + * only the per-domain L3 is allocated when nr =3D=3D 0. + */ + int rc =3D create_perdomain_mapping(d, PERDOMAIN_VIRT_START, 0, NULL, = NULL); + l3_pgentry_t *l3tab; + + if ( rc ) + return rc; + + l3tab =3D __map_domain_page(d->arch.perdomain_l3_pg); + l3tab[l3_table_offset((unsigned long)percpu_fix_to_virt(PCPU_STACK_STA= RT))] + =3D l3e_from_page(l2_all_stacks, __PAGE_HYPERVISOR_RW); + unmap_domain_page(l3tab); + + return 0; +} + static void __init __maybe_unused build_assertions(void) { /* diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 5bf81b81b46f..76f7d71b8c1c 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -808,8 +808,6 @@ static void __init noreturn reinit_bsp_stack(void) /* Update SYSCALL trampolines */ percpu_traps_init(); =20 - stack_base[0] =3D stack; - rc =3D setup_cpu_root_pgt(0); if ( rc ) panic("Error %d setting up PV root page table\n", rc); @@ -1771,10 +1769,6 @@ void asmlinkage __init noreturn __start_xen(unsigned= long mbi_p) =20 system_state =3D SYS_STATE_boot; =20 - bsp_stack =3D cpu_alloc_stack(0); - if ( !bsp_stack ) - panic("No memory for BSP stack\n"); - console_init_ring(); vesa_init(); =20 @@ -1961,6 +1955,16 @@ void asmlinkage __init noreturn __start_xen(unsigned= long mbi_p) =20 alternative_branches(); =20 + /* + * Alloc the BSP stack closer to the point where the AP ones also get + * allocated - and after the speculation mitigations have been initial= ized. + * In order to set up the shadow stack token correctly Xen needs to kn= ow + * whether per-CPU mapped stacks are being used. + */ + bsp_stack =3D cpu_alloc_stack(0); + if ( !bsp_stack ) + panic("No memory for BSP stack\n"); + /* * Setup the local per-domain L3 for the BSP also, so it matches the s= tate * of the APs. @@ -2065,8 +2069,17 @@ void asmlinkage __init noreturn __start_xen(unsigned= long mbi_p) info->last_spec_ctrl =3D default_xen_spec_ctrl; } =20 + stack_base[0] =3D bsp_stack; + /* Copy the cpu info block, and move onto the BSP stack. */ - bsp_info =3D get_cpu_info_from_stack((unsigned long)bsp_stack); + if ( opt_asi_hvm || opt_asi_pv ) + { + cpu_set_stack_mappings(0, 0); + bsp_info =3D get_cpu_info_from_stack((unsigned long)PERCPU_STACK_A= DDR(0)); + } + else + bsp_info =3D get_cpu_info_from_stack((unsigned long)bsp_stack); + *bsp_info =3D *info; =20 asm volatile ("mov %[stk], %%rsp; jmp %c[fn]" :: diff --git a/xen/arch/x86/smp.c b/xen/arch/x86/smp.c index 04c6a0572319..18a7196195cf 100644 --- a/xen/arch/x86/smp.c +++ b/xen/arch/x86/smp.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include =20 @@ -433,3 +434,31 @@ long cf_check cpu_down_helper(void *data) ret =3D cpu_down(cpu); return ret; } + +void arch_smp_pre_callfunc(unsigned int cpu) +{ + if ( (!opt_asi_pv && !opt_asi_hvm) || cpu =3D=3D smp_processor_id() || + (!current->domain->arch.asi && !is_idle_vcpu(current)) || + /* + * CPU#0 still runs on the .init stack when the APs are started, d= on't + * attempt to map such stack. + */ + (!cpu && system_state < SYS_STATE_active) ) + return; + + cpu_set_stack_mappings(smp_processor_id(), cpu); +} + +void arch_smp_post_callfunc(unsigned int cpu) +{ + unsigned int i; + + if ( (!opt_asi_pv && !opt_asi_hvm) || cpu =3D=3D smp_processor_id() || + (!current->domain->arch.asi && !is_idle_vcpu(current)) ) + return; + + for ( i =3D 0; i < (1U << STACK_ORDER); i++ ) + percpu_clear_fixmap(PERCPU_STACK_IDX(cpu) + i); + + flush_area_local(PERCPU_STACK_ADDR(cpu), FLUSH_ORDER(STACK_ORDER)); +} diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index d9841ed3b663..548e3102101c 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -579,7 +579,20 @@ static int do_boot_cpu(int apicid, int cpu) printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip); =20 - stack_start =3D stack_base[cpu] + STACK_SIZE - sizeof(struct cpu_info); + if ( opt_asi_hvm || opt_asi_pv ) + { + /* + * Uniformly run with the stack mapping of the per-CPU area (inclu= ding + * the idle vCPU) if ASI is enabled for any domain type. + */ + cpu_set_stack_mappings(cpu, cpu); + + ASSERT(IS_ALIGNED((unsigned long)PERCPU_STACK_ADDR(cpu), STACK_SIZ= E)); + + stack_start =3D PERCPU_STACK_ADDR(cpu) + STACK_SIZE - sizeof(struc= t cpu_info); + } + else + stack_start =3D stack_base[cpu] + STACK_SIZE - sizeof(struct cpu_i= nfo); =20 /* * If per-CPU idle root page table has been allocated, switch to it as @@ -1053,11 +1066,41 @@ void *cpu_alloc_stack(unsigned int cpu) stack =3D alloc_xenheap_pages(STACK_ORDER, memflags); =20 if ( stack ) - memguard_guard_stack(stack); + { + int rc =3D add_stack(stack, cpu); + + if ( rc ) + { + printk(XENLOG_ERR "unable to map stack for CPU %u: %d\n", cpu,= rc); + free_xenheap_pages(stack, STACK_ORDER); + return NULL; + } + memguard_guard_stack(stack, cpu); + } =20 return stack; } =20 +void cpu_set_stack_mappings(unsigned int dest_cpu, unsigned int stack_cpu) +{ + unsigned int i; + + for ( i =3D 0; i < (1U << STACK_ORDER); i++ ) + { + unsigned int flags =3D (is_shstk_slot(i) ? __PAGE_HYPERVISOR_SHSTK + : __PAGE_HYPERVISOR_RW) | + (dest_cpu =3D=3D stack_cpu ? _PAGE_GLOBAL : 0= ); + + if ( is_shstk_slot(i) && dest_cpu !=3D stack_cpu ) + continue; + + percpu_set_fixmap_remote(dest_cpu, PERCPU_STACK_IDX(stack_cpu) + i, + _mfn(virt_to_mfn(stack_base[stack_cpu] + + i * PAGE_SIZE)), + flags); + } +} + static int cpu_smpboot_alloc(unsigned int cpu) { struct cpu_info *info; diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index b4fb95917023..28513c0e3d6a 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -609,10 +609,12 @@ void show_stack_overflow(unsigned int cpu, const stru= ct cpu_user_regs *regs) unsigned long esp =3D regs->rsp; unsigned long curr_stack_base =3D esp & ~(STACK_SIZE - 1); unsigned long esp_top, esp_bottom; + const void *stack =3D current->domain->arch.asi ? PERCPU_STACK_ADDR(cp= u) + : stack_base[cpu]; =20 - if ( _p(curr_stack_base) !=3D stack_base[cpu] ) + if ( _p(curr_stack_base) !=3D stack ) printk("Current stack base %p differs from expected %p\n", - _p(curr_stack_base), stack_base[cpu]); + _p(curr_stack_base), stack); =20 esp_bottom =3D (esp | (STACK_SIZE - 1)) + 1; esp_top =3D esp_bottom - PRIMARY_STACK_SIZE; diff --git a/xen/common/efi/runtime.c b/xen/common/efi/runtime.c index d952c3ba785e..3a8233ed62ac 100644 --- a/xen/common/efi/runtime.c +++ b/xen/common/efi/runtime.c @@ -32,6 +32,7 @@ void efi_rs_leave(struct efi_rs_state *state); =20 #ifndef CONFIG_ARM # include +# include # include # include #endif @@ -85,6 +86,7 @@ struct efi_rs_state efi_rs_enter(void) static const u16 fcw =3D FCW_DEFAULT; static const u32 mxcsr =3D MXCSR_DEFAULT; struct efi_rs_state state =3D { .cr3 =3D 0 }; + root_pgentry_t *efi_pgt, *idle_pgt; =20 if ( mfn_eq(efi_l4_mfn, INVALID_MFN) ) return state; @@ -98,6 +100,16 @@ struct efi_rs_state efi_rs_enter(void) =20 efi_rs_on_cpu =3D smp_processor_id(); =20 + if ( opt_asi_pv || opt_asi_hvm ) + { + /* Insert the idle per-domain slot for the stack mapping. */ + efi_pgt =3D map_domain_page(efi_l4_mfn); + idle_pgt =3D maddr_to_virt(idle_vcpu[efi_rs_on_cpu]->arch.cr3); + efi_pgt[root_table_offset(PERDOMAIN_VIRT_START)].l4 =3D + idle_pgt[root_table_offset(PERDOMAIN_VIRT_START)].l4; + unmap_domain_page(efi_pgt); + } + /* prevent fixup_page_fault() from doing anything */ irq_enter(); =20 diff --git a/xen/common/smp.c b/xen/common/smp.c index a011f541f1ea..04f5aede0d3d 100644 --- a/xen/common/smp.c +++ b/xen/common/smp.c @@ -29,6 +29,7 @@ static struct call_data_struct { void (*func) (void *info); void *info; int wait; + unsigned int caller; cpumask_t selected; } call_data; =20 @@ -63,6 +64,7 @@ void on_selected_cpus( call_data.func =3D func; call_data.info =3D info; call_data.wait =3D wait; + call_data.caller =3D smp_processor_id(); =20 smp_send_call_function_mask(&call_data.selected); =20 @@ -82,6 +84,12 @@ void smp_call_function_interrupt(void) if ( !cpumask_test_cpu(cpu, &call_data.selected) ) return; =20 + /* + * TODO: use bounce buffers to pass callfunc data, so that when using = ASI + * there's no need to map remote CPU stacks. + */ + arch_smp_pre_callfunc(call_data.caller); + irq_enter(); =20 if ( unlikely(!func) ) @@ -102,6 +110,8 @@ void smp_call_function_interrupt(void) } =20 irq_exit(); + + arch_smp_post_callfunc(call_data.caller); } =20 /* diff --git a/xen/include/xen/smp.h b/xen/include/xen/smp.h index 2ca9ff1bfcc1..610c279ca24c 100644 --- a/xen/include/xen/smp.h +++ b/xen/include/xen/smp.h @@ -76,4 +76,9 @@ extern void *stack_base[NR_CPUS]; void initialize_cpu_data(unsigned int cpu); int setup_cpu_root_pgt(unsigned int cpu); =20 +#ifndef HAS_ARCH_SMP_CALLFUNC +static inline void arch_smp_pre_callfunc(unsigned int cpu) {} +static inline void arch_smp_post_callfunc(unsigned int cpu) {} +#endif + #endif /* __XEN_SMP_H__ */ --=20 2.45.2 From nobody Thu Dec 26 22:57:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Fri, 26 Jul 2024 08:32:15 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: alejandro.vallejo@cloud.com, Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH 22/22] x86/mm: zero stack on stack switch or reset Date: Fri, 26 Jul 2024 17:22:06 +0200 Message-ID: <20240726152206.28411-23-roger.pau@citrix.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726152206.28411-1-roger.pau@citrix.com> References: <20240726152206.28411-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1722008339254116600 With the stack mapped on a per-CPU basis there's no risk of other CPUs being able to read the stack contents, but vCPUs running on the current pCPU could read stack rubble from operations of previous vCPUs. The #DF stack is not zeroed because handling of #DF results in a panic. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/include/asm/current.h | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/= current.h index 75b9a341f814..02b4118b03ef 100644 --- a/xen/arch/x86/include/asm/current.h +++ b/xen/arch/x86/include/asm/current.h @@ -177,6 +177,14 @@ unsigned long get_stack_dump_bottom (unsigned long sp); # define SHADOW_STACK_WORK "" #endif =20 +#define ZERO_STACK \ + "test %[stk_size], %[stk_size];" \ + "jz .L_skip_zeroing.%=3D;" \ + "std;" \ + "rep stosb;" \ + "cld;" \ + ".L_skip_zeroing.%=3D:" + #if __GNUC__ >=3D 9 # define ssaj_has_attr_noreturn(fn) __builtin_has_attribute(fn, __noreturn= __) #else @@ -187,10 +195,24 @@ unsigned long get_stack_dump_bottom (unsigned long sp= ); #define switch_stack_and_jump(fn, instr, constr) \ ({ \ unsigned int tmp; \ + bool zero_stack =3D current->domain->arch.asi; \ BUILD_BUG_ON(!ssaj_has_attr_noreturn(fn)); \ + ASSERT(IS_ALIGNED((unsigned long)guest_cpu_user_regs() - \ + PRIMARY_STACK_SIZE + \ + sizeof(struct cpu_info), PAGE_SIZE)); \ + if ( zero_stack ) \ + { \ + unsigned long stack_top =3D get_stack_bottom() & \ + ~(STACK_SIZE - 1); \ + \ + clear_page((void *)stack_top + IST_MCE * PAGE_SIZE); \ + clear_page((void *)stack_top + IST_NMI * PAGE_SIZE); \ + clear_page((void *)stack_top + IST_DB * PAGE_SIZE); \ + } \ __asm__ __volatile__ ( \ SHADOW_STACK_WORK \ "mov %[stk], %%rsp;" \ + ZERO_STACK \ CHECK_FOR_LIVEPATCH_WORK \ instr "[fun]" \ : [val] "=3D&r" (tmp), \ @@ -201,7 +223,13 @@ unsigned long get_stack_dump_bottom (unsigned long sp); ((PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8), \ [stack_mask] "i" (STACK_SIZE - 1), \ _ASM_BUGFRAME_INFO(BUGFRAME_bug, __LINE__, \ - __FILE__, NULL) \ + __FILE__, NULL), \ + /* For stack zeroing. */ \ + "D" ((void *)guest_cpu_user_regs() - 1), \ + [stk_size] "c" \ + (zero_stack ? PRIMARY_STACK_SIZE - sizeof(struct cpu_info)\ + : 0), \ + "a" (0) \ : "memory" ); \ unreachable(); \ }) --=20 2.45.2