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Tue, 23 Jul 2024 14:05:03 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH] x86/APIC: Change APIC reg types to unsigned int Date: Tue, 23 Jul 2024 22:05:00 +0100 Message-Id: <20240723210500.248261-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1721768727974116600 They're all within a 12 bit range of their respective bases, and this preve= nts all the MSR coordinates being calculated in %rcx. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 There's one unpleasant surprise hidden: add/remove: 0/0 grow/shrink: 2/6 up/down: 18/-99 (-81) Function old new delta trace_exit_reason.part 229 245 +16 check_for_unexpected_msi 73 75 +2 fixup_irqs 1239 1237 -2 lapic_resume 860 844 -16 irq_move_cleanup_interrupt 683 667 -16 intel_mcheck_init 1840 1824 -16 setup_local_APIC 985 968 -17 clear_local_APIC 1141 1109 -32 This causes check_for_unexpected_msi() to gain a CLTQ sign extending reg before adding it to APIC_BASE. Furthermore it retains it's SAR from the st= art of apic_isr_read(). If the vector parameter changes from uint8_t to unsigned int, both the CLTQ and SAR go away and and are replaced with regular unsigned logic. (uint8_t) & ~0x1f undergoes promotion to int, but can't be negative due to it's range, and I'm quite surprised that GCC-12 can't figure this out. --- xen/arch/x86/include/asm/apic.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/include/asm/apic.h b/xen/arch/x86/include/asm/api= c.h index a254e49dd13b..1133954e5540 100644 --- a/xen/arch/x86/include/asm/apic.h +++ b/xen/arch/x86/include/asm/apic.h @@ -49,12 +49,12 @@ const struct genapic *apic_x2apic_probe(void); * Basic functions accessing APICs. */ =20 -static inline void apic_mem_write(unsigned long reg, u32 v) +static inline void apic_mem_write(unsigned int reg, u32 v) { *((volatile u32 *)(APIC_BASE+reg)) =3D v; } =20 -static inline u32 apic_mem_read(unsigned long reg) +static inline u32 apic_mem_read(unsigned int reg) { return *((volatile u32 *)(APIC_BASE+reg)); } @@ -63,7 +63,7 @@ static inline u32 apic_mem_read(unsigned long reg) * access the 64-bit ICR register. */ =20 -static inline void apic_wrmsr(unsigned long reg, uint64_t msr_content) +static inline void apic_wrmsr(unsigned int reg, uint64_t msr_content) { if (reg =3D=3D APIC_DFR || reg =3D=3D APIC_ID || reg =3D=3D APIC_LDR || reg =3D=3D APIC_LVR) @@ -72,7 +72,7 @@ static inline void apic_wrmsr(unsigned long reg, uint64_t= msr_content) wrmsrl(MSR_X2APIC_FIRST + (reg >> 4), msr_content); } =20 -static inline uint64_t apic_rdmsr(unsigned long reg) +static inline uint64_t apic_rdmsr(unsigned int reg) { uint64_t msr_content; =20 @@ -83,7 +83,7 @@ static inline uint64_t apic_rdmsr(unsigned long reg) return msr_content; } =20 -static inline void apic_write(unsigned long reg, u32 v) +static inline void apic_write(unsigned int reg, u32 v) { =20 if ( x2apic_enabled ) @@ -92,7 +92,7 @@ static inline void apic_write(unsigned long reg, u32 v) apic_mem_write(reg, v); } =20 -static inline u32 apic_read(unsigned long reg) +static inline u32 apic_read(unsigned int reg) { if ( x2apic_enabled ) return apic_rdmsr(reg); --=20 2.39.2