From nobody Mon Sep 16 18:53:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1721767052; cv=none; d=zohomail.com; s=zohoarc; b=i9LQMlgcdaiiCkTx3Xz6Je3+nYPxIHzIxlEPKGOtVTuLMEnTMGCDoKDskJRHdr2dCyCEzasALs/pIqTTpwllva0hJKKoo1MQMLcCULuzrI5Z5AW6JKIJXO1HJSNTqj+LJm3DdD8XPueUXXTk0DRgPysIs12Wvumg654y445iB/4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1721767052; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xTnCvWYXUz59Smh4B9IrK+4N18OgjPbN1MkpsUI/QxU=; b=LVG63r0dHuHp0qyJVb01Z95ByPtSt21bHY7GiuRrZq7X4HFVT7BKyge4DT/xdad0Afj9hawfe3+shgm81fmMXuLYdHYcjF0TLKwDsBTacPa+HwBqtRCcDsbB8nFFb0g86dl341HCaWvC7J74J8byQhPNgRCYlTs2fSV7Jz3kffQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1721767052389825.2000477695989; Tue, 23 Jul 2024 13:37:32 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.763530.1173791 (Exim 4.92) (envelope-from ) id 1sWMG0-0000Vm-EG; Tue, 23 Jul 2024 20:37:12 +0000 Received: by outflank-mailman (output) from mailman id 763530.1173791; Tue, 23 Jul 2024 20:37:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sWMG0-0000Vf-A2; Tue, 23 Jul 2024 20:37:12 +0000 Received: by outflank-mailman (input) for mailman id 763530; Tue, 23 Jul 2024 20:37:10 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sWMFy-0000VZ-SM for xen-devel@lists.xenproject.org; Tue, 23 Jul 2024 20:37:10 +0000 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [2a00:1450:4864:20::229]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 53145aee-4933-11ef-8776-851b0ebba9a2; Tue, 23 Jul 2024 22:37:05 +0200 (CEST) Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-2eeb1ba0481so88255571fa.2 for ; Tue, 23 Jul 2024 13:37:05 -0700 (PDT) Received: from andrewcoop.eng.citrite.net ([185.25.67.249]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5a51433f904sm5323226a12.40.2024.07.23.13.37.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jul 2024 13:37:04 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 53145aee-4933-11ef-8776-851b0ebba9a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1721767025; x=1722371825; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=xTnCvWYXUz59Smh4B9IrK+4N18OgjPbN1MkpsUI/QxU=; b=jBUl1wQ4EreWy4bxwJosJiaZ1eaWiHesebx2gTHmCB5dL0zZUmt26v79skcYrfsxJA RLm3YqHpTypwf9HidP2BhytJxI4NZ25zsVyiC3ffiAM9+vLRXjhVPrd1PpS06wDWzWC2 WL//i5woaT4QmhyGosfs0ASRQ8nZZsCdjFK+I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721767025; x=1722371825; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=xTnCvWYXUz59Smh4B9IrK+4N18OgjPbN1MkpsUI/QxU=; b=E2hj7r772Uhs+fnTFTZegyscXPpYp0dJi7IIyjLI91rEwYZCebc5S+H3lU0KJdiGQJ Vvjy+wH0Uc53e8Ufeph3b0yKZtr62pvEfIbN1wel3RCg4kY9s/URZnoWN+YPADsxkNTR TCh1iKOqL6TuhNjYti4m53SJDEWWUVGwok6pfa9R51ioFsxMZR40Z5W7lohID/Puc8aB upBuxRS3mJ5dx10lPHvMGzyXL374CPB2tEwvRuRAn0nWYgb1VDGZBb30pnnkWeBjav4U joQ4VGPUGqgCQvrPtlAhcsEBJSE//ZWqXN7dA2nu7jrR8mS3deTy9q2hSs77hUp8amKz 5dOw== X-Gm-Message-State: AOJu0YwfDJ2vzT2ZfJEISST0cwH+vMFb90nuTcURgDJ4X8KnSKBhoX85 5BkZbT/cFpD1ktcykEq9hY2gfJY5Vbf2jhBiPHcozR5VGGSBnZFxfGa0HOr7yGLJ4ZvU0rFJLQt x X-Google-Smtp-Source: AGHT+IE7mJtodrFB2K6FOaV6OwQoLV67I8WGphKexCnwcXBVVUe8SIwC+gtuqir6BGhsMcBqCuOwXQ== X-Received: by 2002:a2e:bc0f:0:b0:2ef:296d:1dda with SMTP id 38308e7fff4ca-2ef296d21bbmr68146581fa.1.1721767024727; Tue, 23 Jul 2024 13:37:04 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH] x86/IO-APIC: Improve APIC_TMR accesses Date: Tue, 23 Jul 2024 21:37:01 +0100 Message-Id: <20240723203701.208018-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1721767054084116600 XenServer's instance of coverity complains of OVERFLOW_BEFORE_WIDEN in mask_and_ack_level_ioapic_irq(), which is ultimately because of v being unsigned long, and (1U << ...) being 32 bits. Introduce a apic_tmr_read() helper like we already have for ISR and IRR, and use it to remove the opencoded access logic. Introduce an is_level boolean= to improve the legibility of the surrounding logic. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/include/asm/apic.h | 5 +++++ xen/arch/x86/io_apic.c | 15 +++++++-------- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/include/asm/apic.h b/xen/arch/x86/include/asm/api= c.h index 7bd66dc6e151..a254e49dd13b 100644 --- a/xen/arch/x86/include/asm/apic.h +++ b/xen/arch/x86/include/asm/apic.h @@ -132,6 +132,11 @@ static inline bool apic_isr_read(uint8_t vector) (vector & 0x1f)) & 1; } =20 +static inline bool apic_tmr_read(unsigned int vector) +{ + return apic_read(APIC_TMR + (vector / 32 * 0x10)) & (1U << (vector % 3= 2)); +} + static inline bool apic_irr_read(unsigned int vector) { return apic_read(APIC_IRR + (vector / 32 * 0x10)) & (1U << (vector % 3= 2)); diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c index ef076bfaf3f5..0fc1aa05fe3e 100644 --- a/xen/arch/x86/io_apic.c +++ b/xen/arch/x86/io_apic.c @@ -1652,8 +1652,7 @@ static bool io_apic_level_ack_pending(unsigned int ir= q) =20 static void cf_check mask_and_ack_level_ioapic_irq(struct irq_desc *desc) { - unsigned long v; - int i; + bool is_level; =20 irq_complete_move(desc); =20 @@ -1679,9 +1678,8 @@ static void cf_check mask_and_ack_level_ioapic_irq(st= ruct irq_desc *desc) * operation to prevent an edge-triggered interrupt escaping meanwhile. * The idea is from Manfred Spraul. --macro */ - i =3D desc->arch.vector; =20 - v =3D apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); + is_level =3D apic_tmr_read(desc->arch.vector); =20 ack_APIC_irq(); =20 @@ -1692,7 +1690,7 @@ static void cf_check mask_and_ack_level_ioapic_irq(st= ruct irq_desc *desc) !io_apic_level_ack_pending(desc->irq)) move_masked_irq(desc); =20 - if ( !(v & (1U << (i & 0x1f))) ) + if ( !is_level ) { spin_lock(&ioapic_lock); __edge_IO_APIC_irq(desc->irq); @@ -1743,13 +1741,14 @@ static void cf_check end_level_ioapic_irq_new(struc= t irq_desc *desc, u8 vector) * operation to prevent an edge-triggered interrupt escaping meanwhile. * The idea is from Manfred Spraul. --macro */ - unsigned int v, i =3D desc->arch.vector; + unsigned int i =3D desc->arch.vector; + bool is_level; =20 /* Manually EOI the old vector if we are moving to the new */ if ( vector && i !=3D vector ) eoi_IO_APIC_irq(desc); =20 - v =3D apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); + is_level =3D apic_tmr_read(i); =20 end_nonmaskable_irq(desc, vector); =20 @@ -1757,7 +1756,7 @@ static void cf_check end_level_ioapic_irq_new(struct = irq_desc *desc, u8 vector) !io_apic_level_ack_pending(desc->irq) ) move_native_irq(desc); =20 - if ( !(v & (1U << (i & 0x1f))) ) + if ( !is_level ) { spin_lock(&ioapic_lock); __mask_IO_APIC_irq(desc->irq); --=20 2.39.2