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[217.31.164.171]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6f1e6795b9sm107981966b.174.2024.06.09.23.53.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 23:53:52 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3391d7a6-26f6-11ef-90a2-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1718002433; x=1718607233; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JceofD7RBMGtBhxQJQYStOTtcfNOzjMXKDJSoSIwmug=; b=JaWqYG55WainfdKf+S2kg5CQ07FYmhbpwoj0U4RaPRbWap2Ml+0/l7yejbeTiIxd5O 0lsUwdYQ+U7xGeGRiA6/Q+T7TnJLAZL8IqJsREGYbqqtxw4s+Swm9rF7b0yaMZXNY64p CqqSg6Q7pf2X9ICvZRS5rd78KC6j6F8UMmZx7t0a9HZWj7cctJ8oeXwTBuQJBlXpVyEu 25wQan0tfVwqUmTQVTOWHdwahyTaezxlaBj0LVNz1lJhI6uQRJxuEycUgPHPJxpWoXoF lgEYCr7sDzCnmwEfhNyl108f70Njx0cAlNLGLwuG4xPVGSnwKvzc2vilpVJFCR/Sf0VE oPJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718002433; x=1718607233; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JceofD7RBMGtBhxQJQYStOTtcfNOzjMXKDJSoSIwmug=; b=UNyhsPTOP3G0fgmNM9MD5Kl1Es69F5YMNkH2jrxsMcNQNqpfUvIymnVNkURpUjb269 wvVdBvQCARlkVQp5ztZNXfbk0YzrpAASQ1cOBSHSPoSOElFz8KLGU3qfJsRhJuucelWL HZIrPfLh6ts08kTk1kBqtosrV4mR9Wc3oK+FaZUgdDbtRX7ee1K3/UqptxdISRblQrGJ ANaKE4DRy8siHr2R0t0pa7rl/J9KMlWBe1KKv9H71rSVcr87t8Mrpb1Vi+efDGL1DasO AuPEGnfxr0k0iyFjQu1N1gV6OrFh3ggvPJLPcA78g+Lg55/0Y+WNS1Bt5PraeE3CTcDL Mviw== X-Gm-Message-State: AOJu0YzfOgGH1k2jZVwKpvmL5DCKU6m26jRI0gl4acXs8eEAKrfV+Bh5 q7PXfXMNos6w6dvEt45T5U/uTGW+sU2RzNRODsSmYLcQaMKCmHgm8XONQQj1Dcv5d+Xtg63Pu9n 4YUf5wA== X-Google-Smtp-Source: AGHT+IENIvSGyjGpOz9XjYX5uB8uPLMvPPR9yA55yF5Sw+1pXuvS4Hh317Vncdxx9CfRgcNU+2A6zw== X-Received: by 2002:a17:906:1c87:b0:a6f:1106:5dc7 with SMTP id a640c23a62f3a-a6f11065e29mr239543466b.5.1718002433493; Sun, 09 Jun 2024 23:53:53 -0700 (PDT) From: Jens Wiklander To: xen-devel@lists.xenproject.org Cc: patches@linaro.org, Jens Wiklander , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Julien Grall Subject: [XEN PATCH v6 4/7] xen/arm: allow dynamically assigned SGI handlers Date: Mon, 10 Jun 2024 08:53:40 +0200 Message-Id: <20240610065343.2594943-5-jens.wiklander@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240610065343.2594943-1-jens.wiklander@linaro.org> References: <20240610065343.2594943-1-jens.wiklander@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1718002454137100001 Content-Type: text/plain; charset="utf-8" Updates so request_irq() can be used with a dynamically assigned SGI irq as input. This prepares for a later patch where an FF-A schedule receiver interrupt handler is installed for an SGI generated by the secure world. From the Arm Base System Architecture v1.0C [1]: "The system shall implement at least eight Non-secure SGIs, assigned to interrupt IDs 0-7." gic_route_irq_to_xen() don't gic_set_irq_type() for SGIs since they are always edge triggered. gic_interrupt() is updated to route the dynamically assigned SGIs to do_IRQ() instead of do_sgi(). The latter still handles the statically assigned SGI handlers like for instance GIC_SGI_CALL_FUNCTION. [1] https://developer.arm.com/documentation/den0094/ Signed-off-by: Jens Wiklander Acked-by: Julien Grall --- v3->v4 - Use IRQ_TYPE_EDGE_RISING instead of DT_IRQ_TYPE_EDGE_RISING v2->v3 - Rename GIC_SGI_MAX to GIC_SGI_STATIC_MAX and rename do_sgi() to do_static_sgi() - Update comment in setup_irq() to mention that SGI irq_desc is banked - Add ASSERT() in do_IRQ() that the irq isn't an SGI before injecting calling vgic_inject_irq() - Initialize local_irqs_type[] range for SGIs as IRQ_TYPE_EDGE_RISING - Adding link to the Arm Base System Architecture v1.0C v1->v2 - Update patch description as requested --- xen/arch/arm/gic.c | 12 +++++++----- xen/arch/arm/include/asm/gic.h | 2 +- xen/arch/arm/irq.c | 18 ++++++++++++++---- 3 files changed, 22 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index b3467a76ae75..3eaf670fd731 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -38,7 +38,7 @@ const struct gic_hw_operations *gic_hw_ops; static void __init __maybe_unused build_assertions(void) { /* Check our enum gic_sgi only covers SGIs */ - BUILD_BUG_ON(GIC_SGI_MAX > NR_GIC_SGI); + BUILD_BUG_ON(GIC_SGI_STATIC_MAX > NR_GIC_SGI); } =20 void register_gic_ops(const struct gic_hw_operations *ops) @@ -117,7 +117,9 @@ void gic_route_irq_to_xen(struct irq_desc *desc, unsign= ed int priority) =20 desc->handler =3D gic_hw_ops->gic_host_irq_type; =20 - gic_set_irq_type(desc, desc->arch.type); + /* SGIs are always edge-triggered, so there is need to set it */ + if ( desc->irq >=3D NR_GIC_SGI) + gic_set_irq_type(desc, desc->arch.type); gic_set_irq_priority(desc, priority); } =20 @@ -322,7 +324,7 @@ void gic_disable_cpu(void) gic_hw_ops->disable_interface(); } =20 -static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi) +static void do_static_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi) { struct irq_desc *desc =3D irq_to_desc(sgi); =20 @@ -367,7 +369,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_f= iq) /* Reading IRQ will ACK it */ irq =3D gic_hw_ops->read_irq(); =20 - if ( likely(irq >=3D 16 && irq < 1020) ) + if ( likely(irq >=3D GIC_SGI_STATIC_MAX && irq < 1020) ) { isb(); do_IRQ(regs, irq, is_fiq); @@ -379,7 +381,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_f= iq) } else if ( unlikely(irq < 16) ) { - do_sgi(regs, irq); + do_static_sgi(regs, irq); } else { diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h index 03f209529b13..541f0eeb808a 100644 --- a/xen/arch/arm/include/asm/gic.h +++ b/xen/arch/arm/include/asm/gic.h @@ -285,7 +285,7 @@ enum gic_sgi { GIC_SGI_EVENT_CHECK, GIC_SGI_DUMP_STATE, GIC_SGI_CALL_FUNCTION, - GIC_SGI_MAX, + GIC_SGI_STATIC_MAX, }; =20 /* SGI irq mode types */ diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index e5fb26a3de2d..c60502444ccf 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -142,7 +142,13 @@ void __init init_IRQ(void) =20 spin_lock(&local_irqs_type_lock); for ( irq =3D 0; irq < NR_LOCAL_IRQS; irq++ ) - local_irqs_type[irq] =3D IRQ_TYPE_INVALID; + { + /* SGIs are always edge-triggered */ + if ( irq < NR_GIC_SGI ) + local_irqs_type[irq] =3D IRQ_TYPE_EDGE_RISING; + else + local_irqs_type[irq] =3D IRQ_TYPE_INVALID; + } spin_unlock(&local_irqs_type_lock); =20 BUG_ON(init_local_irq_data(smp_processor_id()) < 0); @@ -214,9 +220,12 @@ void do_IRQ(struct cpu_user_regs *regs, unsigned int i= rq, int is_fiq) =20 perfc_incr(irqs); =20 - ASSERT(irq >=3D 16); /* SGIs do not come down this path */ + /* Statically assigned SGIs do not come down this path */ + ASSERT(irq >=3D GIC_SGI_STATIC_MAX); =20 - if ( irq < 32 ) + if ( irq < NR_GIC_SGI ) + perfc_incr(ipis); + else if ( irq < NR_GIC_LOCAL_IRQS ) perfc_incr(ppis); else perfc_incr(spis); @@ -250,6 +259,7 @@ void do_IRQ(struct cpu_user_regs *regs, unsigned int ir= q, int is_fiq) * The irq cannot be a PPI, we only support delivery of SPIs to * guests. */ + ASSERT(irq >=3D NR_GIC_SGI); vgic_inject_irq(info->d, NULL, info->virq, true); goto out_no_end; } @@ -386,7 +396,7 @@ int setup_irq(unsigned int irq, unsigned int irqflags, = struct irqaction *new) { gic_route_irq_to_xen(desc, GIC_PRI_IRQ); /* It's fine to use smp_processor_id() because: - * For PPI: irq_desc is banked + * For SGI and PPI: irq_desc is banked * For SPI: we don't care for now which CPU will receive the * interrupt * TODO: Handle case where SPI is setup on different CPU than --=20 2.34.1