From nobody Sun Nov 24 16:45:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=quarantine dis=quarantine) header.from=epam.com ARC-Seal: i=1; a=rsa-sha256; t=1717671918; cv=none; d=zohomail.com; s=zohoarc; b=T7WAmWaWVKauBj3Voi5Wai+iyxhfXf8DcYDtEJiITx/7HbRi0Kk1UewvCeyuqJHb8P48ndOjhH37IrCidffALt1vEnGIILlS5QThUUkz2EaBySL62kbBdc8SVDHgWwoixJnBrfz4Lx6UjsgZArbVWgz4k8BkxODMrlwE9hx92vU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1717671918; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CuLUbm+BavNJb5CVZohY7CHljIymPydf0jPMON8F2vg=; b=ckzi4W3krEYhOYyCE/HK/Iu+srCHb6Bx55pPjEqnQizLW4M2+XpCT2/YUUlLl5WuDf7EMBQyFhTez383+t3gW0tz1iZEwTNTq0f5xrIdFPf5SXCcNI9QuDZ03JGGvw+3jXL09tnKUFMZILxMBuV5obfflugZIYIoRjApxGzjcyg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=quarantine dis=quarantine) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1717671918206373.04478982535863; Thu, 6 Jun 2024 04:05:18 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.736071.1142194 (Exim 4.92) (envelope-from ) id 1sFAvQ-0002xR-VU; Thu, 06 Jun 2024 11:04:56 +0000 Received: by outflank-mailman (output) from mailman id 736071.1142194; Thu, 06 Jun 2024 11:04:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sFAvQ-0002xK-RP; Thu, 06 Jun 2024 11:04:56 +0000 Received: by outflank-mailman (input) for mailman id 736071; Thu, 06 Jun 2024 11:04:55 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sFAvP-0002xD-JN for xen-devel@lists.xenproject.org; Thu, 06 Jun 2024 11:04:55 +0000 Received: from pb-smtp2.pobox.com (pb-smtp2.pobox.com [64.147.108.71]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9965dd70-23f4-11ef-90a2-e314d9c70b13; Thu, 06 Jun 2024 13:04:53 +0200 (CEST) Received: from pb-smtp2.pobox.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 15E1024BBC; Thu, 6 Jun 2024 07:04:52 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp2.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 0E34924BBB; Thu, 6 Jun 2024 07:04:52 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp2.pobox.com (Postfix) with ESMTPSA id D080D24BBA; Thu, 6 Jun 2024 07:04:50 -0400 (EDT) (envelope-from sakib@darkstar.site) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9965dd70-23f4-11ef-90a2-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:mime-version:content-transfer-encoding; s=sasl; bh=j4XJ7kK9wSYGSQ2+xY8WxVZQ/YBI9b9Yv5L00MvO5ts=; b=jmem UtFC/hA1NXCzrtBAxnof7n+EhbwGUnfgM6bUkuVWhWQ45/r1aLi07D5NCKUN3n2d k2dHsuaPwbkzj43LgSZq2EicztgiUb5+WQgSvzER7RzJfB9grQ7Kl2phKHwmZgAN 0/xDdAbTuPGnL/5plrdsH/CsxvOmBMG3Q2JGW5E= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [XEN PATCH v1] x86/intel: optional build of TSX support Date: Thu, 6 Jun 2024 14:04:48 +0300 Message-Id: <20240606110448.2540261-1-Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Pobox-Relay-ID: 9876CF90-23F4-11EF-BAB5-6488940A682E-90055647!pb-smtp2.pobox.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @pobox.com) X-ZM-MESSAGEID: 1717671920501100001 Content-Type: text/plain; charset="utf-8" Transactional Synchronization Extensions are available for certain Intel's CPUs only, hence can be put under CONFIG_INTEL build option. The whole TSX support, even if supported by CPU, may need to be disabled via options, by microcode or through spec-ctrl, depending on a set of specific conditions. To make sure nothing gets accidentally rutime-broken all modifications of global TSX configuration variables is secured by #ifdef's, while variables themselves redefined to 0, so that ones can't mistakenly be written to. Signed-off-by: Sergiy Kibrik --- xen/arch/x86/Makefile | 2 +- xen/arch/x86/include/asm/processor.h | 8 ++++++++ xen/arch/x86/spec_ctrl.c | 4 ++++ 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile index d902fb7acc..286c003ec3 100644 --- a/xen/arch/x86/Makefile +++ b/xen/arch/x86/Makefile @@ -67,7 +67,7 @@ obj-y +=3D srat.o obj-y +=3D string.o obj-y +=3D time.o obj-y +=3D traps.o -obj-y +=3D tsx.o +obj-$(CONFIG_INTEL) +=3D tsx.o obj-y +=3D usercopy.o obj-y +=3D x86_emulate.o obj-$(CONFIG_TBOOT) +=3D tboot.o diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/as= m/processor.h index c26ef9090c..8b12627ab0 100644 --- a/xen/arch/x86/include/asm/processor.h +++ b/xen/arch/x86/include/asm/processor.h @@ -503,9 +503,17 @@ static inline uint8_t get_cpu_family(uint32_t raw, uin= t8_t *model, return fam; } =20 +#ifdef CONFIG_INTEL extern int8_t opt_tsx; extern bool rtm_disabled; void tsx_init(void); +#else +#define opt_tsx 0 /* explicitly indicate TSX is off */ +#define rtm_disabled false /* RTM was not force-disabled */ +static inline void tsx_init(void) +{ +} +#endif =20 void update_mcu_opt_ctrl(void); void set_in_mcu_opt_ctrl(uint32_t mask, uint32_t val); diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 40f6ae0170..6b3631e375 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -116,8 +116,10 @@ static int __init cf_check parse_spec_ctrl(const char = *s) if ( opt_pv_l1tf_domu < 0 ) opt_pv_l1tf_domu =3D 0; =20 +#ifdef CONFIG_INTEL if ( opt_tsx =3D=3D -1 ) opt_tsx =3D -3; +#endif =20 disable_common: opt_rsb_pv =3D false; @@ -2264,6 +2266,7 @@ void __init init_speculation_mitigations(void) * plausibly value TSX higher than Hyperthreading...), disable TSX to * mitigate TAA. */ +#ifdef CONFIG_INTEL if ( opt_tsx =3D=3D -1 && cpu_has_bug_taa && cpu_has_tsx_ctrl && ((hw_smt_enabled && opt_smt) || !boot_cpu_has(X86_FEATURE_SC_VERW_IDLE)) ) @@ -2271,6 +2274,7 @@ void __init init_speculation_mitigations(void) opt_tsx =3D 0; tsx_init(); } +#endif =20 /* * On some SRBDS-affected hardware, it may be safe to relax srb-lock by --=20 2.25.1