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Fri, 24 May 2024 13:03:52 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel , Oleksii Kurochko , Shawn Anastasio , "consulting @ bugseng . com" , Simone Ballarin , Federico Serafini , Nicola Vetrini Subject: [PATCH v2 09/13] xen/bitops: Replace find_first_set_bit() with ffsl() - 1 Date: Fri, 24 May 2024 21:03:34 +0100 Message-Id: <20240524200338.1232391-10-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240524200338.1232391-1-andrew.cooper3@citrix.com> References: <20240524200338.1232391-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1716581056683100007 find_first_set_bit() is a Xen-ism which has undefined behaviour with a 0 input. The latter is well defined with an input of 0, and is a found outsi= de of Xen too. _init_heap_pages() is the one special case here, comparing the LSB of two different addresses. The -1 cancels off both sides of the expression. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel CC: Oleksii Kurochko CC: Shawn Anastasio CC: consulting@bugseng.com CC: Simone Ballarin CC: Federico Serafini CC: Nicola Vetrini v2: * Reorder from later in the series to keep ARM bisectable In an x86 build, we get the following delta: add/remove: 0/0 grow/shrink: 2/4 up/down: 39/-52 (-13) Function old new delta hpet_write 2183 2206 +23 init_heap_pages 1222 1238 +16 dom0_construct_pvh 3959 3958 -1 mapping_order 139 126 -13 guest_physmap_mark_populate_on_demand 1301 1285 -16 vcpumask_to_pcpumask 525 503 -22 so the optimiser improvements for ffsl() really do speak for themselves. I'm surprised by the increase in hpet_write(), but looking at the code, it very clearly wants the same treatment as: commit 188fa82305e72b725473db9146e20cc9abf7bff3 Author: Andrew Cooper Date: Fri Mar 15 11:31:33 2024 xen/vpci: Improve code generation in mask_write() which I'm confident will end up as a net improvement. --- xen/arch/x86/guest/xen/xen.c | 4 ++-- xen/arch/x86/hvm/dom0_build.c | 2 +- xen/arch/x86/hvm/hpet.c | 8 ++++---- xen/arch/x86/include/asm/pt-contig-markers.h | 2 +- xen/arch/x86/mm.c | 2 +- xen/arch/x86/mm/p2m-pod.c | 4 ++-- xen/common/page_alloc.c | 2 +- xen/common/softirq.c | 2 +- xen/drivers/passthrough/amd/iommu_map.c | 2 +- xen/drivers/passthrough/iommu.c | 4 ++-- xen/drivers/passthrough/x86/iommu.c | 4 ++-- 11 files changed, 18 insertions(+), 18 deletions(-) diff --git a/xen/arch/x86/guest/xen/xen.c b/xen/arch/x86/guest/xen/xen.c index d9768cc9527d..7484b3f73ad3 100644 --- a/xen/arch/x86/guest/xen/xen.c +++ b/xen/arch/x86/guest/xen/xen.c @@ -168,14 +168,14 @@ static void cf_check xen_evtchn_upcall(void) =20 while ( pending ) { - unsigned int l1 =3D find_first_set_bit(pending); + unsigned int l1 =3D ffsl(pending) - 1; unsigned long evtchn =3D xchg(&XEN_shared_info->evtchn_pending[l1]= , 0); =20 __clear_bit(l1, &pending); evtchn &=3D ~XEN_shared_info->evtchn_mask[l1]; while ( evtchn ) { - unsigned int port =3D find_first_set_bit(evtchn); + unsigned int port =3D ffsl(evtchn) - 1; =20 __clear_bit(port, &evtchn); port +=3D l1 * BITS_PER_LONG; diff --git a/xen/arch/x86/hvm/dom0_build.c b/xen/arch/x86/hvm/dom0_build.c index b0cb96c3bc76..68c08bbe94f7 100644 --- a/xen/arch/x86/hvm/dom0_build.c +++ b/xen/arch/x86/hvm/dom0_build.c @@ -139,7 +139,7 @@ static int __init pvh_populate_memory_range(struct doma= in *d, order =3D get_order_from_pages(end - start + 1); order =3D min(order ? order - 1 : 0, max_order); /* The order allocated and populated must be aligned to the addres= s. */ - order =3D min(order, start ? find_first_set_bit(start) : MAX_ORDER= ); + order =3D min(order, start ? ffsl(start) - 1 : MAX_ORDER); page =3D alloc_domheap_pages(d, order, dom0_memflags | MEMF_no_scr= ub); if ( page =3D=3D NULL ) { diff --git a/xen/arch/x86/hvm/hpet.c b/xen/arch/x86/hvm/hpet.c index 12b00b770257..37e765e97df9 100644 --- a/xen/arch/x86/hvm/hpet.c +++ b/xen/arch/x86/hvm/hpet.c @@ -335,7 +335,7 @@ static void timer_sanitize_int_route(HPETState *h, unsi= gned int tn) * enabled pick the first irq. */ timer_config(h, tn) |=3D - MASK_INSR(find_first_set_bit(timer_int_route_cap(h, tn)), + MASK_INSR(ffsl(timer_int_route_cap(h, tn)) - 1, HPET_TN_ROUTE); } =20 @@ -409,7 +409,7 @@ static int cf_check hpet_write( { bool active; =20 - i =3D find_first_set_bit(new_val); + i =3D ffsl(new_val) - 1; if ( i >=3D HPET_TIMER_NUM ) break; __clear_bit(i, &new_val); @@ -535,14 +535,14 @@ static int cf_check hpet_write( /* stop/start timers whos state was changed by this write. */ while (stop_timers) { - i =3D find_first_set_bit(stop_timers); + i =3D ffsl(stop_timers) - 1; __clear_bit(i, &stop_timers); hpet_stop_timer(h, i, guest_time); } =20 while (start_timers) { - i =3D find_first_set_bit(start_timers); + i =3D ffsl(start_timers) - 1; __clear_bit(i, &start_timers); hpet_set_timer(h, i, guest_time); } diff --git a/xen/arch/x86/include/asm/pt-contig-markers.h b/xen/arch/x86/in= clude/asm/pt-contig-markers.h index b3c1fe803534..e8c8157d605f 100644 --- a/xen/arch/x86/include/asm/pt-contig-markers.h +++ b/xen/arch/x86/include/asm/pt-contig-markers.h @@ -60,7 +60,7 @@ static bool pt_update_contig_markers(uint64_t *pt, unsign= ed int idx, /* Step 1: Reduce markers in lower numbered entries. */ while ( i ) { - b =3D find_first_set_bit(i); + b =3D ffsl(i) - 1; i &=3D ~(1U << b); if ( GET_MARKER(pt[i]) <=3D b ) break; diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index d968bbbc7315..2a84bdae670b 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -3424,7 +3424,7 @@ static int vcpumask_to_pcpumask( { unsigned int cpu; =20 - vcpu_id =3D find_first_set_bit(vmask); + vcpu_id =3D ffsl(vmask) - 1; vmask &=3D ~(1UL << vcpu_id); vcpu_id +=3D vcpu_bias; if ( (vcpu_id >=3D d->max_vcpus) ) diff --git a/xen/arch/x86/mm/p2m-pod.c b/xen/arch/x86/mm/p2m-pod.c index 1c727c78c833..bd84fe9e27ee 100644 --- a/xen/arch/x86/mm/p2m-pod.c +++ b/xen/arch/x86/mm/p2m-pod.c @@ -684,7 +684,7 @@ unsigned long p2m_pod_decrease_reservation(struct domain *d, gfn_t gfn, unsigned int ord= er) { unsigned long left =3D 1UL << order, ret =3D 0; - unsigned int chunk_order =3D find_first_set_bit(gfn_x(gfn) | left); + unsigned int chunk_order =3D ffsl(gfn_x(gfn) | left) - 1; =20 do { ret +=3D decrease_reservation(d, gfn, chunk_order); @@ -1393,7 +1393,7 @@ guest_physmap_mark_populate_on_demand(struct domain *= d, unsigned long gfn, unsigned int order) { unsigned long left =3D 1UL << order; - unsigned int chunk_order =3D find_first_set_bit(gfn | left); + unsigned int chunk_order =3D ffsl(gfn | left) - 1; int rc; =20 if ( !paging_mode_translate(d) ) diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index 8d3342e95236..054b7edb3989 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -1819,7 +1819,7 @@ static void _init_heap_pages(const struct page_info *= pg, if ( unlikely(!avail[nid]) ) { bool use_tail =3D IS_ALIGNED(s, 1UL << MAX_ORDER) && - (find_first_set_bit(e) <=3D find_first_set_bit(s)); + (ffsl(e) <=3D ffsl(s)); unsigned long n; =20 n =3D init_node_heap(nid, s, nr_pages, &use_tail); diff --git a/xen/common/softirq.c b/xen/common/softirq.c index 321d26902d37..bee4a82009c3 100644 --- a/xen/common/softirq.c +++ b/xen/common/softirq.c @@ -48,7 +48,7 @@ static void __do_softirq(unsigned long ignore_mask) || cpu_is_offline(cpu) ) break; =20 - i =3D find_first_set_bit(pending); + i =3D ffsl(pending) - 1; clear_bit(i, &softirq_pending(cpu)); (*softirq_handlers[i])(); } diff --git a/xen/drivers/passthrough/amd/iommu_map.c b/xen/drivers/passthro= ugh/amd/iommu_map.c index e0f4fe736a8d..f1061bfc798c 100644 --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -137,7 +137,7 @@ static void set_iommu_ptes_present(unsigned long pt_mfn, ASSERT(!pde->u); =20 if ( pde > table ) - ASSERT(pde->ign0 =3D=3D find_first_set_bit(pde - table)); + ASSERT(pde->ign0 =3D=3D ffsl(pde - table) - 1); else ASSERT(pde->ign0 =3D=3D CONTIG_LEVEL_SHIFT); =20 diff --git a/xen/drivers/passthrough/iommu.c b/xen/drivers/passthrough/iomm= u.c index ba18136c461c..50bfd62553ae 100644 --- a/xen/drivers/passthrough/iommu.c +++ b/xen/drivers/passthrough/iommu.c @@ -305,7 +305,7 @@ static unsigned int mapping_order(const struct domain_i= ommu *hd, { unsigned long res =3D dfn_x(dfn) | mfn_x(mfn); unsigned long sizes =3D hd->platform_ops->page_sizes; - unsigned int bit =3D find_first_set_bit(sizes), order =3D 0; + unsigned int bit =3D ffsl(sizes) - 1, order =3D 0; =20 ASSERT(bit =3D=3D PAGE_SHIFT); =20 @@ -313,7 +313,7 @@ static unsigned int mapping_order(const struct domain_i= ommu *hd, { unsigned long mask; =20 - bit =3D find_first_set_bit(sizes); + bit =3D ffsl(sizes) - 1; mask =3D (1UL << bit) - 1; if ( nr <=3D mask || (res & mask) ) break; diff --git a/xen/drivers/passthrough/x86/iommu.c b/xen/drivers/passthrough/= x86/iommu.c index 304a2f5480c7..cc0062b02712 100644 --- a/xen/drivers/passthrough/x86/iommu.c +++ b/xen/drivers/passthrough/x86/iommu.c @@ -641,7 +641,7 @@ struct page_info *iommu_alloc_pgtable(struct domain_iom= mu *hd, if ( contig_mask ) { /* See pt-contig-markers.h for a description of the marker scheme.= */ - unsigned int i, shift =3D find_first_set_bit(contig_mask); + unsigned int i, shift =3D ffsl(contig_mask) - 1; =20 ASSERT((CONTIG_LEVEL_SHIFT & (contig_mask >> shift)) =3D=3D CONTIG= _LEVEL_SHIFT); =20 @@ -652,7 +652,7 @@ struct page_info *iommu_alloc_pgtable(struct domain_iom= mu *hd, =20 for ( i =3D 4; i < PAGE_SIZE / sizeof(*p); i +=3D 4 ) { - p[i + 0] =3D (find_first_set_bit(i) + 0ULL) << shift; + p[i + 0] =3D (ffsl(i) - 1ULL) << shift; p[i + 1] =3D 0; p[i + 2] =3D 1ULL << shift; p[i + 3] =3D 0; --=20 2.30.2