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Thu, 23 May 2024 04:16:39 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 1/7] x86/xstate: Fix initialisation of XSS cache Date: Thu, 23 May 2024 12:16:21 +0100 Message-Id: <20240523111627.28896-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240523111627.28896-1-andrew.cooper3@citrix.com> References: <20240523111627.28896-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1716463029044100001 The clobbering of this_cpu(xcr0) and this_cpu(xss) to architecturally inval= id values is to force the subsequent set_xcr0() and set_msr_xss() to reload the hardware register. While XCR0 is reloaded in xstate_init(), MSR_XSS isn't. This causes get_msr_xss() to return the invalid value, and logic of the form: old =3D get_msr_xss(); set_msr_xss(new); ... set_msr_xss(old); to try and restore the architecturally invalid value. The architecturally invalid value must be purged from the cache, meaning the hardware register must be written at least once. This in turn highlights t= hat the invalid value must only be used in the case that the hardware register = is available. Fixes: f7f4a523927f ("x86/xstate: reset cached register values on resume") Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 v3: * Split out of later patch --- xen/arch/x86/xstate.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index 99cedb4f5e24..75788147966a 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -641,13 +641,6 @@ void xstate_init(struct cpuinfo_x86 *c) return; } =20 - /* - * Zap the cached values to make set_xcr0() and set_msr_xss() really - * write it. - */ - this_cpu(xcr0) =3D 0; - this_cpu(xss) =3D ~0; - cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); feature_mask =3D (((u64)edx << 32) | eax) & XCNTXT_MASK; BUG_ON(!valid_xcr0(feature_mask)); @@ -657,8 +650,19 @@ void xstate_init(struct cpuinfo_x86 *c) * Set CR4_OSXSAVE and run "cpuid" to get xsave_cntxt_size. */ set_in_cr4(X86_CR4_OSXSAVE); + + /* + * Zap the cached values to make set_xcr0() and set_msr_xss() really w= rite + * the hardware register. + */ + this_cpu(xcr0) =3D 0; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1716463035126100003 Right now, xstate_ctxt_size() performs a cross-check of size with CPUID in = for every call. This is expensive, being used for domain create/migrate, as we= ll as to service certain guest CPUID instructions. Instead, arrange to check the sizes once at boot. See the code comments for details. Right now, it just checks hardware against the algorithm expectations. Later patches will add further cross-checking. Introduce the missing X86_XCR0_* and X86_XSS_* constants, and a couple of missing CPUID bits. This is to maximise coverage in the sanity check, even= if we don't expect to use/virtualise some of these features any time soon. Le= ave HDC and HWP alone for now. We don't have CPUID bits from them stored nicel= y. Only perform the cross-checks in debug builds. It's only developers or new hardware liable to trip these checks, and Xen at least tracks "maximum value ever seen in xcr0" for the lifetime of the VM, which we don't want to be tickling in the general case. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 v3: * New On Sapphire Rapids with the whole series inc diagnostics, we get this patte= rn: (XEN) *** check_new_xstate(, 0x00000003) (XEN) *** check_new_xstate(, 0x00000004) (XEN) *** check_new_xstate(, 0x000000e0) (XEN) *** check_new_xstate(, 0x00000200) (XEN) *** check_new_xstate(, 0x00060000) (XEN) *** check_new_xstate(, 0x00000100) (XEN) *** check_new_xstate(, 0x00000400) (XEN) *** check_new_xstate(, 0x00000800) (XEN) *** check_new_xstate(, 0x00001000) (XEN) *** check_new_xstate(, 0x00004000) (XEN) *** check_new_xstate(, 0x00008000) and on Genoa, this pattern: (XEN) *** check_new_xstate(, 0x00000003) (XEN) *** check_new_xstate(, 0x00000004) (XEN) *** check_new_xstate(, 0x000000e0) (XEN) *** check_new_xstate(, 0x00000200) (XEN) *** check_new_xstate(, 0x00000800) (XEN) *** check_new_xstate(, 0x00001000) --- xen/arch/x86/include/asm/x86-defns.h | 25 +++- xen/arch/x86/xstate.c | 150 ++++++++++++++++++++ xen/include/public/arch-x86/cpufeatureset.h | 3 + 3 files changed, 177 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/as= m/x86-defns.h index 48d7a3b7af45..d7602ab225c4 100644 --- a/xen/arch/x86/include/asm/x86-defns.h +++ b/xen/arch/x86/include/asm/x86-defns.h @@ -77,7 +77,7 @@ #define X86_CR4_PKS 0x01000000 /* Protection Key Supervisor */ =20 /* - * XSTATE component flags in XCR0 + * XSTATE component flags in XCR0 | MSR_XSS */ #define X86_XCR0_FP_POS 0 #define X86_XCR0_FP (1ULL << X86_XCR0_FP_POS) @@ -95,11 +95,34 @@ #define X86_XCR0_ZMM (1ULL << X86_XCR0_ZMM_POS) #define X86_XCR0_HI_ZMM_POS 7 #define X86_XCR0_HI_ZMM (1ULL << X86_XCR0_HI_ZMM_POS) +#define X86_XSS_PROC_TRACE (_AC(1, ULL) << 8) #define X86_XCR0_PKRU_POS 9 #define X86_XCR0_PKRU (1ULL << X86_XCR0_PKRU_POS) +#define X86_XSS_PASID (_AC(1, ULL) << 10) +#define X86_XSS_CET_U (_AC(1, ULL) << 11) +#define X86_XSS_CET_S (_AC(1, ULL) << 12) +#define X86_XSS_HDC (_AC(1, ULL) << 13) +#define X86_XSS_UINTR (_AC(1, ULL) << 14) +#define X86_XSS_LBR (_AC(1, ULL) << 15) +#define X86_XSS_HWP (_AC(1, ULL) << 16) +#define X86_XCR0_TILE_CFG (_AC(1, ULL) << 17) +#define X86_XCR0_TILE_DATA (_AC(1, ULL) << 18) #define X86_XCR0_LWP_POS 62 #define X86_XCR0_LWP (1ULL << X86_XCR0_LWP_POS) =20 +#define X86_XCR0_STATES \ + (X86_XCR0_FP | X86_XCR0_SSE | X86_XCR0_YMM | X86_XCR0_BNDREGS | \ + X86_XCR0_BNDCSR | X86_XCR0_OPMASK | X86_XCR0_ZMM | \ + X86_XCR0_HI_ZMM | X86_XCR0_PKRU | X86_XCR0_TILE_CFG | \ + X86_XCR0_TILE_DATA | \ + X86_XCR0_LWP) + +#define X86_XSS_STATES \ + (X86_XSS_PROC_TRACE | X86_XSS_PASID | X86_XSS_CET_U | \ + X86_XSS_CET_S | X86_XSS_HDC | X86_XSS_UINTR | X86_XSS_LBR | \ + X86_XSS_HWP | \ + 0) + /* * Debug status flags in DR6. * diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index 75788147966a..33a5a89719ef 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -604,9 +604,156 @@ static bool valid_xcr0(uint64_t xcr0) if ( !(xcr0 & X86_XCR0_BNDREGS) !=3D !(xcr0 & X86_XCR0_BNDCSR) ) return false; =20 + /* TILE_CFG and TILE_DATA must be the same. */ + if ( !(xcr0 & X86_XCR0_TILE_CFG) !=3D !(xcr0 & X86_XCR0_TILE_DATA) ) + return false; + return true; } =20 +struct xcheck_state { + uint64_t states; + uint32_t uncomp_size; + uint32_t comp_size; +}; + +static void __init check_new_xstate(struct xcheck_state *s, uint64_t new) +{ + uint32_t hw_size; + + BUILD_BUG_ON(X86_XCR0_STATES & X86_XSS_STATES); + + BUG_ON(s->states & new); /* States only increase. */ + BUG_ON(!valid_xcr0(s->states | new)); /* Xen thinks it's a good value.= */ + BUG_ON(new & ~(X86_XCR0_STATES | X86_XSS_STATES)); /* Known state. */ + BUG_ON((new & X86_XCR0_STATES) && + (new & X86_XSS_STATES)); /* User or supervisor, not both. */ + + s->states |=3D new; + if ( new & X86_XCR0_STATES ) + { + if ( !set_xcr0(s->states & X86_XCR0_STATES) ) + BUG(); + } + else + set_msr_xss(s->states & X86_XSS_STATES); + + /* + * Check the uncompressed size. Some XSTATEs are out-of-order and fil= l in + * prior holes in the state area, so we check that the size doesn't + * decrease. + */ + hw_size =3D cpuid_count_ebx(0xd, 0); + + if ( hw_size < s->uncomp_size ) + panic("XSTATE 0x%016"PRIx64", new bits {%63pbl}, uncompressed hw s= ize %#x < prev size %#x\n", + s->states, &new, hw_size, s->uncomp_size); + + s->uncomp_size =3D hw_size; + + /* + * Check the compressed size, if available. All components strictly + * appear in index order. In principle there are no holes, but some + * components have their base address 64-byte aligned for efficiency + * reasons (e.g. AMX-TILE) and there are other components small enough= to + * fit in the gap (e.g. PKRU) without increasing the overall length. + */ + hw_size =3D cpuid_count_ebx(0xd, 1); + + if ( cpu_has_xsavec ) + { + if ( hw_size < s->comp_size ) + panic("XSTATE 0x%016"PRIx64", new bits {%63pbl}, compressed hw= size %#x < prev size %#x\n", + s->states, &new, hw_size, s->comp_size); + + s->comp_size =3D hw_size; + } + else + BUG_ON(hw_size); /* Compressed size reported, but no XSAVEC ? */ +} + +/* + * The {un,}compressed XSTATE sizes are reported by dynamic CPUID value, b= ased + * on the current %XCR0 and MSR_XSS values. The exact layout is also feat= ure + * and vendor specific. Cross-check Xen's understanding against real hard= ware + * on boot. + * + * Testing every combination is prohibitive, so we use a partial approach. + * Starting with nothing active, we add new XSTATEs and check that the CPU= ID + * dynamic values never decreases. + */ +static void __init noinline xstate_check_sizes(void) +{ + uint64_t old_xcr0 =3D get_xcr0(); + uint64_t old_xss =3D get_msr_xss(); + struct xcheck_state s =3D {}; + + /* + * User XSTATEs, increasing by index. + * + * Chronologically, Intel and AMD had identical layouts for AVX (YMM). + * AMD introduced LWP in Fam15h, following immediately on from YMM. I= ntel + * left an LWP-shaped hole when adding MPX (BND{CSR,REGS}) in Skylake. + * AMD removed LWP in Fam17h, putting PKRU in the same space, breaking + * layout compatibility with Intel and having a knock-on effect on all + * subsequent states. + */ + check_new_xstate(&s, X86_XCR0_SSE | X86_XCR0_FP); + + if ( cpu_has_avx ) + check_new_xstate(&s, X86_XCR0_YMM); + + if ( cpu_has_mpx ) + check_new_xstate(&s, X86_XCR0_BNDCSR | X86_XCR0_BNDREGS); + + if ( cpu_has_avx512f ) + check_new_xstate(&s, X86_XCR0_HI_ZMM | X86_XCR0_ZMM | X86_XCR0_OPM= ASK); + + if ( cpu_has_pku ) + check_new_xstate(&s, X86_XCR0_PKRU); + + if ( boot_cpu_has(X86_FEATURE_AMX_TILE) ) + check_new_xstate(&s, X86_XCR0_TILE_DATA | X86_XCR0_TILE_CFG); + + if ( boot_cpu_has(X86_FEATURE_LWP) ) + check_new_xstate(&s, X86_XCR0_LWP); + + /* + * Supervisor XSTATEs, increasing by index. + * + * Intel Broadwell in particular had Processor Trace but no XSAVES. T= here + * doesn't appear to have been a new enumeration when X86_XSS_PROC_TRA= CE + * was introduced in Skylake. + */ + if ( cpu_has_xsaves ) + { + if ( cpu_has_proc_trace ) + check_new_xstate(&s, X86_XSS_PROC_TRACE); + + if ( boot_cpu_has(X86_FEATURE_ENQCMD) ) + check_new_xstate(&s, X86_XSS_PASID); + + if ( boot_cpu_has(X86_FEATURE_CET_SS) || + boot_cpu_has(X86_FEATURE_CET_IBT) ) + { + check_new_xstate(&s, X86_XSS_CET_U); + check_new_xstate(&s, X86_XSS_CET_S); + } + + if ( boot_cpu_has(X86_FEATURE_UINTR) ) + check_new_xstate(&s, X86_XSS_UINTR); + + if ( boot_cpu_has(X86_FEATURE_ARCH_LBR) ) + check_new_xstate(&s, X86_XSS_LBR); + } + + /* Restore old state now the test is done. */ + if ( !set_xcr0(old_xcr0) ) + BUG(); + if ( cpu_has_xsaves ) + set_msr_xss(old_xss); +} + /* Collect the information of processor's extended state */ void xstate_init(struct cpuinfo_x86 *c) { @@ -683,6 +830,9 @@ void xstate_init(struct cpuinfo_x86 *c) =20 if ( setup_xstate_features(bsp) && bsp ) BUG(); + + if ( IS_ENABLED(CONFIG_DEBUG) && bsp ) + xstate_check_sizes(); } =20 int validate_xstate(const struct domain *d, uint64_t xcr0, uint64_t xcr0_a= ccum, diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/publ= ic/arch-x86/cpufeatureset.h index 6627453e3985..d9eba5e9a714 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -266,6 +266,7 @@ XEN_CPUFEATURE(IBPB_RET, 8*32+30) /*A IBPB clears= RSB/RAS too. */ XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instruct= ions */ XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation S= ingle Precision */ XEN_CPUFEATURE(FSRM, 9*32+ 4) /*A Fast Short REP MOVS */ +XEN_CPUFEATURE(UINTR, 9*32+ 5) /* User-mode Interrupts */ XEN_CPUFEATURE(AVX512_VP2INTERSECT, 9*32+8) /*a VP2INTERSECT{D,Q} insns */ XEN_CPUFEATURE(SRBDS_CTRL, 9*32+ 9) /* MSR_MCU_OPT_CTRL and RNGDS_MIT= G_DIS. */ XEN_CPUFEATURE(MD_CLEAR, 9*32+10) /*!A| VERW clears microarchitectura= l buffers */ @@ -274,8 +275,10 @@ XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FO= RCE_ABORT.RTM_ABORT */ XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*A SERIALIZE insn */ XEN_CPUFEATURE(HYBRID, 9*32+15) /* Heterogeneous platform */ XEN_CPUFEATURE(TSXLDTRK, 9*32+16) /*a TSX load tracking suspend/resu= me insns */ +XEN_CPUFEATURE(ARCH_LBR, 9*32+19) /* Architectural Last Branch Reco= rd */ XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking= */ XEN_CPUFEATURE(AVX512_FP16, 9*32+23) /*A AVX512 FP16 instructions */ +XEN_CPUFEATURE(AMX_TILE, 9*32+24) /* AMX Tile architecture */ XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by= Intel) */ XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */ --=20 2.30.2 From nobody Fri Nov 22 13:35:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Thu, 23 May 2024 04:16:44 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 3/7] x86/boot: Collect the Raw CPU Policy earlier on boot Date: Thu, 23 May 2024 12:16:23 +0100 Message-Id: <20240523111627.28896-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240523111627.28896-1-andrew.cooper3@citrix.com> References: <20240523111627.28896-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1716463035039100001 This is a tangle, but it's a small step in the right direction. xstate_init() is shortly going to want data from the Raw policy. calculate_raw_cpu_policy() is sufficiently separate from the other policies= to be safe to do. No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 This is necessary for the forthcoming xstate_{un,}compressed_size() to perf= orm boot-time sanity checks on state components which aren't fully enabled yet.= I decided that doing this was better than extending the xstate_{offsets,sizes= }[] logic that we're intending to retire in due course. v3: * New. --- xen/arch/x86/cpu-policy.c | 1 - xen/arch/x86/setup.c | 4 +++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index b96f4ee55cc4..5b66f002df05 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -845,7 +845,6 @@ static void __init calculate_hvm_def_policy(void) =20 void __init init_guest_cpu_policies(void) { - calculate_raw_cpu_policy(); calculate_host_policy(); =20 if ( IS_ENABLED(CONFIG_PV) ) diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index b50c9c84af6d..8850e5637a98 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -1888,7 +1888,9 @@ void asmlinkage __init noreturn __start_xen(unsigned = long mbi_p) =20 tsx_init(); /* Needs microcode. May change HLE/RTM feature bits. */ =20 - identify_cpu(&boot_cpu_data); + calculate_raw_cpu_policy(); /* Needs microcode. No other dependenices= . */ + + identify_cpu(&boot_cpu_data); /* Needs microcode and raw policy. */ =20 set_in_cr4(X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT); =20 --=20 2.30.2 From nobody Fri Nov 22 13:35:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1716463039; cv=none; d=zohomail.com; s=zohoarc; b=PryOJQ8xLbDRfmbtCw/FYv899Ftc0yjDFSd6Bcq+exjxZhgrRYWu8pNzM7A3sAiVvhVIrnX0t9CHOLDoEbm5PPrb4ZyJncCnrFDmGGARqyz/TWxig8W/nSHrKDRZF+JtYQ7WW5Y10TjVXWyFLB+HlDHYbQTusAr301np+rTF6VQ= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1716463041123100001 We're soon going to need a compressed helper of the same form. The size of the uncompressed image depends on the single element with the largest offset + size. Sadly this isn't always the element with the largest index. Name the per-xstate-component cpu_policy struture, for legibility of the lo= gic in xstate_uncompressed_size(). Cross-check with hardware during boot, and remove hw_uncompressed_size(). This means that the migration paths don't n= eed to mess with XCR0 just to sanity check the buffer size. The users of hw_uncompressed_size() in xstate_init() can (and indeed need) = to be replaced with CPUID instructions. They run with feature_mask in XCR0, a= nd prior to setup_xstate_features() on the BSP. No practical change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 v2: * Scan all features. LWP/APX_F are out-of-order. v3: * Rebase over boot time check. * Use the raw CPU policy. --- xen/arch/x86/domctl.c | 2 +- xen/arch/x86/hvm/hvm.c | 2 +- xen/arch/x86/include/asm/xstate.h | 2 +- xen/arch/x86/xstate.c | 78 +++++++++++++++++----------- xen/include/xen/lib/x86/cpu-policy.h | 2 +- 5 files changed, 51 insertions(+), 35 deletions(-) diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index 9a72d57333e9..c2f2016ed45a 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -833,7 +833,7 @@ long arch_do_domctl( uint32_t offset =3D 0; =20 #define PV_XSAVE_HDR_SIZE (2 * sizeof(uint64_t)) -#define PV_XSAVE_SIZE(xcr0) (PV_XSAVE_HDR_SIZE + xstate_ctxt_size(xcr0)) +#define PV_XSAVE_SIZE(xcr0) (PV_XSAVE_HDR_SIZE + xstate_uncompressed_size(= xcr0)) =20 ret =3D -ESRCH; if ( (evc->vcpu >=3D d->max_vcpus) || diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 2c66fe0f7a16..b84f4d2387d1 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -1190,7 +1190,7 @@ HVM_REGISTER_SAVE_RESTORE(CPU, hvm_save_cpu_ctxt, NUL= L, hvm_load_cpu_ctxt, 1, =20 #define HVM_CPU_XSAVE_SIZE(xcr0) (offsetof(struct hvm_hw_cpu_xsave, \ save_area) + \ - xstate_ctxt_size(xcr0)) + xstate_uncompressed_size(xcr0)) =20 static int cf_check hvm_save_cpu_xsave_states( struct vcpu *v, hvm_domain_context_t *h) diff --git a/xen/arch/x86/include/asm/xstate.h b/xen/arch/x86/include/asm/x= state.h index c08c267884f0..f5115199d4f9 100644 --- a/xen/arch/x86/include/asm/xstate.h +++ b/xen/arch/x86/include/asm/xstate.h @@ -107,7 +107,7 @@ void compress_xsave_states(struct vcpu *v, const void *= src, unsigned int size); void xstate_free_save_area(struct vcpu *v); int xstate_alloc_save_area(struct vcpu *v); void xstate_init(struct cpuinfo_x86 *c); -unsigned int xstate_ctxt_size(u64 xcr0); +unsigned int xstate_uncompressed_size(uint64_t xcr0); =20 static inline uint64_t xgetbv(unsigned int index) { diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index 33a5a89719ef..1b3153600d9c 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -8,6 +8,8 @@ #include #include #include + +#include #include #include #include @@ -183,7 +185,7 @@ void expand_xsave_states(const struct vcpu *v, void *de= st, unsigned int size) /* Check there is state to serialise (i.e. at least an XSAVE_HDR) */ BUG_ON(!v->arch.xcr0_accum); /* Check there is the correct room to decompress into. */ - BUG_ON(size !=3D xstate_ctxt_size(v->arch.xcr0_accum)); + BUG_ON(size !=3D xstate_uncompressed_size(v->arch.xcr0_accum)); =20 if ( !(xstate->xsave_hdr.xcomp_bv & XSTATE_COMPACTION_ENABLED) ) { @@ -245,7 +247,7 @@ void compress_xsave_states(struct vcpu *v, const void *= src, unsigned int size) u64 xstate_bv, valid; =20 BUG_ON(!v->arch.xcr0_accum); - BUG_ON(size !=3D xstate_ctxt_size(v->arch.xcr0_accum)); + BUG_ON(size !=3D xstate_uncompressed_size(v->arch.xcr0_accum)); ASSERT(!xsave_area_compressed(src)); =20 xstate_bv =3D ((const struct xsave_struct *)src)->xsave_hdr.xstate_bv; @@ -553,32 +555,6 @@ void xstate_free_save_area(struct vcpu *v) v->arch.xsave_area =3D NULL; } =20 -static unsigned int hw_uncompressed_size(uint64_t xcr0) -{ - u64 act_xcr0 =3D get_xcr0(); - unsigned int size; - bool ok =3D set_xcr0(xcr0); - - ASSERT(ok); - size =3D cpuid_count_ebx(XSTATE_CPUID, 0); - ok =3D set_xcr0(act_xcr0); - ASSERT(ok); - - return size; -} - -/* Fastpath for common xstate size requests, avoiding reloads of xcr0. */ -unsigned int xstate_ctxt_size(u64 xcr0) -{ - if ( xcr0 =3D=3D xfeature_mask ) - return xsave_cntxt_size; - - if ( xcr0 =3D=3D 0 ) /* TODO: clean up paths passing 0 in here. */ - return 0; - - return hw_uncompressed_size(xcr0); -} - static bool valid_xcr0(uint64_t xcr0) { /* FP must be unconditionally set. */ @@ -611,6 +587,40 @@ static bool valid_xcr0(uint64_t xcr0) return true; } =20 +unsigned int xstate_uncompressed_size(uint64_t xcr0) +{ + unsigned int size =3D XSTATE_AREA_MIN_SIZE, i; + + ASSERT((xcr0 & ~X86_XCR0_STATES) =3D=3D 0); + + if ( xcr0 =3D=3D xfeature_mask ) + return xsave_cntxt_size; + + if ( xcr0 =3D=3D 0 ) /* TODO: clean up paths passing 0 in here. */ + return 0; + + if ( xcr0 <=3D (X86_XCR0_SSE | X86_XCR0_FP) ) + return size; + + /* + * For the non-legacy states, search all activate states and find the + * maximum offset+size. Some states (e.g. LWP, APX_F) are out-of-order + * with respect their index. + */ + xcr0 &=3D ~(X86_XCR0_SSE | X86_XCR0_FP); + for_each_set_bit ( i, &xcr0, 63 ) + { + const struct xstate_component *c =3D &raw_cpu_policy.xstate.comp[i= ]; + unsigned int s =3D c->offset + c->size; + + ASSERT(c->offset && c->size); + + size =3D max(size, s); + } + + return size; +} + struct xcheck_state { uint64_t states; uint32_t uncomp_size; @@ -619,7 +629,7 @@ struct xcheck_state { =20 static void __init check_new_xstate(struct xcheck_state *s, uint64_t new) { - uint32_t hw_size; + uint32_t hw_size, xen_size; =20 BUILD_BUG_ON(X86_XCR0_STATES & X86_XSS_STATES); =20 @@ -651,6 +661,12 @@ static void __init check_new_xstate(struct xcheck_stat= e *s, uint64_t new) =20 s->uncomp_size =3D hw_size; =20 + xen_size =3D xstate_uncompressed_size(s->states & X86_XCR0_STATES); + + if ( xen_size !=3D hw_size ) + panic("XSTATE 0x%016"PRIx64", uncompressed hw size %#x !=3D xen si= ze %#x\n", + s->states, hw_size, xen_size); + /* * Check the compressed size, if available. All components strictly * appear in index order. In principle there are no holes, but some @@ -818,14 +834,14 @@ void xstate_init(struct cpuinfo_x86 *c) * xsave_cntxt_size is the max size required by enabled features. * We know FP/SSE and YMM about eax, and nothing about edx at pres= ent. */ - xsave_cntxt_size =3D hw_uncompressed_size(feature_mask); + xsave_cntxt_size =3D cpuid_count_ebx(0xd, 0); printk("xstate: size: %#x and states: %#"PRIx64"\n", xsave_cntxt_size, xfeature_mask); } else { BUG_ON(xfeature_mask !=3D feature_mask); - BUG_ON(xsave_cntxt_size !=3D hw_uncompressed_size(feature_mask)); + BUG_ON(xsave_cntxt_size !=3D cpuid_count_ebx(0xd, 0)); } =20 if ( setup_xstate_features(bsp) && bsp ) diff --git a/xen/include/xen/lib/x86/cpu-policy.h b/xen/include/xen/lib/x86= /cpu-policy.h index d5e447e9dc06..d26012c6da78 100644 --- a/xen/include/xen/lib/x86/cpu-policy.h +++ b/xen/include/xen/lib/x86/cpu-policy.h @@ -248,7 +248,7 @@ struct cpu_policy }; =20 /* Per-component common state. Valid for i >=3D 2. */ - struct { + struct xstate_component { uint32_t size, offset; bool xss:1, align:1; uint32_t _res_d; --=20 2.30.2 From nobody Fri Nov 22 13:35:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1716463041; cv=none; d=zohomail.com; s=zohoarc; b=a4+GGdKAN+DqUEhY1XzNqn6V/x9g549Z6otxx0IUrYuQlS3AWrv7Wb4m54c8o2mizcBqsXgD3I1waUpizxAKUXBFlzgxqHgDSY/sV3IE/bixSZA1IsPWX8DZ4d7Nb+3JioADmvZzRPqwMddOl9ynLxL5qF//t8dIs0OHelfaGQU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1716463043113100003 Make use of xstate_uncompressed_size() helper rather than maintaining the running calculation while accumulating feature components. The rest of the CPUID data can come direct from the raw cpu policy. All per-component data form an ABI through the behaviour of the X{SAVE,RSTOR}* instructions. Use for_each_set_bit() rather than opencoding a slightly awkward version of it. Mask the attributes in ecx down based on the visible features. This isn't actually necessary for any components or attributes defined at the ti= me of writing (up to AMX), but is added out of an abundance of caution. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 v2: * Tie ALIGN64 to xsavec rather than xsaves. v3: * Tweak commit message. --- xen/arch/x86/cpu-policy.c | 55 +++++++++++-------------------- xen/arch/x86/include/asm/xstate.h | 1 + 2 files changed, 21 insertions(+), 35 deletions(-) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 5b66f002df05..304dc20cfab8 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -193,8 +193,7 @@ static void sanitise_featureset(uint32_t *fs) static void recalculate_xstate(struct cpu_policy *p) { uint64_t xstates =3D XSTATE_FP_SSE; - uint32_t xstate_size =3D XSTATE_AREA_MIN_SIZE; - unsigned int i, Da1 =3D p->xstate.Da1; + unsigned int i, ecx_mask =3D 0, Da1 =3D p->xstate.Da1; =20 /* * The Da1 leaf is the only piece of information preserved in the comm= on @@ -206,61 +205,47 @@ static void recalculate_xstate(struct cpu_policy *p) return; =20 if ( p->basic.avx ) - { xstates |=3D X86_XCR0_YMM; - xstate_size =3D max(xstate_size, - xstate_offsets[X86_XCR0_YMM_POS] + - xstate_sizes[X86_XCR0_YMM_POS]); - } =20 if ( p->feat.mpx ) - { xstates |=3D X86_XCR0_BNDREGS | X86_XCR0_BNDCSR; - xstate_size =3D max(xstate_size, - xstate_offsets[X86_XCR0_BNDCSR_POS] + - xstate_sizes[X86_XCR0_BNDCSR_POS]); - } =20 if ( p->feat.avx512f ) - { xstates |=3D X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM; - xstate_size =3D max(xstate_size, - xstate_offsets[X86_XCR0_HI_ZMM_POS] + - xstate_sizes[X86_XCR0_HI_ZMM_POS]); - } =20 if ( p->feat.pku ) - { xstates |=3D X86_XCR0_PKRU; - xstate_size =3D max(xstate_size, - xstate_offsets[X86_XCR0_PKRU_POS] + - xstate_sizes[X86_XCR0_PKRU_POS]); - } =20 - p->xstate.max_size =3D xstate_size; + /* Subleaf 0 */ + p->xstate.max_size =3D + xstate_uncompressed_size(xstates & ~XSTATE_XSAVES_ONLY); p->xstate.xcr0_low =3D xstates & ~XSTATE_XSAVES_ONLY; p->xstate.xcr0_high =3D (xstates & ~XSTATE_XSAVES_ONLY) >> 32; =20 + /* Subleaf 1 */ p->xstate.Da1 =3D Da1; + if ( p->xstate.xsavec ) + ecx_mask |=3D XSTATE_ALIGN64; + if ( p->xstate.xsaves ) { + ecx_mask |=3D XSTATE_XSS; p->xstate.xss_low =3D xstates & XSTATE_XSAVES_ONLY; p->xstate.xss_high =3D (xstates & XSTATE_XSAVES_ONLY) >> 32; } - else - xstates &=3D ~XSTATE_XSAVES_ONLY; =20 - for ( i =3D 2; i < min(63UL, ARRAY_SIZE(p->xstate.comp)); ++i ) + /* Subleafs 2+ */ + xstates &=3D ~XSTATE_FP_SSE; + BUILD_BUG_ON(ARRAY_SIZE(p->xstate.comp) < 63); + for_each_set_bit ( i, &xstates, 63 ) { - uint64_t curr_xstate =3D 1UL << i; - - if ( !(xstates & curr_xstate) ) - continue; - - p->xstate.comp[i].size =3D xstate_sizes[i]; - p->xstate.comp[i].offset =3D xstate_offsets[i]; - p->xstate.comp[i].xss =3D curr_xstate & XSTATE_XSAVES_ONLY; - p->xstate.comp[i].align =3D curr_xstate & xstate_align; + /* + * Pass through size (eax) and offset (ebx) directly. Visbility of + * attributes in ecx limited by visible features in Da1. + */ + p->xstate.raw[i].a =3D raw_cpu_policy.xstate.raw[i].a; + p->xstate.raw[i].b =3D raw_cpu_policy.xstate.raw[i].b; + p->xstate.raw[i].c =3D raw_cpu_policy.xstate.raw[i].c & ecx_mask; } } =20 diff --git a/xen/arch/x86/include/asm/xstate.h b/xen/arch/x86/include/asm/x= state.h index f5115199d4f9..bfb66dd766b6 100644 --- a/xen/arch/x86/include/asm/xstate.h +++ b/xen/arch/x86/include/asm/xstate.h @@ -40,6 +40,7 @@ extern uint32_t mxcsr_mask; #define XSTATE_XSAVES_ONLY 0 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) =20 +#define XSTATE_XSS (1U << 0) #define XSTATE_ALIGN64 (1U << 1) =20 extern u64 xfeature_mask; --=20 2.30.2 From nobody Fri Nov 22 13:35:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; 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Thu, 23 May 2024 04:16:53 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 6/7] x86/cpuid: Fix handling of XSAVE dynamic leaves Date: Thu, 23 May 2024 12:16:26 +0100 Message-Id: <20240523111627.28896-7-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240523111627.28896-1-andrew.cooper3@citrix.com> References: <20240523111627.28896-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1716463047131100001 First, if XSAVE is available in hardware but not visible to the guest, the dynamic leaves shouldn't be filled in. Second, the comment concerning XSS state is wrong. VT-x doesn't manage host/guest state automatically, but there is provision for "host only" bits= to be set, so the implications are still accurate. Introduce xstate_compressed_size() to mirror the uncompressed one. Cross check it at boot. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu v3: * Adjust commit message about !XSAVE guests * Rebase over boot time cross check * Use raw policy --- xen/arch/x86/cpuid.c | 24 ++++++++-------------- xen/arch/x86/include/asm/xstate.h | 1 + xen/arch/x86/xstate.c | 34 +++++++++++++++++++++++++++++++ 3 files changed, 43 insertions(+), 16 deletions(-) diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 7a38e032146a..a822e80c7ea7 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -330,23 +330,15 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, case XSTATE_CPUID: switch ( subleaf ) { - case 1: - if ( !p->xstate.xsavec && !p->xstate.xsaves ) - break; - - /* - * TODO: Figure out what to do for XSS state. VT-x manages ho= st - * vs guest MSR_XSS automatically, so as soon as we start - * supporting any XSS states, the wrong XSS will be in context. - */ - BUILD_BUG_ON(XSTATE_XSAVES_ONLY !=3D 0); - fallthrough; case 0: - /* - * Read CPUID[0xD,0/1].EBX from hardware. They vary with enab= led - * XSTATE, and appropriate XCR0|XSS are in context. - */ - res->b =3D cpuid_count_ebx(leaf, subleaf); + if ( p->basic.xsave ) + res->b =3D xstate_uncompressed_size(v->arch.xcr0); + break; + + case 1: + if ( p->xstate.xsavec ) + res->b =3D xstate_compressed_size(v->arch.xcr0 | + v->arch.msrs->xss.raw); break; } break; diff --git a/xen/arch/x86/include/asm/xstate.h b/xen/arch/x86/include/asm/x= state.h index bfb66dd766b6..da1d89d2f416 100644 --- a/xen/arch/x86/include/asm/xstate.h +++ b/xen/arch/x86/include/asm/xstate.h @@ -109,6 +109,7 @@ void xstate_free_save_area(struct vcpu *v); int xstate_alloc_save_area(struct vcpu *v); void xstate_init(struct cpuinfo_x86 *c); unsigned int xstate_uncompressed_size(uint64_t xcr0); +unsigned int xstate_compressed_size(uint64_t xstates); =20 static inline uint64_t xgetbv(unsigned int index) { diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index 1b3153600d9c..7b7f2dcaf651 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -621,6 +621,34 @@ unsigned int xstate_uncompressed_size(uint64_t xcr0) return size; } =20 +unsigned int xstate_compressed_size(uint64_t xstates) +{ + unsigned int i, size =3D XSTATE_AREA_MIN_SIZE; + + if ( xstates =3D=3D 0 ) /* TODO: clean up paths passing 0 in here. */ + return 0; + + if ( xstates <=3D (X86_XCR0_SSE | X86_XCR0_FP) ) + return size; + + /* + * For the compressed size, every component matters. Some componenets= are + * rounded up to 64 first. + */ + xstates &=3D ~(X86_XCR0_SSE | X86_XCR0_FP); + for_each_set_bit ( i, &xstates, 63 ) + { + const struct xstate_component *c =3D &raw_cpu_policy.xstate.comp[i= ]; + + if ( c->align ) + size =3D ROUNDUP(size, 64); + + size +=3D c->size; + } + + return size; +} + struct xcheck_state { uint64_t states; uint32_t uncomp_size; @@ -683,6 +711,12 @@ static void __init check_new_xstate(struct xcheck_stat= e *s, uint64_t new) s->states, &new, hw_size, s->comp_size); =20 s->comp_size =3D hw_size; + + xen_size =3D xstate_compressed_size(s->states); + + if ( xen_size !=3D hw_size ) + panic("XSTATE 0x%016"PRIx64", compressed hw size %#x !=3D xen = size %#x\n", + s->states, hw_size, xen_size); } else BUG_ON(hw_size); /* Compressed size reported, but no XSAVEC ? */ --=20 2.30.2 From nobody Fri Nov 22 13:35:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Thu, 23 May 2024 04:16:55 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 7/7] x86/defns: Clean up X86_{XCR0,XSS}_* constants Date: Thu, 23 May 2024 12:16:27 +0100 Message-Id: <20240523111627.28896-8-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240523111627.28896-1-andrew.cooper3@citrix.com> References: <20240523111627.28896-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1716463051097100001 With the exception of one case in read_bndcfgu() which can use ilog2(), the *_POS defines are unused. X86_XCR0_X87 is the name used by both the SDM and APM, rather than X86_XCR0_FP. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 v3: * New --- xen/arch/x86/i387.c | 2 +- xen/arch/x86/include/asm/x86-defns.h | 32 ++++++++++------------------ xen/arch/x86/include/asm/xstate.h | 4 ++-- xen/arch/x86/xstate.c | 18 ++++++++-------- 4 files changed, 23 insertions(+), 33 deletions(-) diff --git a/xen/arch/x86/i387.c b/xen/arch/x86/i387.c index 7a4297cc921e..fcdee10a6e69 100644 --- a/xen/arch/x86/i387.c +++ b/xen/arch/x86/i387.c @@ -369,7 +369,7 @@ void vcpu_setup_fpu(struct vcpu *v, struct xsave_struct= *xsave_area, { v->arch.xsave_area->xsave_hdr.xstate_bv &=3D ~XSTATE_FP_SSE; if ( fcw_default !=3D FCW_DEFAULT ) - v->arch.xsave_area->xsave_hdr.xstate_bv |=3D X86_XCR0_FP; + v->arch.xsave_area->xsave_hdr.xstate_bv |=3D X86_XCR0_X87; } } =20 diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/as= m/x86-defns.h index d7602ab225c4..3bcdbaccd3aa 100644 --- a/xen/arch/x86/include/asm/x86-defns.h +++ b/xen/arch/x86/include/asm/x86-defns.h @@ -79,25 +79,16 @@ /* * XSTATE component flags in XCR0 | MSR_XSS */ -#define X86_XCR0_FP_POS 0 -#define X86_XCR0_FP (1ULL << X86_XCR0_FP_POS) -#define X86_XCR0_SSE_POS 1 -#define X86_XCR0_SSE (1ULL << X86_XCR0_SSE_POS) -#define X86_XCR0_YMM_POS 2 -#define X86_XCR0_YMM (1ULL << X86_XCR0_YMM_POS) -#define X86_XCR0_BNDREGS_POS 3 -#define X86_XCR0_BNDREGS (1ULL << X86_XCR0_BNDREGS_POS) -#define X86_XCR0_BNDCSR_POS 4 -#define X86_XCR0_BNDCSR (1ULL << X86_XCR0_BNDCSR_POS) -#define X86_XCR0_OPMASK_POS 5 -#define X86_XCR0_OPMASK (1ULL << X86_XCR0_OPMASK_POS) -#define X86_XCR0_ZMM_POS 6 -#define X86_XCR0_ZMM (1ULL << X86_XCR0_ZMM_POS) -#define X86_XCR0_HI_ZMM_POS 7 -#define X86_XCR0_HI_ZMM (1ULL << X86_XCR0_HI_ZMM_POS) +#define X86_XCR0_X87 (_AC(1, ULL) << 0) +#define X86_XCR0_SSE (_AC(1, ULL) << 1) +#define X86_XCR0_YMM (_AC(1, ULL) << 2) +#define X86_XCR0_BNDREGS (_AC(1, ULL) << 3) +#define X86_XCR0_BNDCSR (_AC(1, ULL) << 4) +#define X86_XCR0_OPMASK (_AC(1, ULL) << 5) +#define X86_XCR0_ZMM (_AC(1, ULL) << 6) +#define X86_XCR0_HI_ZMM (_AC(1, ULL) << 7) #define X86_XSS_PROC_TRACE (_AC(1, ULL) << 8) -#define X86_XCR0_PKRU_POS 9 -#define X86_XCR0_PKRU (1ULL << X86_XCR0_PKRU_POS) +#define X86_XCR0_PKRU (_AC(1, ULL) << 9) #define X86_XSS_PASID (_AC(1, ULL) << 10) #define X86_XSS_CET_U (_AC(1, ULL) << 11) #define X86_XSS_CET_S (_AC(1, ULL) << 12) @@ -107,11 +98,10 @@ #define X86_XSS_HWP (_AC(1, ULL) << 16) #define X86_XCR0_TILE_CFG (_AC(1, ULL) << 17) #define X86_XCR0_TILE_DATA (_AC(1, ULL) << 18) -#define X86_XCR0_LWP_POS 62 -#define X86_XCR0_LWP (1ULL << X86_XCR0_LWP_POS) +#define X86_XCR0_LWP (_AC(1, ULL) << 62) =20 #define X86_XCR0_STATES \ - (X86_XCR0_FP | X86_XCR0_SSE | X86_XCR0_YMM | X86_XCR0_BNDREGS | \ + (X86_XCR0_X87 | X86_XCR0_SSE | X86_XCR0_YMM | X86_XCR0_BNDREGS | \ X86_XCR0_BNDCSR | X86_XCR0_OPMASK | X86_XCR0_ZMM | \ X86_XCR0_HI_ZMM | X86_XCR0_PKRU | X86_XCR0_TILE_CFG | \ X86_XCR0_TILE_DATA | \ diff --git a/xen/arch/x86/include/asm/xstate.h b/xen/arch/x86/include/asm/x= state.h index da1d89d2f416..f4a8e5f814a0 100644 --- a/xen/arch/x86/include/asm/xstate.h +++ b/xen/arch/x86/include/asm/xstate.h @@ -29,8 +29,8 @@ extern uint32_t mxcsr_mask; #define XSAVE_HDR_OFFSET FXSAVE_SIZE #define XSTATE_AREA_MIN_SIZE (FXSAVE_SIZE + XSAVE_HDR_SIZE) =20 -#define XSTATE_FP_SSE (X86_XCR0_FP | X86_XCR0_SSE) -#define XCNTXT_MASK (X86_XCR0_FP | X86_XCR0_SSE | X86_XCR0_YMM | \ +#define XSTATE_FP_SSE (X86_XCR0_X87 | X86_XCR0_SSE) +#define XCNTXT_MASK (X86_XCR0_X87 | X86_XCR0_SSE | X86_XCR0_YMM | \ X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM |= \ XSTATE_NONLAZY) =20 diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index 7b7f2dcaf651..0ed2541665b3 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -313,7 +313,7 @@ void xsave(struct vcpu *v, uint64_t mask) "=3Dm" (*ptr), \ "a" (lmask), "d" (hmask), "D" (ptr)) =20 - if ( fip_width =3D=3D 8 || !(mask & X86_XCR0_FP) ) + if ( fip_width =3D=3D 8 || !(mask & X86_XCR0_X87) ) { XSAVE("0x48,"); } @@ -366,7 +366,7 @@ void xsave(struct vcpu *v, uint64_t mask) fip_width =3D 8; } #undef XSAVE - if ( mask & X86_XCR0_FP ) + if ( mask & X86_XCR0_X87 ) ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET] =3D fip_width; } =20 @@ -558,7 +558,7 @@ void xstate_free_save_area(struct vcpu *v) static bool valid_xcr0(uint64_t xcr0) { /* FP must be unconditionally set. */ - if ( !(xcr0 & X86_XCR0_FP) ) + if ( !(xcr0 & X86_XCR0_X87) ) return false; =20 /* YMM depends on SSE. */ @@ -599,7 +599,7 @@ unsigned int xstate_uncompressed_size(uint64_t xcr0) if ( xcr0 =3D=3D 0 ) /* TODO: clean up paths passing 0 in here. */ return 0; =20 - if ( xcr0 <=3D (X86_XCR0_SSE | X86_XCR0_FP) ) + if ( xcr0 <=3D (X86_XCR0_SSE | X86_XCR0_X87) ) return size; =20 /* @@ -607,7 +607,7 @@ unsigned int xstate_uncompressed_size(uint64_t xcr0) * maximum offset+size. Some states (e.g. LWP, APX_F) are out-of-order * with respect their index. */ - xcr0 &=3D ~(X86_XCR0_SSE | X86_XCR0_FP); + xcr0 &=3D ~(X86_XCR0_SSE | X86_XCR0_X87); for_each_set_bit ( i, &xcr0, 63 ) { const struct xstate_component *c =3D &raw_cpu_policy.xstate.comp[i= ]; @@ -628,14 +628,14 @@ unsigned int xstate_compressed_size(uint64_t xstates) if ( xstates =3D=3D 0 ) /* TODO: clean up paths passing 0 in here. */ return 0; =20 - if ( xstates <=3D (X86_XCR0_SSE | X86_XCR0_FP) ) + if ( xstates <=3D (X86_XCR0_SSE | X86_XCR0_X87) ) return size; =20 /* * For the compressed size, every component matters. Some componenets= are * rounded up to 64 first. */ - xstates &=3D ~(X86_XCR0_SSE | X86_XCR0_FP); + xstates &=3D ~(X86_XCR0_SSE | X86_XCR0_X87); for_each_set_bit ( i, &xstates, 63 ) { const struct xstate_component *c =3D &raw_cpu_policy.xstate.comp[i= ]; @@ -748,7 +748,7 @@ static void __init noinline xstate_check_sizes(void) * layout compatibility with Intel and having a knock-on effect on all * subsequent states. */ - check_new_xstate(&s, X86_XCR0_SSE | X86_XCR0_FP); + check_new_xstate(&s, X86_XCR0_SSE | X86_XCR0_X87); =20 if ( cpu_has_avx ) check_new_xstate(&s, X86_XCR0_YMM); @@ -1000,7 +1000,7 @@ uint64_t read_bndcfgu(void) : "=3Dm" (*xstate) : "a" (X86_XCR0_BNDCSR), "d" (0), "D" (xstate) ); =20 - bndcsr =3D (void *)xstate + xstate_offsets[X86_XCR0_BNDCSR_POS]; + bndcsr =3D (void *)xstate + xstate_offsets[ilog2(X86_XCR0_BNDCSR)]; } =20 if ( cr0 & X86_CR0_TS ) --=20 2.30.2