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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 May 2024 14:34:24.5194 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 364e5c62-d5e9-4e98-1028-08dc7422f3bb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066EB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4057 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1715697286955100001 Content-Type: text/plain; charset="utf-8" From: Oleksandr Andrushchenko Xen and/or Dom0 may have put values in PCI_COMMAND which they expect to remain unaltered. PCI_COMMAND_SERR bit is a good example: while the guest's (domU) view of this will want to be zero (for now), the host having set it to 1 should be preserved, or else we'd effectively be giving the domU control of the bit. Thus, PCI_COMMAND register needs proper emulation in order to honor host's settings. According to "PCI LOCAL BUS SPECIFICATION, REV. 3.0", section "6.2.2 Device Control" the reset state of the command register is typically 0, so when assigning a PCI device use 0 as the initial state for the guest's (domU) view of the command register. Here is the full list of command register bits with notes about PCI/PCIe specification, and how Xen handles the bit. QEMU's behavior is also documented here since that is our current reference implementation for PCI passthrough. PCI_COMMAND_IO (bit 0) PCIe 6.1: RW PCI LB 3.0: RW QEMU: (emu_mask) QEMU provides an emulated view of this bit. Guest writes do not propagate to hardware. QEMU sets this bit to 1 in hardware if an I/O BAR is exposed to the guest. Xen domU: (rsvdp_mask) We treat this bit as RsvdP for now since we don't yet support I/O BARs for domUs. Xen dom0: We allow dom0 to control this bit freely. PCI_COMMAND_MEMORY (bit 1) PCIe 6.1: RW PCI LB 3.0: RW QEMU: (emu_mask) QEMU provides an emulated view of this bit. Guest writes do not propagate to hardware. QEMU sets this bit to 1 in hardware if a Memory BAR is exposed to the guest. Xen domU/dom0: We handle writes to this bit by mapping/unmapping BAR regions. Xen domU: For devices assigned to DomUs, memory decoding will be disabled at the time of initialization. PCI_COMMAND_MASTER (bit 2) PCIe 6.1: RW PCI LB 3.0: RW QEMU: Pass through writes to hardware. Xen domU/dom0: Pass through writes to hardware. PCI_COMMAND_SPECIAL (bit 3) PCIe 6.1: RO, hardwire to 0 PCI LB 3.0: RW QEMU: Pass through writes to hardware. Xen domU/dom0: Pass through writes to hardware. PCI_COMMAND_INVALIDATE (bit 4) PCIe 6.1: RO, hardwire to 0 PCI LB 3.0: RW QEMU: Pass through writes to hardware. Xen domU/dom0: Pass through writes to hardware. PCI_COMMAND_VGA_PALETTE (bit 5) PCIe 6.1: RO, hardwire to 0 PCI LB 3.0: RW QEMU: Pass through writes to hardware. Xen domU/dom0: Pass through writes to hardware. PCI_COMMAND_PARITY (bit 6) PCIe 6.1: RW PCI LB 3.0: RW QEMU: (emu_mask) QEMU provides an emulated view of this bit. Guest writes do not propagate to hardware. Xen domU: (rsvdp_mask) We treat this bit as RsvdP. Xen dom0: We allow dom0 to control this bit freely. PCI_COMMAND_WAIT (bit 7) PCIe 6.1: RO, hardwire to 0 PCI LB 3.0: hardwire to 0 QEMU: res_mask Xen domU: (rsvdp_mask) We treat this bit as RsvdP. Xen dom0: We allow dom0 to control this bit freely. PCI_COMMAND_SERR (bit 8) PCIe 6.1: RW PCI LB 3.0: RW QEMU: (emu_mask) QEMU provides an emulated view of this bit. Guest writes do not propagate to hardware. Xen domU: (rsvdp_mask) We treat this bit as RsvdP. Xen dom0: We allow dom0 to control this bit freely. PCI_COMMAND_FAST_BACK (bit 9) PCIe 6.1: RO, hardwire to 0 PCI LB 3.0: RW QEMU: (emu_mask) QEMU provides an emulated view of this bit. Guest writes do not propagate to hardware. Xen domU: (rsvdp_mask) We treat this bit as RsvdP. Xen dom0: We allow dom0 to control this bit freely. PCI_COMMAND_INTX_DISABLE (bit 10) PCIe 6.1: RW PCI LB 3.0: RW QEMU: (emu_mask) QEMU provides an emulated view of this bit. Guest writes do not propagate to hardware. QEMU checks if INTx was mapped for a device. If it is not, then guest can't control PCI_COMMAND_INTX_DISABLE bit. Xen domU: We prohibit a guest from enabling INTx if MSI(X) is enabled. Xen dom0: We allow dom0 to control this bit freely. Bits 11-15 PCIe 6.1: RsvdP PCI LB 3.0: Reserved QEMU: res_mask Xen domU/dom0: rsvdp_mask Signed-off-by: Oleksandr Andrushchenko Signed-off-by: Volodymyr Babchuk Signed-off-by: Stewart Hildebrand Reviewed-by: Jan Beulich --- RFC: There is an unaddressed question for Roger: should we update the guest view of the PCI_COMMAND_INTX_DISABLE bit in msi.c/msix.c:control_write()? See prior discussion at [1]. In my opinion, I think we should make sure that hardware state and the guest view are consistent (i.e. don't lie to the guest). [1] https://lore.kernel.org/xen-devel/86b25777-788c-4b9a-8166-a6f8174bedc9@= suse.com/ In v14: - check for 0->1 transition in INTX_DISABLE-setting logic in msi.c:control_write() to match msix.c:control_write() - clear domU-controllable bits in header.c:init_header() In v13: - Update right away (don't defer) PCI_COMMAND_MEMORY bit in guest_cmd variable in cmd_write() - Make comment single line in xen/drivers/vpci/msi.c:control_write() - Rearrange memory decoding disabling snippet in init_header() In v12: - Rework patch using vpci_add_register_mask() - Add bitmask #define in pci_regs.h according to PCIe 6.1 spec, except don't add the RO bits because they were RW in PCI LB 3.0 spec. - Move and expand TODO comment about properly emulating bits - Update guest_cmd in msi.c/msix.c:control_write() - Simplify cmd_write(), thanks to rsvdp_mask - Update commit description In v11: - Fix copy-paste mistake: vpci->msi should be vpci->msix - Handle PCI_COMMAND_IO - Fix condition for disabling INTx in the MSI-X code - Show domU changes to only allowed bits - Show PCI_COMMAND_MEMORY write only after P2M was altered - Update comments in the code In v10: - Added cf_check attribute to guest_cmd_read - Removed warning about non-zero cmd - Updated comment MSI code regarding disabling INTX - Used ternary operator in vpci_add_register() call - Disable memory decoding for DomUs in init_bars() In v9: - Reworked guest_cmd_read - Added handling for more bits Since v6: - fold guest's logic into cmd_write - implement cmd_read, so we can report emulated INTx state to guests - introduce header->guest_cmd to hold the emulated state of the PCI_COMMAND register for guests Since v5: - add additional check for MSI-X enabled while altering INTX bit - make sure INTx disabled while guests enable MSI/MSI-X Since v3: - gate more code on CONFIG_HAS_MSI - removed logic for the case when MSI/MSI-X not enabled --- xen/drivers/vpci/header.c | 60 ++++++++++++++++++++++++++++++++++---- xen/drivers/vpci/msi.c | 8 +++++ xen/drivers/vpci/msix.c | 7 +++++ xen/include/xen/pci_regs.h | 1 + xen/include/xen/vpci.h | 3 ++ 5 files changed, 73 insertions(+), 6 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 47648c395132..2491dbae8901 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -524,9 +524,21 @@ static void cf_check cmd_write( { struct vpci_header *header =3D data; =20 + if ( !is_hardware_domain(pdev->domain) ) + { + const struct vpci *vpci =3D pdev->vpci; + + if ( (vpci->msi && vpci->msi->enabled) || + (vpci->msix && vpci->msix->enabled) ) + cmd |=3D PCI_COMMAND_INTX_DISABLE; + + header->guest_cmd =3D cmd; + } + /* * Let Dom0 play with all the bits directly except for the memory - * decoding one. + * decoding one. Bits that are not allowed for DomU are already + * handled above and by the rsvdp_mask. */ if ( header->bars_mapped !=3D !!(cmd & PCI_COMMAND_MEMORY) ) /* @@ -540,6 +552,14 @@ static void cf_check cmd_write( pci_conf_write16(pdev->sbdf, reg, cmd); } =20 +static uint32_t cf_check guest_cmd_read( + const struct pci_dev *pdev, unsigned int reg, void *data) +{ + const struct vpci_header *header =3D data; + + return header->guest_cmd; +} + static void cf_check bar_write( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) { @@ -754,9 +774,23 @@ static int cf_check init_header(struct pci_dev *pdev) return -EOPNOTSUPP; } =20 - /* Setup a handler for the command register. */ - rc =3D vpci_add_register(pdev->vpci, vpci_hw_read16, cmd_write, PCI_CO= MMAND, - 2, header); + /* + * Setup a handler for the command register. + * + * TODO: If support for emulated bits is added, re-visit how to handle + * PCI_COMMAND_PARITY, PCI_COMMAND_SERR, and PCI_COMMAND_FAST_BACK. + */ + rc =3D vpci_add_register_mask(pdev->vpci, + is_hwdom ? vpci_hw_read16 : guest_cmd_read, + cmd_write, PCI_COMMAND, 2, header, 0, 0, + PCI_COMMAND_RSVDP_MASK | + (is_hwdom ? 0 + : PCI_COMMAND_IO | + PCI_COMMAND_PARITY | + PCI_COMMAND_WAIT | + PCI_COMMAND_SERR | + PCI_COMMAND_FAST_BACK), + 0); if ( rc ) return rc; =20 @@ -836,9 +870,23 @@ static int cf_check init_header(struct pci_dev *pdev) if ( pdev->ignore_bars ) return 0; =20 - /* Disable memory decoding before sizing. */ cmd =3D pci_conf_read16(pdev->sbdf, PCI_COMMAND); - if ( cmd & PCI_COMMAND_MEMORY ) + + /* + * For DomUs, clear PCI_COMMAND_{MASTER,MEMORY,IO} and other + * DomU-controllable bits in PCI_COMMAND. Devices assigned to DomUs wi= ll + * start with memory decoding disabled, and modify_bars() will not be = called + * at the end of this function. + */ + if ( !is_hwdom ) + cmd &=3D ~(PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_INVALIDATE | + PCI_COMMAND_SPECIAL | PCI_COMMAND_MASTER | PCI_COMMAND_ME= MORY | + PCI_COMMAND_IO); + + header->guest_cmd =3D cmd; + + /* Disable memory decoding before sizing. */ + if ( !is_hwdom || (cmd & PCI_COMMAND_MEMORY) ) pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd & ~PCI_COMMAND_MEMOR= Y); =20 for ( i =3D 0; i < num_bars; i++ ) diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c index 30adcf7df05d..3e414e69a432 100644 --- a/xen/drivers/vpci/msi.c +++ b/xen/drivers/vpci/msi.c @@ -57,6 +57,7 @@ static void cf_check control_write( =20 if ( new_enabled ) { + bool old_enabled =3D msi->enabled; /* * If the device is already enabled it means the number of * enabled messages has changed. Disable and re-enable the @@ -70,6 +71,13 @@ static void cf_check control_write( =20 if ( vpci_msi_arch_enable(msi, pdev, vectors) ) return; + + /* Make sure domU doesn't enable INTx while enabling MSI. */ + if ( !old_enabled && !is_hardware_domain(pdev->domain) ) + { + pci_intx(pdev, false); + pdev->vpci->header.guest_cmd |=3D PCI_COMMAND_INTX_DISABLE; + } } else vpci_msi_arch_disable(msi, pdev); diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index 58c16ebdf283..fbe710ab92ef 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -135,6 +135,13 @@ static void cf_check control_write( } } =20 + /* Make sure domU doesn't enable INTx while enabling MSI-X. */ + if ( new_enabled && !msix->enabled && !is_hardware_domain(pdev->domain= ) ) + { + pci_intx(pdev, false); + pdev->vpci->header.guest_cmd |=3D PCI_COMMAND_INTX_DISABLE; + } + msix->masked =3D new_masked; msix->enabled =3D new_enabled; =20 diff --git a/xen/include/xen/pci_regs.h b/xen/include/xen/pci_regs.h index 0bc18efabb74..250ba106dbd3 100644 --- a/xen/include/xen/pci_regs.h +++ b/xen/include/xen/pci_regs.h @@ -48,6 +48,7 @@ #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ +#define PCI_COMMAND_RSVDP_MASK 0xf800 =20 #define PCI_STATUS 0x06 /* 16 bits */ #define PCI_STATUS_IMM_READY 0x01 /* Immediate Readiness */ diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 6e4c972f35ed..2064d9354f5b 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -107,6 +107,9 @@ struct vpci { } bars[PCI_HEADER_NORMAL_NR_BARS + 1]; /* At most 6 BARS + 1 expansion ROM BAR. */ =20 + /* Guest (domU only) view of the PCI_COMMAND register. */ + uint16_t guest_cmd; + /* * Store whether the ROM enable bit is set (doesn't imply ROM BAR * is mapped into guest p2m) if there's a ROM BAR on the device. --=20 2.43.2 From nobody Mon Nov 25 05:41:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1715697295; cv=pass; d=zohomail.com; s=zohoarc; b=YFxTu9mtOIhvE+Y6yX7+VtMImc/yKir51O3ovbyA3SHxb4oYOVvmD2KXCgq4LjLonVcXr5oRNKgoAW7/lvY9o9H57FGPoQSG2ZxSy3rXx08x58jW0NTsWENSss+7eonMmColR7aRYKb6Otd9ecsT7IWtKXh9hbUIrZvomWHea1k= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 May 2024 14:34:35.5296 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e10c92a1-2e7c-4b8d-d914-08dc7422fa4f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6911 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1715697296482100001 Content-Type: text/plain; charset="utf-8" From: Oleksandr Andrushchenko Assign SBDF to the PCI devices being passed through with bus 0. The resulting topology is where PCIe devices reside on the bus 0 of the root complex itself (embedded endpoints). This implementation is limited to 32 devices which are allowed on a single PCI bus. Please note, that at the moment only function 0 of a multifunction device can be passed through. Signed-off-by: Oleksandr Andrushchenko Signed-off-by: Volodymyr Babchuk Signed-off-by: Stewart Hildebrand Acked-by: Jan Beulich --- In v13: - s/depends on/select/ in Kconfig - check pdev->sbdf.fn instead of two booleans in add_virtual_device() - comment #endifs in sched.h - clarify comment about limits in vpci.h with seg/bus limit In v11: - Fixed code formatting - Removed bogus write_unlock() call - Fixed type for new_dev_number In v10: - Removed ASSERT(pcidevs_locked()) - Removed redundant code (local sbdf variable, clearing sbdf during device removal, etc) - Added __maybe_unused attribute to "out:" label - Introduced HAS_VPCI_GUEST_SUPPORT Kconfig option, as this is the first patch where it is used (previously was in "vpci: add hooks for PCI device assign/de-assign") In v9: - Lock in add_virtual_device() replaced with ASSERT (thanks, Stewart) In v8: - Added write lock in add_virtual_device Since v6: - re-work wrt new locking scheme - OT: add ASSERT(pcidevs_write_locked()); to add_virtual_device() Since v5: - s/vpci_add_virtual_device/add_virtual_device and make it static - call add_virtual_device from vpci_assign_device and do not use REGISTER_VPCI_INIT machinery - add pcidevs_locked ASSERT - use DECLARE_BITMAP for vpci_dev_assigned_map Since v4: - moved and re-worked guest sbdf initializers - s/set_bit/__set_bit - s/clear_bit/__clear_bit - minor comment fix s/Virtual/Guest/ - added VPCI_MAX_VIRT_DEV constant (PCI_SLOT(~0) + 1) which will be used later for counting the number of MMIO handlers required for a guest (Julien) Since v3: - make use of VPCI_INIT - moved all new code to vpci.c which belongs to it - changed open-coded 31 to PCI_SLOT(~0) - added comments and code to reject multifunction devices with functions other than 0 - updated comment about vpci_dev_next and made it unsigned int - implement roll back in case of error while assigning/deassigning devices - s/dom%pd/%pd Since v2: - remove casts that are (a) malformed and (b) unnecessary - add new line for better readability - remove CONFIG_HAS_VPCI_GUEST_SUPPORT ifdef's as the relevant vPCI functions are now completely gated with this config - gate common code with CONFIG_HAS_VPCI_GUEST_SUPPORT New in v2 --- xen/drivers/Kconfig | 4 +++ xen/drivers/vpci/vpci.c | 57 +++++++++++++++++++++++++++++++++++++++++ xen/include/xen/sched.h | 10 +++++++- xen/include/xen/vpci.h | 12 +++++++++ 4 files changed, 82 insertions(+), 1 deletion(-) diff --git a/xen/drivers/Kconfig b/xen/drivers/Kconfig index db94393f47a6..20050e9bb8b3 100644 --- a/xen/drivers/Kconfig +++ b/xen/drivers/Kconfig @@ -15,4 +15,8 @@ source "drivers/video/Kconfig" config HAS_VPCI bool =20 +config HAS_VPCI_GUEST_SUPPORT + bool + select HAS_VPCI + endmenu diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 97e115dc5798..23722634d50b 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -40,6 +40,49 @@ extern vpci_register_init_t *const __start_vpci_array[]; extern vpci_register_init_t *const __end_vpci_array[]; #define NUM_VPCI_INIT (__end_vpci_array - __start_vpci_array) =20 +#ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT +static int add_virtual_device(struct pci_dev *pdev) +{ + struct domain *d =3D pdev->domain; + unsigned int new_dev_number; + + if ( is_hardware_domain(d) ) + return 0; + + ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); + + /* + * Each PCI bus supports 32 devices/slots at max or up to 256 when + * there are multi-function ones which are not yet supported. + */ + if ( pdev->sbdf.fn ) + { + gdprintk(XENLOG_ERR, "%pp: only function 0 passthrough supported\n= ", + &pdev->sbdf); + return -EOPNOTSUPP; + } + new_dev_number =3D find_first_zero_bit(d->vpci_dev_assigned_map, + VPCI_MAX_VIRT_DEV); + if ( new_dev_number =3D=3D VPCI_MAX_VIRT_DEV ) + return -ENOSPC; + + __set_bit(new_dev_number, &d->vpci_dev_assigned_map); + + /* + * Both segment and bus number are 0: + * - we emulate a single host bridge for the guest, e.g. segment 0 + * - with bus 0 the virtual devices are seen as embedded + * endpoints behind the root complex + * + * TODO: add support for multi-function devices. + */ + pdev->vpci->guest_sbdf =3D PCI_SBDF(0, 0, new_dev_number, 0); + + return 0; +} + +#endif /* CONFIG_HAS_VPCI_GUEST_SUPPORT */ + void vpci_deassign_device(struct pci_dev *pdev) { unsigned int i; @@ -49,6 +92,12 @@ void vpci_deassign_device(struct pci_dev *pdev) if ( !has_vpci(pdev->domain) || !pdev->vpci ) return; =20 +#ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT + if ( pdev->vpci->guest_sbdf.sbdf !=3D ~0 ) + __clear_bit(pdev->vpci->guest_sbdf.dev, + &pdev->domain->vpci_dev_assigned_map); +#endif + spin_lock(&pdev->vpci->lock); while ( !list_empty(&pdev->vpci->handlers) ) { @@ -103,6 +152,13 @@ int vpci_assign_device(struct pci_dev *pdev) INIT_LIST_HEAD(&pdev->vpci->handlers); spin_lock_init(&pdev->vpci->lock); =20 +#ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT + pdev->vpci->guest_sbdf.sbdf =3D ~0; + rc =3D add_virtual_device(pdev); + if ( rc ) + goto out; +#endif + for ( i =3D 0; i < NUM_VPCI_INIT; i++ ) { rc =3D __start_vpci_array[i](pdev); @@ -110,6 +166,7 @@ int vpci_assign_device(struct pci_dev *pdev) break; } =20 + out: __maybe_unused; if ( rc ) vpci_deassign_device(pdev); =20 diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 132b84199598..2dcd1d1a4f8a 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -486,7 +486,15 @@ struct domain * 2. pdev->vpci->lock */ rwlock_t pci_lock; -#endif +#ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT + /* + * The bitmap which shows which device numbers are already used by the + * virtual PCI bus topology and is used to assign a unique SBDF to the + * next passed through virtual PCI device. + */ + DECLARE_BITMAP(vpci_dev_assigned_map, VPCI_MAX_VIRT_DEV); +#endif /* CONFIG_HAS_VPCI_GUEST_SUPPORT */ +#endif /* CONFIG_HAS_PCI */ =20 #ifdef CONFIG_HAS_PASSTHROUGH struct domain_iommu iommu; diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 2064d9354f5b..980aded26fc1 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -21,6 +21,14 @@ typedef int vpci_register_init_t(struct pci_dev *dev); =20 #define VPCI_ECAM_BDF(addr) (((addr) & 0x0ffff000) >> 12) =20 +/* + * Maximum number of devices supported by the virtual bus topology: + * each PCI bus supports 32 devices/slots at max or up to 256 when + * there are multi-function ones which are not yet supported. + * This limit implies only segment 0, bus 0 is supported. + */ +#define VPCI_MAX_VIRT_DEV (PCI_SLOT(~0) + 1) + #define REGISTER_VPCI_INIT(x, p) \ static vpci_register_init_t *const x##_entry \ __used_section(".data.vpci." p) =3D (x) @@ -175,6 +183,10 @@ struct vpci { struct vpci_arch_msix_entry arch; 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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Andrushchenko , "Stewart Hildebrand" , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Volodymyr Babchuk Subject: [PATCH v14 3/5] xen/arm: translate virtual PCI bus topology for guests Date: Tue, 14 May 2024 10:33:55 -0400 Message-ID: <20240514143400.152280-4-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240514143400.152280-1-stewart.hildebrand@amd.com> References: <20240514143400.152280-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB04.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DB:EE_|MN2PR12MB4254:EE_ X-MS-Office365-Filtering-Correlation-Id: 021f1f9e-2393-4caf-2263-08dc742302d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|376005|82310400017|1800799015; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 May 2024 14:34:49.9292 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 021f1f9e-2393-4caf-2263-08dc742302d9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4254 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1715697312549100001 Content-Type: text/plain; charset="utf-8" From: Oleksandr Andrushchenko There are three originators for the PCI configuration space access: 1. The domain that owns physical host bridge: MMIO handlers are there so we can update vPCI register handlers with the values written by the hardware domain, e.g. physical view of the registers vs guest's view on the configuration space. 2. Guest access to the passed through PCI devices: we need to properly map virtual bus topology to the physical one, e.g. pass the configuration space access to the corresponding physical devices. 3. Emulated host PCI bridge access. It doesn't exist in the physical topology, e.g. it can't be mapped to some physical host bridge. So, all access to the host bridge itself needs to be trapped and emulated. Signed-off-by: Oleksandr Andrushchenko Signed-off-by: Volodymyr Babchuk Signed-off-by: Stewart Hildebrand --- In v11: - Fixed format issues - Added ASSERT_UNREACHABLE() to the dummy implementation of vpci_translate_virtual_device() - Moved variable in vpci_sbdf_from_gpa(), now it is easier to follow the logic in the function Since v9: - Commend about required lock replaced with ASSERT() - Style fixes - call to vpci_translate_virtual_device folded into vpci_sbdf_from_gpa Since v8: - locks moved out of vpci_translate_virtual_device() Since v6: - add pcidevs locking to vpci_translate_virtual_device - update wrt to the new locking scheme Since v5: - add vpci_translate_virtual_device for #ifndef CONFIG_HAS_VPCI_GUEST_SUPPO= RT case to simplify ifdefery - add ASSERT(!is_hardware_domain(d)); to vpci_translate_virtual_device - reset output register on failed virtual SBDF translation Since v4: - indentation fixes - constify struct domain - updated commit message - updates to the new locking scheme (pdev->vpci_lock) Since v3: - revisit locking - move code to vpci.c Since v2: - pass struct domain instead of struct vcpu - constify arguments where possible - gate relevant code with CONFIG_HAS_VPCI_GUEST_SUPPORT New in v2 --- xen/arch/arm/vpci.c | 47 +++++++++++++++++++++++++++++++---------- xen/drivers/vpci/vpci.c | 24 +++++++++++++++++++++ xen/include/xen/vpci.h | 12 +++++++++++ 3 files changed, 72 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/vpci.c b/xen/arch/arm/vpci.c index 3bc4bb55082a..7a6a0017d132 100644 --- a/xen/arch/arm/vpci.c +++ b/xen/arch/arm/vpci.c @@ -7,31 +7,51 @@ =20 #include =20 -static pci_sbdf_t vpci_sbdf_from_gpa(const struct pci_host_bridge *bridge, - paddr_t gpa) +static bool vpci_sbdf_from_gpa(struct domain *d, + const struct pci_host_bridge *bridge, + paddr_t gpa, pci_sbdf_t *sbdf) { - pci_sbdf_t sbdf; + bool translated =3D true; + + ASSERT(sbdf); =20 if ( bridge ) { - sbdf.sbdf =3D VPCI_ECAM_BDF(gpa - bridge->cfg->phys_addr); - sbdf.seg =3D bridge->segment; - sbdf.bus +=3D bridge->cfg->busn_start; + sbdf->sbdf =3D VPCI_ECAM_BDF(gpa - bridge->cfg->phys_addr); + sbdf->seg =3D bridge->segment; + sbdf->bus +=3D bridge->cfg->busn_start; } else - sbdf.sbdf =3D VPCI_ECAM_BDF(gpa - GUEST_VPCI_ECAM_BASE); + { + /* + * For the passed through devices we need to map their virtual SBDF + * to the physical PCI device being passed through. + */ + sbdf->sbdf =3D VPCI_ECAM_BDF(gpa - GUEST_VPCI_ECAM_BASE); + read_lock(&d->pci_lock); + translated =3D vpci_translate_virtual_device(d, sbdf); + read_unlock(&d->pci_lock); + } =20 - return sbdf; + return translated; } =20 static int vpci_mmio_read(struct vcpu *v, mmio_info_t *info, register_t *r, void *p) { struct pci_host_bridge *bridge =3D p; - pci_sbdf_t sbdf =3D vpci_sbdf_from_gpa(bridge, info->gpa); + pci_sbdf_t sbdf; /* data is needed to prevent a pointer cast on 32bit */ unsigned long data; =20 + ASSERT(!bridge =3D=3D !is_hardware_domain(v->domain)); + + if ( !vpci_sbdf_from_gpa(v->domain, bridge, info->gpa, &sbdf) ) + { + *r =3D ~0UL; + return 1; + } + if ( vpci_ecam_read(sbdf, ECAM_REG_OFFSET(info->gpa), 1U << info->dabt.size, &data) ) { @@ -39,7 +59,7 @@ static int vpci_mmio_read(struct vcpu *v, mmio_info_t *in= fo, return 1; } =20 - *r =3D ~0ul; + *r =3D ~0UL; =20 return 0; } @@ -48,7 +68,12 @@ static int vpci_mmio_write(struct vcpu *v, mmio_info_t *= info, register_t r, void *p) { struct pci_host_bridge *bridge =3D p; - pci_sbdf_t sbdf =3D vpci_sbdf_from_gpa(bridge, info->gpa); + pci_sbdf_t sbdf; + + ASSERT(!bridge =3D=3D !is_hardware_domain(v->domain)); + + if ( !vpci_sbdf_from_gpa(v->domain, bridge, info->gpa, &sbdf) ) + return 1; =20 return vpci_ecam_write(sbdf, ECAM_REG_OFFSET(info->gpa), 1U << info->dabt.size, r); diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 23722634d50b..98b294f09688 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -81,6 +81,30 @@ static int add_virtual_device(struct pci_dev *pdev) return 0; } =20 +/* + * Find the physical device which is mapped to the virtual device + * and translate virtual SBDF to the physical one. + */ +bool vpci_translate_virtual_device(const struct domain *d, pci_sbdf_t *sbd= f) +{ + const struct pci_dev *pdev; + + ASSERT(!is_hardware_domain(d)); + ASSERT(rw_is_locked(&d->pci_lock)); + + for_each_pdev ( d, pdev ) + { + if ( pdev->vpci && (pdev->vpci->guest_sbdf.sbdf =3D=3D sbdf->sbdf)= ) + { + /* Replace guest SBDF with the physical one. */ + *sbdf =3D pdev->sbdf; + return true; + } + } + + return false; +} + #endif /* CONFIG_HAS_VPCI_GUEST_SUPPORT */ =20 void vpci_deassign_device(struct pci_dev *pdev) diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 980aded26fc1..7e5a0f0c50c1 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -303,6 +303,18 @@ static inline bool __must_check vpci_process_pending(s= truct vcpu *v) } #endif =20 +#ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT +bool vpci_translate_virtual_device(const struct domain *d, pci_sbdf_t *sbd= f); +#else +static inline bool vpci_translate_virtual_device(const struct domain *d, + pci_sbdf_t *sbdf) +{ + ASSERT_UNREACHABLE(); + + return false; +} +#endif + #endif =20 /* --=20 2.43.2 From nobody Mon Nov 25 05:41:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1715697323; cv=pass; d=zohomail.com; s=zohoarc; b=GeDkmHagPprVVl04aqLZy7ssR2NwHVphtohVqfdKnduqeXf3+oVqics0bzKeRrR7aq7OLY3cyEXfz7c5+sHIULW9TzO2dOlWmvarfdXZ/lXrv2UQBnOJEH7IT0Hzcpx/Wjp49nlSmH42jfdiGpH4lmAS5Bxa7hs6vOea9mqsKmk= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1715697323; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Oleksandr Andrushchenko , "Stewart Hildebrand" , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Julien Grall , Volodymyr Babchuk Subject: [PATCH v14 4/5] xen/arm: account IO handlers for emulated PCI MSI-X Date: Tue, 14 May 2024 10:33:56 -0400 Message-ID: <20240514143400.152280-5-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240514143400.152280-1-stewart.hildebrand@amd.com> References: <20240514143400.152280-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DC:EE_|CY8PR12MB7610:EE_ X-MS-Office365-Filtering-Correlation-Id: 054dbf8b-0e00-4edc-a5e0-08dc74230b3f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|376005|1800799015|36860700004; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 May 2024 14:35:04.0384 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 054dbf8b-0e00-4edc-a5e0-08dc74230b3f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DC.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7610 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1715697324629100001 Content-Type: text/plain; charset="utf-8" From: Oleksandr Andrushchenko At the moment, we always allocate an extra 16 slots for IO handlers (see MAX_IO_HANDLER). So while adding IO trap handlers for the emulated MSI-X registers we need to explicitly tell that we have additional IO handlers, so those are accounted. Signed-off-by: Oleksandr Andrushchenko Acked-by: Julien Grall Signed-off-by: Volodymyr Babchuk Signed-off-by: Stewart Hildebrand --- This actually moved here from the part 2 of the prep work for PCI passthrough on Arm as it seems to be the proper place for it. Since v5: - optimize with IS_ENABLED(CONFIG_HAS_PCI_MSI) since VPCI_MAX_VIRT_DEV is defined unconditionally New in v5 --- xen/arch/arm/vpci.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vpci.c b/xen/arch/arm/vpci.c index 7a6a0017d132..348ba0fbc860 100644 --- a/xen/arch/arm/vpci.c +++ b/xen/arch/arm/vpci.c @@ -130,6 +130,8 @@ static int vpci_get_num_handlers_cb(struct domain *d, =20 unsigned int domain_vpci_get_num_mmio_handlers(struct domain *d) { + unsigned int count; + if ( !has_vpci(d) ) return 0; =20 @@ -150,7 +152,17 @@ unsigned int domain_vpci_get_num_mmio_handlers(struct = domain *d) * For guests each host bridge requires one region to cover the * configuration space. At the moment, we only expose a single host br= idge. */ - return 1; + count =3D 1; + + /* + * There's a single MSI-X MMIO handler that deals with both PBA + * and MSI-X tables per each PCI device being passed through. + * Maximum number of emulated virtual devices is VPCI_MAX_VIRT_DEV. + */ + if ( IS_ENABLED(CONFIG_HAS_PCI_MSI) ) + count +=3D VPCI_MAX_VIRT_DEV; + + return count; } =20 /* --=20 2.43.2 From nobody Mon Nov 25 05:41:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1715697340; cv=pass; d=zohomail.com; s=zohoarc; b=jPyJXoc4MQvl8G4OCxKtWTJqsttNzmj2cHNaqwSdXF/E96KYvx5QTohqyCS1kGX7wQ2zsiOBBPj9GDJMuDQODHXnFwcTs7qAuo2M5kKLbpVdMuz3t7/+kTeSO3HzqAgtgqgpH8OpIz/nIiS5mmZJMbhBju8Nsd4t3Z98Vk+rJk0= ARC-Message-Signature: i=2; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 May 2024 14:35:16.6850 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b0ef63ab-8853-4624-2182-08dc742312ce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7977 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1715697340761100001 Content-Type: text/plain; charset="utf-8" From: Volodymyr Babchuk Guest can try to read config space using different access sizes: 8, 16, 32, 64 bits. We need to take this into account when we are returning an error back to MMIO handler, otherwise it is possible to provide more data than requested: i.e. guest issues LDRB instruction to read one byte, but we are writing 0xFFFFFFFFFFFFFFFF in the target register. Signed-off-by: Volodymyr Babchuk Signed-off-by: Stewart Hildebrand Acked-by: Julien Grall --- v9->10: * New patch in v10. --- xen/arch/arm/vpci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vpci.c b/xen/arch/arm/vpci.c index 348ba0fbc860..aaf9d9120c3d 100644 --- a/xen/arch/arm/vpci.c +++ b/xen/arch/arm/vpci.c @@ -41,6 +41,8 @@ static int vpci_mmio_read(struct vcpu *v, mmio_info_t *in= fo, { struct pci_host_bridge *bridge =3D p; pci_sbdf_t sbdf; + const uint8_t access_size =3D (1 << info->dabt.size) * 8; + const uint64_t access_mask =3D GENMASK_ULL(access_size - 1, 0); /* data is needed to prevent a pointer cast on 32bit */ unsigned long data; =20 @@ -48,7 +50,7 @@ static int vpci_mmio_read(struct vcpu *v, mmio_info_t *in= fo, =20 if ( !vpci_sbdf_from_gpa(v->domain, bridge, info->gpa, &sbdf) ) { - *r =3D ~0UL; + *r =3D access_mask; return 1; } =20 @@ -59,7 +61,7 @@ static int vpci_mmio_read(struct vcpu *v, mmio_info_t *in= fo, return 1; } =20 - *r =3D ~0UL; + *r =3D access_mask; =20 return 0; } --=20 2.43.2