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Thu, 18 Apr 2024 08:52:49 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH v2 1/2] x86/spec: fix reporting of BHB clearing usage from guest entry points Date: Thu, 18 Apr 2024 17:52:07 +0200 Message-ID: <20240418155208.7771-2-roger.pau@citrix.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240418155208.7771-1-roger.pau@citrix.com> References: <20240418155208.7771-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1713455589448100003 Reporting whether the BHB clearing on entry is done for the different domai= ns types based on cpu_has_bhb_seq is incorrect, as that variable signals wheth= er there's a BHB clearing sequence selected, but that alone doesn't imply that such sequence is used from the PV and/or HVM entry points. Instead use opt_bhb_entry_{pv,hvm} which do signal whether BHB clearing is performed on entry from PV/HVM. Fixes: 689ad48ce9cf ('x86/spec-ctrl: Wire up the Native-BHI software sequen= ces') Signed-off-by: Roger Pau Monn=C3=A9 Reviewed-by: Andrew Cooper Reviewed-by: Jan Beulich --- Changes since v1: - Also fix usage of cpu_has_bhb_seq when deciding whether to print "None". --- xen/arch/x86/spec_ctrl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index dd01e30844a1..1e831c1c108e 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -634,7 +634,7 @@ static void __init print_details(enum ind_thunk thunk) (boot_cpu_has(X86_FEATURE_SC_MSR_HVM) || boot_cpu_has(X86_FEATURE_SC_RSB_HVM) || boot_cpu_has(X86_FEATURE_IBPB_ENTRY_HVM) || - cpu_has_bhb_seq || amd_virt_spec_ctrl || + opt_bhb_entry_hvm || amd_virt_spec_ctrl || opt_eager_fpu || opt_verw_hvm) ? "" : = " None", boot_cpu_has(X86_FEATURE_SC_MSR_HVM) ? " MSR_SPEC_CTRL" : = "", (boot_cpu_has(X86_FEATURE_SC_MSR_HVM) || @@ -643,7 +643,7 @@ static void __init print_details(enum ind_thunk thunk) opt_eager_fpu ? " EAGER_FPU" : = "", opt_verw_hvm ? " VERW" : = "", boot_cpu_has(X86_FEATURE_IBPB_ENTRY_HVM) ? " IBPB-entry" : = "", - cpu_has_bhb_seq ? " BHB-entry" : = ""); + opt_bhb_entry_hvm ? " BHB-entry" : = ""); =20 #endif #ifdef CONFIG_PV @@ -651,14 +651,14 @@ static void __init print_details(enum ind_thunk thunk) (boot_cpu_has(X86_FEATURE_SC_MSR_PV) || boot_cpu_has(X86_FEATURE_SC_RSB_PV) || boot_cpu_has(X86_FEATURE_IBPB_ENTRY_PV) || - cpu_has_bhb_seq || + opt_bhb_entry_pv || opt_eager_fpu || opt_verw_pv) ? "" : = " None", boot_cpu_has(X86_FEATURE_SC_MSR_PV) ? " MSR_SPEC_CTRL" : = "", boot_cpu_has(X86_FEATURE_SC_RSB_PV) ? " RSB" : = "", opt_eager_fpu ? " EAGER_FPU" : = "", opt_verw_pv ? " VERW" : = "", boot_cpu_has(X86_FEATURE_IBPB_ENTRY_PV) ? " IBPB-entry" : = "", - cpu_has_bhb_seq ? " BHB-entry" : = ""); + opt_bhb_entry_pv ? " BHB-entry" : = ""); =20 printk(" XPTI (64-bit PV only): Dom0 %s, DomU %s (with%s PCID)\n", opt_xpti_hwdom ? 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Thu, 18 Apr 2024 08:52:52 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH v2 2/2] x86/spec: adjust logic to logic that elides lfence Date: Thu, 18 Apr 2024 17:52:08 +0200 Message-ID: <20240418155208.7771-3-roger.pau@citrix.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240418155208.7771-1-roger.pau@citrix.com> References: <20240418155208.7771-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1713455591764100001 It's currently too restrictive by just checking whether there's a BHB clear= ing sequence selected. It should instead check whether BHB clearing is used on entry from PV or HVM specifically. Switch to use opt_bhb_entry_{pv,hvm} instead, and then remove cpu_has_bhb_s= eq since it no longer has any users. Reported-by: Jan Beulich Fixes: 954c983abcee ('x86/spec-ctrl: Software BHB-clearing sequences') Signed-off-by: Roger Pau Monn=C3=A9 Reviewed-by: Andrew Cooper Reviewed-by: Jan Beulich --- Changes since v1: - New in this version. There (possibly) still a bit of overhead for dom0 if BHB clearing is not us= ed for dom0, as Xen would still add the lfence if domUs require it. --- xen/arch/x86/include/asm/cpufeature.h | 3 --- xen/arch/x86/spec_ctrl.c | 6 +++--- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/a= sm/cpufeature.h index 743f11f98940..9bc553681f4a 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -235,9 +235,6 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_bug_fpu_ptrs boot_cpu_has(X86_BUG_FPU_PTRS) #define cpu_bug_null_seg boot_cpu_has(X86_BUG_NULL_SEG) =20 -#define cpu_has_bhb_seq (boot_cpu_has(X86_SPEC_BHB_TSX) || \ - boot_cpu_has(X86_SPEC_BHB_LOOPS)) - enum _cache_type { CACHE_TYPE_NULL =3D 0, CACHE_TYPE_DATA =3D 1, diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 1e831c1c108e..40f6ae017010 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -2328,7 +2328,7 @@ void __init init_speculation_mitigations(void) * unconditional WRMSR. If we do have it, or we're not using any * prior conditional block, then it's safe to drop the LFENCE. */ - if ( !cpu_has_bhb_seq && + if ( !opt_bhb_entry_pv && (boot_cpu_has(X86_FEATURE_SC_MSR_PV) || !boot_cpu_has(X86_FEATURE_IBPB_ENTRY_PV)) ) setup_force_cpu_cap(X86_SPEC_NO_LFENCE_ENTRY_PV); @@ -2344,7 +2344,7 @@ void __init init_speculation_mitigations(void) * active in the block that is skipped when interrupting guest * context, then it's safe to drop the LFENCE. */ - if ( !cpu_has_bhb_seq && + if ( !opt_bhb_entry_pv && (boot_cpu_has(X86_FEATURE_SC_MSR_PV) || (!boot_cpu_has(X86_FEATURE_IBPB_ENTRY_PV) && !boot_cpu_has(X86_FEATURE_SC_RSB_PV))) ) @@ -2356,7 +2356,7 @@ void __init init_speculation_mitigations(void) * A BHB sequence, if used, is the only conditional action, so if = we * don't have it, we don't need the safety LFENCE. */ - if ( !cpu_has_bhb_seq ) + if ( !opt_bhb_entry_hvm ) setup_force_cpu_cap(X86_SPEC_NO_LFENCE_ENTRY_VMX); } =20 --=20 2.44.0