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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id q26-20020a170906b29a00b00a51dd500071sm3119108ejz.169.2024.04.10.03.37.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Apr 2024 03:37:22 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 515209ed-f726-11ee-b907-491648fe20b8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1712745443; x=1713350243; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=5RnrHsqwo8RE6VxgiL7wXAgM6cFtodAhRpuovZ8ouyQ=; b=WCU5F1n19eq9nPA/A1K6F0D3mtBWjczKGySI5Us5nDbFIlrp9eVkoI5rk2gTu8Jn5U 8BmmIZCQPEXvLbMiHWpwVhwHKt6WCPVbn+18kBl6aEC0Dcws9H4gtl0gGI1rZXnc53Xp mnAQ37o8nKDGtx2W8nbSRha8bIx20VPPtY4kU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712745443; x=1713350243; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=5RnrHsqwo8RE6VxgiL7wXAgM6cFtodAhRpuovZ8ouyQ=; b=puiYW4Q5sC7UFfc9+89lbvE6YgeIMFxloelg72IaWcrCMHhcWLIGNKlpenORke27OY l6u4usYvuzrGvnmGyXHEwigDOgiQBsyK+c9VkZZB43BC9dj1HpogYoSw6v6HXQ0mIc02 rS3b7A8uxCOMxbQxjmWGVLuOyIWbJijk0SDHjnpu5j7jiGrhfBjIPoECf3jZWkz4Q48c vr+CNJyHnStegTw2IMb38jgg9D3rNzO7F2ssCbNzF7b6m0AqkGEzTivHQ3bgOsl24FzC gz7D1VtH7aD4wbUeMgZrbyvb6M6Yuu1JWj7/8fM24KO5+sYFZcxT2EYGU3Y/AjkqY0m5 K8ag== X-Gm-Message-State: AOJu0YyfstVcEGRKhh5unN3XRVK9q3WevaQPTi6f/H49Un6vHhEcd+EG vmW6FpUUZa2GpEHVfVgG8sNPhWpzsyCBK4xLXawy1FQQZS+EYcUNMh8weOYDcAYSCeqKI9G8cJv 3NDU= X-Google-Smtp-Source: AGHT+IG8gb4DS5jcGyz6sU2P/vzuWizZhMjMNBkm9dGGQlUhdiW3iKckHTuovbDgvPPGugQbgx56RQ== X-Received: by 2002:a17:906:3b09:b0:a51:95f1:4308 with SMTP id g9-20020a1709063b0900b00a5195f14308mr1710222ejf.51.1712745443215; Wed, 10 Apr 2024 03:37:23 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , "consulting @ bugseng . com" , Roberto Bagnara , Federico Serafini , Nicola Vetrini Subject: [PATCH] x86/hvm: Fix Misra Rule 19.1 regression Date: Wed, 10 Apr 2024 11:37:21 +0100 Message-Id: <20240410103721.593839-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1712745475365100001 Despite noticing an impending Rule 19.1 violation, the adjustment made (the uint32_t cast) wasn't sufficient to avoid it. Try again. Fixes: 6a98383b0877 ("x86/HVM: clear upper halves of GPRs upon entry from 3= 2-bit code") Signed-off-by: Andrew Cooper Reviewed-by: Stefano Stabellini --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Stefano Stabellini CC: consulting@bugseng.com CC: Roberto Bagnara CC: Federico Serafini CC: Nicola Vetrini --- xen/arch/x86/include/asm/hvm/hvm.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/= hvm/hvm.h index 595253babeaf..899233fb257b 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -575,16 +575,16 @@ static inline void hvm_sanitize_regs_fields(struct cp= u_user_regs *regs, if ( compat ) { /* Clear GPR upper halves, to counteract guests playing games. */ - regs->rbp =3D (uint32_t)regs->ebp; - regs->rbx =3D (uint32_t)regs->ebx; - regs->rax =3D (uint32_t)regs->eax; - regs->rcx =3D (uint32_t)regs->ecx; - regs->rdx =3D (uint32_t)regs->edx; - regs->rsi =3D (uint32_t)regs->esi; - regs->rdi =3D (uint32_t)regs->edi; - regs->rip =3D (uint32_t)regs->eip; - regs->rflags =3D (uint32_t)regs->eflags; - regs->rsp =3D (uint32_t)regs->esp; + regs->rbp =3D (uint32_t)regs->rbp; + regs->rbx =3D (uint32_t)regs->rbx; + regs->rax =3D (uint32_t)regs->rax; + regs->rcx =3D (uint32_t)regs->rcx; + regs->rdx =3D (uint32_t)regs->rdx; + regs->rsi =3D (uint32_t)regs->rsi; + regs->rdi =3D (uint32_t)regs->rdi; + regs->rip =3D (uint32_t)regs->rip; + regs->rflags =3D (uint32_t)regs->rflags; + regs->rsp =3D (uint32_t)regs->rsp; } =20 #ifndef NDEBUG base-commit: f48299cad5c3c69fdc2c101517a6dab9c9827ea5 --=20 2.30.2