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([91.123.150.27]) by smtp.gmail.com with ESMTPSA id o10-20020a170906774a00b00a4e472a8e54sm4303773ejn.48.2024.04.02.05.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 05:06:26 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 6f588766-f0e9-11ee-afe5-a90da7624cb6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1712059587; x=1712664387; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tXRZoBkrIDvTNlJOaVE/UOyTf5pEhamTYtPvWBSXQsk=; b=esPGY+207ziPSlGR2WMnGvXhm9ZuWmciDd189gdL304K8diM8adCf3n0lepVZbf1HD IIBlkwHuiGlLQqxPFDsEfh3KDVEQ1r2ehCCvFMG42hnVW6iZqhFEDpkMoL8BxHUDW9nF fPqC0CV3tf/fHuzA0I8aPeKZA1azp3GJTVE4uOK48guZBxniQ7dNiASef0s1fHppuqci UQ1WKZgEGWv6+PSpUg2Qlt7xwAlOTxrdKl6rmTp2yCaF8TBvb+OQdqhVC1BWrF4vjFlJ SozTZan5s9+oKIsECDkteexQO6YwA7cHTXHqWa4UqVTzSijj8wAfQrnNur+X94R5VXoo +tRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712059587; x=1712664387; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tXRZoBkrIDvTNlJOaVE/UOyTf5pEhamTYtPvWBSXQsk=; b=hTAt+S0Ul0s4v9HnTMu8Gv/h63jAPB0AEmtIbhc8kIUJmq8+0bWzeS6oohYzB9kaxr CkTIHWhRPy3tGM9LJ7bK+ATWPIv1aRzIRUDH3xCFJti1EQLi06JN3IwVj6NKxNJXMSpq w0s0y/aZYv1pvKAXbGp62+UVozVROHIuFUTkp529Oe6HU+fTYlNxV827cF3HUzUoclY0 xIATq9LKjChErPfbhCrbkQxJ6jHzGi0p04DeEuLEY2bQkH6x4R/AQvIVHrqRDH/OlRzk XgItNTmr95r/ClPuYQm8fH+mj3HdlJ/vFxUWJ7rA5tJ0oyB+Ng5atZRqg8A9Ccc3mq2j LehQ== X-Gm-Message-State: AOJu0YyRWOTfKmLZOACJ5l+4rhdPbWOw9bpBo9QrT6ZZZWPMu54y/G8c 4xxGkveocMN3ennwM76ZDyRIAVArJFxo1kfnoSrfnZt3ivs5zTMuWExljjNH X-Google-Smtp-Source: AGHT+IGNo07CHKnbFiMZtWKQ71TkvlQlT2xcaqfjvF/EUoSPv9tbYhEuPzH760lZuULNadQG3B+zSw== X-Received: by 2002:a17:906:2c12:b0:a4e:282d:b540 with SMTP id e18-20020a1709062c1200b00a4e282db540mr6688228ejh.77.1712059587098; Tue, 02 Apr 2024 05:06:27 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Cc: Oleksandr Tyshchenko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Peng Fan Subject: [PATCH 1/2] xen/arm: Add i.MX UART early printk support Date: Tue, 2 Apr 2024 15:05:56 +0300 Message-Id: <20240402120557.1822253-2-olekstysh@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240402120557.1822253-1-olekstysh@gmail.com> References: <20240402120557.1822253-1-olekstysh@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1712059611402100003 Content-Type: text/plain; charset="utf-8" From: Oleksandr Tyshchenko Tested on i.MX 8M Mini only, but I guess, it should be suitable for other i.MX8M* SoCs (those UART device tree nodes contain "fsl,imx6q-uart" compatible string). Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Michal Orzel --- I selected the following configs for enabling early printk: CONFIG_EARLY_UART_CHOICE_IMX_UART=3Dy CONFIG_EARLY_UART_IMX_UART=3Dy CONFIG_EARLY_PRINTK=3Dy CONFIG_EARLY_UART_BASE_ADDRESS=3D0x30890000 CONFIG_EARLY_PRINTK_INC=3D"debug-imx-uart.inc" --- --- xen/arch/arm/Kconfig.debug | 14 +++++ xen/arch/arm/arm64/debug-imx-uart.inc | 38 ++++++++++++++ xen/arch/arm/include/asm/imx-uart.h | 76 +++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) create mode 100644 xen/arch/arm/arm64/debug-imx-uart.inc create mode 100644 xen/arch/arm/include/asm/imx-uart.h diff --git a/xen/arch/arm/Kconfig.debug b/xen/arch/arm/Kconfig.debug index eec860e88e..a15d08f214 100644 --- a/xen/arch/arm/Kconfig.debug +++ b/xen/arch/arm/Kconfig.debug @@ -68,6 +68,16 @@ choice provide the parameters for the i.MX LPUART rather than selecting one of the platform specific options below if you know the parameters for the port. + config EARLY_UART_CHOICE_IMX_UART + select EARLY_UART_IMX_UART + depends on ARM_64 + bool "Early printk via i.MX UART" + help + Say Y here if you wish the early printk to direct their + output to a i.MX UART. You can use this option to + provide the parameters for the i.MX UART rather than + selecting one of the platform specific options below if + you know the parameters for the port. config EARLY_UART_CHOICE_MESON select EARLY_UART_MESON depends on ARM_64 @@ -199,6 +209,9 @@ config EARLY_UART_EXYNOS4210 config EARLY_UART_IMX_LPUART select EARLY_PRINTK bool +config EARLY_UART_IMX_UART + select EARLY_PRINTK + bool config EARLY_UART_MESON select EARLY_PRINTK bool @@ -304,6 +317,7 @@ config EARLY_PRINTK_INC default "debug-cadence.inc" if EARLY_UART_CADENCE default "debug-exynos4210.inc" if EARLY_UART_EXYNOS4210 default "debug-imx-lpuart.inc" if EARLY_UART_IMX_LPUART + default "debug-imx-uart.inc" if EARLY_UART_IMX_UART default "debug-meson.inc" if EARLY_UART_MESON default "debug-mvebu.inc" if EARLY_UART_MVEBU default "debug-pl011.inc" if EARLY_UART_PL011 diff --git a/xen/arch/arm/arm64/debug-imx-uart.inc b/xen/arch/arm/arm64/deb= ug-imx-uart.inc new file mode 100644 index 0000000000..27a68b1ed5 --- /dev/null +++ b/xen/arch/arm/arm64/debug-imx-uart.inc @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * xen/arch/arm/arm64/debug-imx-uart.inc + * + * i.MX8M* specific debug code + * + * Copyright (C) 2024 EPAM Systems Inc. + */ + +#include + +/* + * Wait UART to be ready to transmit + * rb: register which contains the UART base address + * rc: scratch register + */ +.macro early_uart_ready xb, c +1: + ldr w\c, [\xb, #IMX21_UTS] /* <- Test register */ + tst w\c, #UTS_TXFULL /* Check TxFIFO FULL bit */ + bne 1b /* Wait for the UART to be ready */ +.endm + +/* + * UART transmit character + * rb: register which contains the UART base address + * rt: register which contains the character to transmit + */ +.macro early_uart_transmit xb, wt + str \wt, [\xb, #URTX0] /* -> Transmitter Register */ +.endm + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/imx-uart.h b/xen/arch/arm/include/asm= /imx-uart.h new file mode 100644 index 0000000000..413a81dd44 --- /dev/null +++ b/xen/arch/arm/include/asm/imx-uart.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * xen/arch/arm/include/asm/imx-uart.h + * + * Common constant definition between early printk and the UART driver + * + * Copyright (C) 2024 EPAM Systems Inc. + */ + +#ifndef __ASM_ARM_IMX_UART_H__ +#define __ASM_ARM_IMX_UART_H__ + +/* 32-bit register definition */ +#define URXD0 (0x00) /* Receiver Register */ +#define URTX0 (0x40) /* Transmitter Register */ +#define UCR1 (0x80) /* Control Register 1 */ +#define UCR2 (0x84) /* Control Register 2 */ +#define UCR3 (0x88) /* Control Register 3 */ +#define UCR4 (0x8c) /* Control Register 4 */ +#define UFCR (0x90) /* FIFO Control Register */ +#define USR1 (0x94) /* Status Register 1 */ +#define USR2 (0x98) /* Status Register 2 */ +#define IMX21_UTS (0xb4) /* Test Register */ + +#define URXD_ERR BIT(14, UL) /* Error detect */ +#define URXD_RX_DATA GENMASK(7, 0) /* Received data mask */ + +#define UCR1_TRDYEN BIT(13, UL) /* Transmitter ready interrupt enable= */ +#define UCR1_RRDYEN BIT(9, UL) /* Receiver ready interrupt enable */ +#define UCR1_RXDMAEN BIT(8, UL) /* Receiver ready DMA enable */ +#define UCR1_TXMPTYEN BIT(6, UL) /* Transmitter empty interrupt enable = */ +#define UCR1_RTSDEN BIT(5, UL) /* RTS delta interrupt enable */ +#define UCR1_TXDMAEN BIT(3, UL) /* Transmitter ready DMA enable */ +#define UCR1_ATDMAEN BIT(2, UL) /* Aging DMA Timer enable */ +#define UCR1_UARTEN BIT(0, UL) /* UART enable */ + +#define UCR2_ATEN BIT(3, UL) /* Aging Timer Enable */ +#define UCR2_TXEN BIT(2, UL) /* Transmitter enable */ +#define UCR2_RXEN BIT(1, UL) /* Receiver enable */ + +#define UCR4_TCEN BIT(3, UL) /* Transmit complete interrupt enable */ +#define UCR4_DREN BIT(0, UL) /* Receive data ready interrupt enable */ + +#define UFCR_TXTL_SHF (10) /* Transmitter trigger level shift */ +#define UFCR_RFDIV GENMASK(9, 7) /* Reference frequency divider mask= */ +#define UFCR_DCEDTE BIT(6, UL) /* DCE/DTE mode select */ + +#define USR1_PARITYERR BIT(15, UL) /* Parity error interrupt flag */ +#define USR1_TRDY BIT(13, UL) /* Transmitter ready interrupt/DMA f= lag */ +#define USR1_FRAMERR BIT(10, UL) /* Frame error interrupt flag */ +#define USR1_RRDY BIT(9, UL) /* Receiver ready interrupt/DMA flag = */ +#define USR1_AGTIM BIT(8, UL) /* Aging timer interrupt flag */ + +#define USR2_TXDC BIT(3, UL) /* Transmitter complete */ +#define USR2_BRCD BIT(2, UL) /* Break condition detected */ +#define USR2_ORE BIT(1, UL) /* Overrun error */ +#define USR2_RDR BIT(0, UL) /* Receive data ready */ + +#define UTS_TXEMPTY BIT(6, UL) /* TxFIFO empty */ +#define UTS_TXFULL BIT(4, UL) /* TxFIFO full */ + +#define TXTL_DEFAULT (2) +#define RXTL_DEFAULT (8) + +#define TX_FIFO_SIZE 32 + +#endif /* __ASM_ARM_IMX_UART_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * 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([91.123.150.27]) by smtp.gmail.com with ESMTPSA id o10-20020a170906774a00b00a4e472a8e54sm4303773ejn.48.2024.04.02.05.06.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 05:06:28 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7066c174-f0e9-11ee-a1ef-f123f15fe8a2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1712059589; x=1712664389; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FUGgsrjKPl/22WR8VSn54cLHJfWkay8frEJz8oEQvJ0=; b=hBFiUnfkWMNU21vk9PQpTqD4w9/3sw/q98H+5k6j3bT14vfX/kQpcliNTUi62mZMyC G+e+KSPLfsCqOSU+X31IDNeBTwcVbPDOl2x6z5HroAsg0W/tfJjbkyCi9BHPKsV3glJx tyPvPJpdp7G5+nhJ9QlV+AlRmni77aYBanSr9W5Q5OkIcCscKUzchV0VeIdd1YkznlCx z3XAXrRKLFCDMjSn1EbynVKjfb9IvTWUJzdWvC/qX72grFZICN6CO74qDu3AjxUynA3O eSQOIureh+REihf62Al2XnR2WYyYYE+A7ShNguTjMD96ljiQCtl1zF7Wy+WLik9rELMw yS/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712059589; x=1712664389; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FUGgsrjKPl/22WR8VSn54cLHJfWkay8frEJz8oEQvJ0=; b=JuCaGXLlV21WnPBDLW+9KZdUiBYNQ6Y1efl8sOPnhHb65O/RTfX9s0N1/K8K8whDlG +7K9NK0WXN6kl5vKrmTD2bdoimiUfVIIENZ5vEv5yloYPI10wUxF8zvfAThwiSZLT5P9 dfjbO64KJZEf2QmOXEBmvZEiWGXwNOy+iLf/rNrh1H1Sk5aAht4bV9SUDvKTtso5OXRV FyPfislSQ3KdBtOx7vsaEDwp04sY+szVnlqHC6Yyy+0SgcGeLLnACnkhE/TknfbJu400 9giGgNZY8J+8sBbtCLgRf7y+BVrSw6d3LcT/at++vF4zjA6Vpsn6zqsCIy30gE8Ca6bu KXbw== X-Gm-Message-State: AOJu0YyMzl40/OfmDNJXaZ3PflpWX977fHE6C3o+c5Swbimgjoh8z/c2 Yb+BwsP+dCqRNSG27Sqey19vNbciieJ1+uN3LYZOU6oGw5czBuGwiUDWiLJJ X-Google-Smtp-Source: AGHT+IEe151L0J+G7gezYuP2Ey74bXQU7Msp/+iN5C48PhOX/MgTtpNc19hVo4PzgFkP5hhgLTqruw== X-Received: by 2002:a17:906:38c3:b0:a46:36ee:cfac with SMTP id r3-20020a17090638c300b00a4636eecfacmr8327286ejd.77.1712059588641; Tue, 02 Apr 2024 05:06:28 -0700 (PDT) From: Oleksandr Tyshchenko To: xen-devel@lists.xenproject.org Cc: Oleksandr Tyshchenko , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Peng Fan Subject: [PATCH 2/2] xen/arm: Add i.MX UART driver Date: Tue, 2 Apr 2024 15:05:57 +0300 Message-Id: <20240402120557.1822253-3-olekstysh@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240402120557.1822253-1-olekstysh@gmail.com> References: <20240402120557.1822253-1-olekstysh@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1712059609457100001 Content-Type: text/plain; charset="utf-8" From: Oleksandr Tyshchenko The i.MX UART Documentation: https://www.nxp.com/webapp/Download?colCode=3DIMX8MMRM Chapter 16.2 Universal Asynchronous Receiver/Transmitter (UART) Tested on i.MX 8M Mini only, but I guess, it should be suitable for other i.MX8M* SoCs (those UART device tree nodes contain "fsl,imx6q-uart" compatible string). Signed-off-by: Oleksandr Tyshchenko --- I used the "earlycon=3Dec_imx6q,0x30890000" cmd arg and selected CONFIG_SERIAL_IMX_EARLYCON in Linux for enabling vUART. --- --- MAINTAINERS | 1 + xen/drivers/char/Kconfig | 7 + xen/drivers/char/Makefile | 1 + xen/drivers/char/imx-uart.c | 299 ++++++++++++++++++++++++++++++++++++ 4 files changed, 308 insertions(+) create mode 100644 xen/drivers/char/imx-uart.c diff --git a/MAINTAINERS b/MAINTAINERS index 1bd22fd75f..bd4084fd20 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -249,6 +249,7 @@ F: xen/drivers/char/arm-uart.c F: xen/drivers/char/cadence-uart.c F: xen/drivers/char/exynos4210-uart.c F: xen/drivers/char/imx-lpuart.c +F: xen/drivers/char/imx-uart.c F: xen/drivers/char/meson-uart.c F: xen/drivers/char/mvebu-uart.c F: xen/drivers/char/omap-uart.c diff --git a/xen/drivers/char/Kconfig b/xen/drivers/char/Kconfig index e18ec3788c..f51a1f596a 100644 --- a/xen/drivers/char/Kconfig +++ b/xen/drivers/char/Kconfig @@ -20,6 +20,13 @@ config HAS_IMX_LPUART help This selects the i.MX LPUART. If you have i.MX8QM based board, say Y. =20 +config HAS_IMX_UART + bool "i.MX UART driver" + default y + depends on ARM_64 + help + This selects the i.MX UART. If you have i.MX8M* based board, say Y. + config HAS_MVEBU bool "Marvell MVEBU UART driver" default y diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile index e7e374775d..147530a1ed 100644 --- a/xen/drivers/char/Makefile +++ b/xen/drivers/char/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_HAS_SCIF) +=3D scif-uart.o obj-$(CONFIG_HAS_EHCI) +=3D ehci-dbgp.o obj-$(CONFIG_XHCI) +=3D xhci-dbc.o obj-$(CONFIG_HAS_IMX_LPUART) +=3D imx-lpuart.o +obj-$(CONFIG_HAS_IMX_UART) +=3D imx-uart.o obj-$(CONFIG_ARM) +=3D arm-uart.o obj-y +=3D serial.o obj-$(CONFIG_XEN_GUEST) +=3D xen_pv_console.o diff --git a/xen/drivers/char/imx-uart.c b/xen/drivers/char/imx-uart.c new file mode 100644 index 0000000000..13bb189063 --- /dev/null +++ b/xen/drivers/char/imx-uart.c @@ -0,0 +1,299 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * xen/drivers/char/imx-uart.c + * + * Driver for i.MX UART. + * + * Based on Linux's drivers/tty/serial/imx.c + * + * Copyright (C) 2024 EPAM Systems Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define imx_uart_read(uart, off) readl((uart)->regs + (off)) +#define imx_uart_write(uart, off, val) writel((val), (uart)->regs + (of= f)) + +static struct imx_uart { + uint32_t baud, clock_hz, data_bits, parity, stop_bits, fifo_size; + uint32_t irq; + char __iomem *regs; + struct irqaction irqaction; + struct vuart_info vuart; +} imx_com; + +static void imx_uart_interrupt(int irq, void *data) +{ + struct serial_port *port =3D data; + struct imx_uart *uart =3D port->uart; + uint32_t usr1, usr2; + + usr1 =3D imx_uart_read(uart, USR1); + usr2 =3D imx_uart_read(uart, USR2); + + if ( usr1 & (USR1_RRDY | USR1_AGTIM) ) + { + imx_uart_write(uart, USR1, USR1_AGTIM); + serial_rx_interrupt(port); + } + + if ( (usr1 & USR1_TRDY) || (usr2 & USR2_TXDC) ) + serial_tx_interrupt(port); +} + +static void imx_uart_clear_rx_errors(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + uint32_t usr1, usr2; + + usr1 =3D imx_uart_read(uart, USR1); + usr2 =3D imx_uart_read(uart, USR2); + + if ( usr2 & USR2_BRCD ) + imx_uart_write(uart, USR2, USR2_BRCD); + else if ( usr1 & USR1_FRAMERR ) + imx_uart_write(uart, USR1, USR1_FRAMERR); + else if ( usr1 & USR1_PARITYERR ) + imx_uart_write(uart, USR1, USR1_PARITYERR); + + if ( usr2 & USR2_ORE ) + imx_uart_write(uart, USR2, USR2_ORE); +} + +static void __init imx_uart_init_preirq(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + uint32_t reg; + + /* + * Wait for the transmission to complete. This is needed for a smooth + * transition when we come from early printk. + */ + while ( !(imx_uart_read(uart, USR2) & USR2_TXDC) ) + cpu_relax(); + + /* Set receiver/transmitter trigger level */ + reg =3D imx_uart_read(uart, UFCR); + reg &=3D (UFCR_RFDIV | UFCR_DCEDTE); + reg |=3D TXTL_DEFAULT << UFCR_TXTL_SHF | RXTL_DEFAULT; + imx_uart_write(uart, UFCR, reg); + + /* Enable UART and disable interrupts/DMA */ + reg =3D imx_uart_read(uart, UCR1); + reg |=3D UCR1_UARTEN; + reg &=3D ~(UCR1_TRDYEN | UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN | + UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); + imx_uart_write(uart, UCR1, reg); + + /* Enable receiver/transmitter and disable Aging Timer */ + reg =3D imx_uart_read(uart, UCR2); + reg |=3D UCR2_RXEN | UCR2_TXEN; + reg &=3D ~UCR2_ATEN; + imx_uart_write(uart, UCR2, reg); + + /* Disable interrupts */ + reg =3D imx_uart_read(uart, UCR4); + reg &=3D ~(UCR4_TCEN | UCR4_DREN); + imx_uart_write(uart, UCR4, reg); +} + +static void __init imx_uart_init_postirq(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + + uart->irqaction.handler =3D imx_uart_interrupt; + uart->irqaction.name =3D "imx_uart"; + uart->irqaction.dev_id =3D port; + + if ( setup_irq(uart->irq, 0, &uart->irqaction) !=3D 0 ) + { + dprintk(XENLOG_ERR, "Failed to allocate imx_uart IRQ %d\n", uart->= irq); + return; + } + + /* Clear possible receiver errors */ + imx_uart_clear_rx_errors(port); + + /* Enable interrupts */ + imx_uart_write(uart, UCR1, imx_uart_read(uart, UCR1) | + UCR1_RRDYEN | UCR1_TRDYEN); + imx_uart_write(uart, UCR2, imx_uart_read(uart, UCR2) | UCR2_ATEN); +} + +static void imx_uart_suspend(struct serial_port *port) +{ + BUG(); +} + +static void imx_uart_resume(struct serial_port *port) +{ + BUG(); +} + +static int imx_uart_tx_ready(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + uint32_t reg; + + reg =3D imx_uart_read(uart, IMX21_UTS); + if ( reg & UTS_TXEMPTY ) + return TX_FIFO_SIZE; + if ( reg & UTS_TXFULL ) + return 0; + + /* + * If the FIFO is neither full nor empty then there is a space for + * one char at least. + */ + return 1; +} + +static void imx_uart_putc(struct serial_port *port, char c) +{ + struct imx_uart *uart =3D port->uart; + + while ( imx_uart_read(uart, IMX21_UTS) & UTS_TXFULL ) + cpu_relax(); + + imx_uart_write(uart, URTX0, c); +} + +static int imx_uart_getc(struct serial_port *port, char *pc) +{ + struct imx_uart *uart =3D port->uart; + uint32_t data; + + if ( !(imx_uart_read(uart, USR2) & USR2_RDR) ) + return 0; + + data =3D imx_uart_read(uart, URXD0); + *pc =3D data & URXD_RX_DATA; + + if ( unlikely(data & URXD_ERR) ) + imx_uart_clear_rx_errors(port); + + return 1; +} + +static int __init imx_uart_irq(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + + return ((uart->irq > 0) ? uart->irq : -1); +} + +static const struct vuart_info *imx_uart_vuart_info(struct serial_port *po= rt) +{ + struct imx_uart *uart =3D port->uart; + + return &uart->vuart; +} + +static void imx_uart_start_tx(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + + imx_uart_write(uart, UCR1, imx_uart_read(uart, UCR1) | UCR1_TRDYEN); +} + +static void imx_uart_stop_tx(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + + imx_uart_write(uart, UCR1, imx_uart_read(uart, UCR1) & ~UCR1_TRDYEN); +} + +static struct uart_driver __read_mostly imx_uart_driver =3D { + .init_preirq =3D imx_uart_init_preirq, + .init_postirq =3D imx_uart_init_postirq, + .endboot =3D NULL, + .suspend =3D imx_uart_suspend, + .resume =3D imx_uart_resume, + .tx_ready =3D imx_uart_tx_ready, + .putc =3D imx_uart_putc, + .getc =3D imx_uart_getc, + .irq =3D imx_uart_irq, + .start_tx =3D imx_uart_start_tx, + .stop_tx =3D imx_uart_stop_tx, + .vuart_info =3D imx_uart_vuart_info, +}; + +static int __init imx_uart_init(struct dt_device_node *dev, const void *da= ta) +{ + const char *config =3D data; + struct imx_uart *uart; + int res; + paddr_t addr, size; + + if ( strcmp(config, "") ) + printk("WARNING: UART configuration is not supported\n"); + + uart =3D &imx_com; + + uart->baud =3D 115200; + uart->data_bits =3D 8; + uart->parity =3D 0; + uart->stop_bits =3D 1; + + res =3D dt_device_get_paddr(dev, 0, &addr, &size); + if ( res ) + { + printk("imx-uart: Unable to retrieve the base address of the UART\= n"); + return res; + } + + res =3D platform_get_irq(dev, 0); + if ( res < 0 ) + { + printk("imx-uart: Unable to retrieve the IRQ\n"); + return -EINVAL; + } + uart->irq =3D res; + + uart->regs =3D ioremap_nocache(addr, size); + if ( !uart->regs ) + { + printk("imx-uart: Unable to map the UART memory\n"); + return -ENOMEM; + } + + uart->vuart.base_addr =3D addr; + uart->vuart.size =3D size; + uart->vuart.data_off =3D URTX0; + uart->vuart.status_off =3D IMX21_UTS; + uart->vuart.status =3D UTS_TXEMPTY; + + /* Register with generic serial driver */ + serial_register_uart(SERHND_DTUART, &imx_uart_driver, uart); + + dt_device_set_used_by(dev, DOMID_XEN); + + return 0; +} + +static const struct dt_device_match imx_uart_dt_compat[] __initconst =3D +{ + DT_MATCH_COMPATIBLE("fsl,imx6q-uart"), + { /* sentinel */ }, +}; + +DT_DEVICE_START(imx_uart, "i.MX UART", DEVICE_SERIAL) + .dt_match =3D imx_uart_dt_compat, + .init =3D imx_uart_init, +DT_DEVICE_END + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.34.1