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b=cAKHpjakJmApsYxCI+yyPhbPMVLm3aQ9yA09tIeBbsqHfJ+aqiFEdfQaYWZ4PsfHOo3xDnP1kzq6c6dZjA00FYoGbCaGfro9UwkDyIxiApsGUC7ZqHyYcadqb6/4WwYbbFtqSyNJf1BeEWDr0WcEYu8hdlXt0LcRsMQ0CYpgjxpKdb2KYYKviR7/q1IzzTSUGo3YlHaHhR1IrliT9OAeB+nzM7AAsxs33iabz0Z+MICd5qQPmeafEtAqyRtQS471qPRnWkRyPNrsyrVCthDbF6s3ZFhRKyNwKq/EwBPVDvr22OudiYG/BapjOQ0Q16VfCvxwnrCLqna1vwU5pq0Nkw== From: Volodymyr Babchuk To: "xen-devel@lists.xenproject.org" CC: Volodymyr Babchuk , Julien Grall , Rahul Singh , Stefano Stabellini , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH 1/3] arm: smmu: allow SMMU to have more IRQs than context banks Thread-Topic: [PATCH 1/3] arm: smmu: allow SMMU to have more IRQs than context banks Thread-Index: AQHagW1LqEDvA9goAU2CqI9xrHsnFw== Date: Fri, 29 Mar 2024 00:08:57 +0000 Message-ID: <20240329000822.3363568-2-volodymyr_babchuk@epam.com> References: <20240329000822.3363568-1-volodymyr_babchuk@epam.com> In-Reply-To: <20240329000822.3363568-1-volodymyr_babchuk@epam.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.43.0 x-ms-publictraffictype: Email x-ms-traffictypediagnostic: GV1PR03MB10456:EE_|DBBPR03MB10269:EE_ x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="utf-8" I encountered platform, namely Qualcomm SA8155P where SMMU-compatible IO-MMU advertises more context IQRs than there are context banks. This should not be an issue, we need to relax the check in the SMMU driver to allow such configuration. Signed-off-by: Volodymyr Babchuk --- xen/drivers/passthrough/arm/smmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/a= rm/smmu.c index 32e2ff279b..2dd3688f3b 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -2550,7 +2550,7 @@ static int arm_smmu_device_dt_probe(struct platform_d= evice *pdev) parse_driver_options(smmu); =20 if (smmu->version > ARM_SMMU_V1 && - smmu->num_context_banks !=3D smmu->num_context_irqs) { + smmu->num_context_banks > smmu->num_context_irqs) { dev_err(dev, "found only %d context interrupt(s) but %d required\n", smmu->num_context_irqs, smmu->num_context_banks); --=20 2.43.0 From nobody Wed May 22 00:54:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; 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Fri, 29 Mar 2024 00:09:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 935585d9-ed60-11ee-a1ef-f123f15fe8a2 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Np3SQsj2d+/ruyrD/CKSIbQIhqW9cd72UNQGcwY4efPfCB+fVfVumXDEEfDfsmiNKQ+cDGbD6sKXKcu54KVtgM0DRzOp+AVgeajsQ1tQYxFeOosPGYetjMnvKtr+9usm0eVAoGHkAW1ul+rbM9TXXKRj1XqxGCTqqPTRt8hAyetLjpIn7qAx9XgcdEyQeDwsbRflAZSuv7+Z+Wv5lWrC8XyGvUSYMSl+i81O32ob+CvsS1wWiNBJ1IrkeTn1migLVf7hbofbdYX8aDa+54eeRfmoxUPTU9Kcag0Uds9rUbS1POY/ZOC4xjthAnWqe31t1XASTV0uMN8KymJcrWys3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; 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charset="utf-8" Generic Interface (GENI) is a newer interface for low speed interfaces like UART, I2C or SPI. This patch adds the simple driver for the UART instance of GENI. Code is based on similar drivers in U-Boot and Linux kernel. This driver implements only simple synchronous mode, because although GENI supports FIFO mode, it needs to know number of characters **before** starting TX transaction. This is a stark contrast when compared to other UART peripherals, which allow adding characters to a FIFO while TX operation is running. The patch adds both normal UART driver and earlyprintk version. Signed-off-by: Volodymyr Babchuk --- xen/arch/arm/Kconfig.debug | 19 +- xen/arch/arm/arm64/debug-qcom.inc | 76 +++++++ xen/arch/arm/include/asm/qcom-uart.h | 48 +++++ xen/drivers/char/Kconfig | 8 + xen/drivers/char/Makefile | 1 + xen/drivers/char/qcom-uart.c | 288 +++++++++++++++++++++++++++ 6 files changed, 439 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/arm64/debug-qcom.inc create mode 100644 xen/arch/arm/include/asm/qcom-uart.h create mode 100644 xen/drivers/char/qcom-uart.c diff --git a/xen/arch/arm/Kconfig.debug b/xen/arch/arm/Kconfig.debug index eec860e88e..f6ab0bb30e 100644 --- a/xen/arch/arm/Kconfig.debug +++ b/xen/arch/arm/Kconfig.debug @@ -119,6 +119,19 @@ choice selecting one of the platform specific options below if you know the parameters for the port. =20 + This option is preferred over the platform specific + options; the platform specific options are deprecated + and will soon be removed. + config EARLY_UART_CHOICE_QCOM + select EARLY_UART_QCOM + bool "Early printk via Qualcomm debug UART" + help + Say Y here if you wish the early printk to direct their + output to a Qualcomm debug UART. You can use this option to + provide the parameters for the debug UART rather than + selecting one of the platform specific options below if + you know the parameters for the port. + This option is preferred over the platform specific options; the platform specific options are deprecated and will soon be removed. @@ -211,6 +224,9 @@ config EARLY_UART_PL011 config EARLY_UART_SCIF select EARLY_PRINTK bool +config EARLY_UART_QCOM + select EARLY_PRINTK + bool =20 config EARLY_PRINTK bool @@ -261,7 +277,7 @@ config EARLY_UART_PL011_MMIO32 will be done using 32-bit only accessors. =20 config EARLY_UART_INIT - depends on EARLY_UART_PL011 && EARLY_UART_PL011_BAUD_RATE !=3D 0 + depends on (EARLY_UART_PL011 && EARLY_UART_PL011_BAUD_RATE !=3D 0) || EAR= LY_UART_QCOM def_bool y =20 config EARLY_UART_8250_REG_SHIFT @@ -308,3 +324,4 @@ config EARLY_PRINTK_INC default "debug-mvebu.inc" if EARLY_UART_MVEBU default "debug-pl011.inc" if EARLY_UART_PL011 default "debug-scif.inc" if EARLY_UART_SCIF + default "debug-qcom.inc" if EARLY_UART_QCOM diff --git a/xen/arch/arm/arm64/debug-qcom.inc b/xen/arch/arm/arm64/debug-q= com.inc new file mode 100644 index 0000000000..130d08d6e9 --- /dev/null +++ b/xen/arch/arm/arm64/debug-qcom.inc @@ -0,0 +1,76 @@ +/* + * xen/arch/arm/arm64/debug-qcom.inc + * + * Qualcomm debug UART specific debug code + * + * Volodymyr Babchuk + * Copyright (C) 2024, EPAM Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +.macro early_uart_init xb c + mov w\c, #M_GENI_CMD_ABORT + str w\c, [\xb, #SE_GENI_M_CMD_CTRL_REG] +1: + ldr w\c, [\xb, #SE_GENI_M_IRQ_STATUS] /* Load IRQ status */ + tst w\c, #M_CMD_ABORT_EN /* Check TX_FIFI_WATERMARK_EN b= it */ + beq 1b /* Wait for the UART to be ready= */ + mov w\c, #M_CMD_ABORT_EN + orr w\c, w\c, #M_CMD_DONE_EN + str w\c, [\xb, #SE_GENI_M_IRQ_CLEAR] + + mov w\c, #1 + str w\c, [\xb, #SE_UART_TX_TRANS_LEN] /* write len */ + + mov w\c, #(UART_START_TX << M_OPCODE_SHFT) /* Prepare cmd */ + str w\c, [\xb, #SE_GENI_M_CMD0] /* write cmd */ +.endm +/* + * wait for UART to be ready to transmit + * xb: register which contains the UART base address + * c: scratch register + */ +.macro early_uart_ready xb c +1: + ldr w\c, [\xb, #SE_GENI_M_IRQ_STATUS] /* Load IRQ status */ + tst w\c, #M_TX_FIFO_WATERMARK_EN /* Check TX_FIFI_WATERMARK_EN = bit */ + beq 1b /* Wait for the UART to be rea= dy */ +.endm + +/* + * UART transmit character + * xb: register which contains the UART base address + * wt: register which contains the character to transmit + */ +.macro early_uart_transmit xb wt + str \wt, [\xb, #SE_GENI_TX_FIFOn] /* Put char to FIF= O */ + mov \wt, #M_TX_FIFO_WATERMARK_EN /* Prepare to FIFO= */ + str \wt, [\xb, #SE_GENI_M_IRQ_CLEAR] /* Kick FIFO */ +95: + ldr \wt, [\xb, #SE_GENI_M_IRQ_STATUS] /* Load IRQ status= */ + tst \wt, #M_CMD_DONE_EN /* Check TX_FIFO_WATERMARK_EN = bit */ + beq 95b /* Wait for the UART to be rea= dy */ + mov \wt, #M_CMD_DONE_EN + str \wt, [\xb, #SE_GENI_M_IRQ_CLEAR] + + mov \wt, #(UART_START_TX << M_OPCODE_SHFT) /* Prepare next cm= d */ + str \wt, [\xb, #SE_GENI_M_CMD0] /* write cmd */ +.endm + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/qcom-uart.h b/xen/arch/arm/include/as= m/qcom-uart.h new file mode 100644 index 0000000000..dc9579374c --- /dev/null +++ b/xen/arch/arm/include/asm/qcom-uart.h @@ -0,0 +1,48 @@ +/* + * xen/include/asm-arm/qcom-uart.h + * + * Common constant definition between early printk and the UART driver + * for the Qualcomm debug UART + * + * Volodymyr Babchuk + * Copyright (C) 2024, EPAM Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARM_QCOM_UART_H +#define __ASM_ARM_QCOM_UART_H + +#define SE_UART_TX_TRANS_LEN 0x270 +#define SE_GENI_M_CMD0 0x600 +#define UART_START_TX 0x1 +#define M_OPCODE_SHFT 27 + +#define SE_GENI_M_CMD_CTRL_REG 0x604 +#define M_GENI_CMD_ABORT BIT(1, U) +#define SE_GENI_M_IRQ_STATUS 0x610 +#define M_CMD_DONE_EN BIT(0, U) +#define M_CMD_ABORT_EN BIT(5, U) +#define M_TX_FIFO_WATERMARK_EN BIT(30, U) +#define SE_GENI_M_IRQ_CLEAR 0x618 +#define SE_GENI_TX_FIFOn 0x700 +#define SE_GENI_TX_WATERMARK_REG 0x80c + +#endif /* __ASM_ARM_QCOM_UART_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/drivers/char/Kconfig b/xen/drivers/char/Kconfig index e18ec3788c..52c3934d06 100644 --- a/xen/drivers/char/Kconfig +++ b/xen/drivers/char/Kconfig @@ -68,6 +68,14 @@ config HAS_SCIF This selects the SuperH SCI(F) UART. If you have a SuperH based board, or Renesas R-Car Gen 2/3 based board say Y. =20 +config HAS_QCOM_UART + bool "Qualcomm GENI UART driver" + default y + depends on ARM + help + This selects the Qualcomm GENI-based UART driver. If you + have a Qualcomm-based board board say Y here. + config HAS_EHCI bool depends on X86 diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile index e7e374775d..698ad0578c 100644 --- a/xen/drivers/char/Makefile +++ b/xen/drivers/char/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_HAS_MESON) +=3D meson-uart.o obj-$(CONFIG_HAS_MVEBU) +=3D mvebu-uart.o obj-$(CONFIG_HAS_OMAP) +=3D omap-uart.o obj-$(CONFIG_HAS_SCIF) +=3D scif-uart.o +obj-$(CONFIG_HAS_QCOM_UART) +=3D qcom-uart.o obj-$(CONFIG_HAS_EHCI) +=3D ehci-dbgp.o obj-$(CONFIG_XHCI) +=3D xhci-dbc.o obj-$(CONFIG_HAS_IMX_LPUART) +=3D imx-lpuart.o diff --git a/xen/drivers/char/qcom-uart.c b/xen/drivers/char/qcom-uart.c new file mode 100644 index 0000000000..2614051ca0 --- /dev/null +++ b/xen/drivers/char/qcom-uart.c @@ -0,0 +1,288 @@ +/* + * xen/drivers/char/qcom-uart.c + * + * Driver for Qualcomm GENI-based UART interface + * + * Volodymyr Babchuk + * + * Copyright (C) EPAM Systems 2024 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GENI_FORCE_DEFAULT_REG 0x20 +#define FORCE_DEFAULT BIT(0, U) +#define DEF_TX_WM 2 +#define SE_GENI_TX_PACKING_CFG0 0x260 +#define SE_GENI_TX_PACKING_CFG1 0x264 +#define SE_GENI_RX_PACKING_CFG0 0x284 +#define SE_GENI_RX_PACKING_CFG1 0x288 +#define SE_GENI_M_IRQ_EN 0x614 +#define M_SEC_IRQ_EN BIT(31, U) +#define M_RX_FIFO_WATERMARK_EN BIT(26, U) +#define M_RX_FIFO_LAST_EN BIT(27, U) +#define SE_GENI_S_CMD0 0x630 +#define UART_START_READ 0x1 +#define S_OPCODE_SHFT 27 +#define SE_GENI_S_CMD_CTRL_REG 0x634 +#define S_GENI_CMD_ABORT BIT(1, U) +#define SE_GENI_S_IRQ_STATUS 0x640 +#define SE_GENI_S_IRQ_EN 0x644 +#define S_RX_FIFO_LAST_EN BIT(27, U) +#define S_RX_FIFO_WATERMARK_EN BIT(26, U) +#define S_CMD_ABORT_EN BIT(5, U) +#define S_CMD_DONE_EN BIT(0, U) +#define SE_GENI_S_IRQ_CLEAR 0x648 +#define SE_GENI_RX_FIFOn 0x780 +#define SE_GENI_TX_FIFO_STATUS 0x800 +#define TX_FIFO_WC GENMASK(27, 0) +#define SE_GENI_RX_FIFO_STATUS 0x804 +#define RX_LAST BIT(31, U) +#define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28) +#define RX_LAST_BYTE_VALID_SHFT 28 +#define RX_FIFO_WC_MSK GENMASK(24, 0) +#define SE_GENI_TX_WATERMARK_REG 0x80c + +static struct qcom_uart { + unsigned int irq; + char __iomem *regs; + struct irqaction irqaction; +} qcom_com =3D {0}; + +static bool qcom_uart_poll_bit(void *addr, uint32_t mask, bool set) +{ + unsigned long timeout_us =3D 20000; + uint32_t reg; + + while ( timeout_us ) { + reg =3D readl(addr); + if ( (bool)(reg & mask) =3D=3D set ) + return true; + udelay(10); + timeout_us -=3D 10; + } + + return false; +} + +static void __init qcom_uart_init_preirq(struct serial_port *port) +{ + struct qcom_uart *uart =3D port->uart; + + /* Stop anything in TX that earlyprintk configured and clear all error= s */ + writel(M_GENI_CMD_ABORT, uart->regs + SE_GENI_M_CMD_CTRL_REG); + qcom_uart_poll_bit(uart->regs + SE_GENI_M_IRQ_STATUS, M_CMD_ABORT_EN, + true); + writel(M_CMD_ABORT_EN, uart->regs + SE_GENI_M_IRQ_CLEAR); + + /* + * Configure FIFO length: 1 byte per FIFO entry. This is terribly + * ineffective, as it is possible to cram 4 bytes per FIFO word, + * like Linux does. But using one byte per FIFO entry makes this + * driver much simpler. + */ + writel(0xf, uart->regs + SE_GENI_TX_PACKING_CFG0); + writel(0x0, uart->regs + SE_GENI_TX_PACKING_CFG1); + writel(0xf, uart->regs + SE_GENI_RX_PACKING_CFG0); + writel(0x0, uart->regs + SE_GENI_RX_PACKING_CFG1); + + /* Reset RX state machine */ + writel(S_GENI_CMD_ABORT, uart->regs + SE_GENI_S_CMD_CTRL_REG); + qcom_uart_poll_bit(uart->regs + SE_GENI_S_CMD_CTRL_REG, + S_GENI_CMD_ABORT, false); + writel(S_CMD_DONE_EN | S_CMD_ABORT_EN, uart->regs + SE_GENI_S_IRQ_CLEA= R); + writel(FORCE_DEFAULT, uart->regs + GENI_FORCE_DEFAULT_REG); +} + +static void qcom_uart_interrupt(int irq, void *data, struct cpu_user_regs = *regs) +{ + struct serial_port *port =3D data; + struct qcom_uart *uart =3D port->uart; + uint32_t m_irq_status, s_irq_status; + + m_irq_status =3D readl(uart->regs + SE_GENI_M_IRQ_STATUS); + s_irq_status =3D readl(uart->regs + SE_GENI_S_IRQ_STATUS); + writel(m_irq_status, uart->regs + SE_GENI_M_IRQ_CLEAR); + writel(s_irq_status, uart->regs + SE_GENI_S_IRQ_CLEAR); + + if ( s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN) ) + serial_rx_interrupt(port, regs); +} + +static void __init qcom_uart_init_postirq(struct serial_port *port) +{ + struct qcom_uart *uart =3D port->uart; + int rc; + uint32_t val; + + uart->irqaction.handler =3D qcom_uart_interrupt; + uart->irqaction.name =3D "qcom_uart"; + uart->irqaction.dev_id =3D port; + + if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) + dprintk(XENLOG_ERR, "Failed to allocated qcom_uart IRQ %d\n", + uart->irq); + + /* Enable TX/RX and Error Interrupts */ + writel(S_GENI_CMD_ABORT, uart->regs + SE_GENI_S_CMD_CTRL_REG); + qcom_uart_poll_bit(uart->regs + SE_GENI_S_CMD_CTRL_REG, + S_GENI_CMD_ABORT, false); + writel(S_CMD_DONE_EN | S_CMD_ABORT_EN, uart->regs + SE_GENI_S_IRQ_CLEA= R); + writel(FORCE_DEFAULT, uart->regs + GENI_FORCE_DEFAULT_REG); + + val =3D readl(uart->regs + SE_GENI_S_IRQ_EN); + val =3D S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; + writel(val, uart->regs + SE_GENI_S_IRQ_EN); + + val =3D readl(uart->regs + SE_GENI_M_IRQ_EN); + val =3D M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; + writel(val, uart->regs + SE_GENI_M_IRQ_EN); + + /* Send RX command */ + writel(UART_START_READ << S_OPCODE_SHFT, uart->regs + SE_GENI_S_CMD0); + qcom_uart_poll_bit(uart->regs + SE_GENI_M_IRQ_STATUS, M_SEC_IRQ_EN, + true); +} + +static void qcom_uart_putc(struct serial_port *port, char c) +{ + struct qcom_uart *uart =3D port->uart; + uint32_t irq_clear =3D M_CMD_DONE_EN; + uint32_t m_cmd; + bool done; + + /* Setup TX */ + writel(1, uart->regs + SE_UART_TX_TRANS_LEN); + + writel(DEF_TX_WM, uart->regs + SE_GENI_TX_WATERMARK_REG); + + m_cmd =3D UART_START_TX << M_OPCODE_SHFT; + writel(m_cmd, uart->regs + SE_GENI_M_CMD0); + + qcom_uart_poll_bit(uart->regs + SE_GENI_M_IRQ_STATUS, + M_TX_FIFO_WATERMARK_EN, true); + + writel(c, uart->regs + SE_GENI_TX_FIFOn); + writel(M_TX_FIFO_WATERMARK_EN, uart->regs + SE_GENI_M_IRQ_CLEAR); + + /* Check for TX done */ + done =3D qcom_uart_poll_bit(uart->regs + SE_GENI_M_IRQ_STATUS, M_CMD_D= ONE_EN, + true); + if ( !done ) + { + writel(M_GENI_CMD_ABORT, uart->regs + SE_GENI_M_CMD_CTRL_REG); + irq_clear |=3D M_CMD_ABORT_EN; + qcom_uart_poll_bit(uart->regs + SE_GENI_M_IRQ_STATUS, M_CMD_ABORT_= EN, + true); + + } + writel(irq_clear, uart->regs + SE_GENI_M_IRQ_CLEAR); +} + +static int qcom_uart_getc(struct serial_port *port, char *pc) +{ + struct qcom_uart *uart =3D port->uart; + + if ( !readl(uart->regs + SE_GENI_RX_FIFO_STATUS) ) + return 0; + + *pc =3D readl(uart->regs + SE_GENI_RX_FIFOn) & 0xFF; + + writel(UART_START_READ << S_OPCODE_SHFT, uart->regs + SE_GENI_S_CMD0); + qcom_uart_poll_bit(uart->regs + SE_GENI_M_IRQ_STATUS, M_SEC_IRQ_EN, + true); + + return 1; + +} + +static struct uart_driver __read_mostly qcom_uart_driver =3D { + .init_preirq =3D qcom_uart_init_preirq, + .init_postirq =3D qcom_uart_init_postirq, + .putc =3D qcom_uart_putc, + .getc =3D qcom_uart_getc, +}; + +static const struct dt_device_match qcom_uart_dt_match[] __initconst =3D +{ + { .compatible =3D "qcom,geni-debug-uart"}, + { /* sentinel */ }, +}; + +static int __init qcom_uart_init(struct dt_device_node *dev, + const void *data) +{ + const char *config =3D data; + struct qcom_uart *uart; + int res; + paddr_t addr, size; + + if ( strcmp(config, "") ) + printk("WARNING: UART configuration is not supported\n"); + + uart =3D &qcom_com; + + res =3D dt_device_get_paddr(dev, 0, &addr, &size); + if ( res ) + { + printk("qcom-uart: Unable to retrieve the base" + " address of the UART\n"); + return res; + } + + res =3D platform_get_irq(dev, 0); + if ( res < 0 ) + { + printk("qcom-uart: Unable to retrieve the IRQ\n"); + return res; + } + uart->irq =3D res; + + uart->regs =3D ioremap_nocache(addr, size); + if ( !uart->regs ) + { + printk("qcom-uart: Unable to map the UART memory\n"); + return -ENOMEM; + } + + /* Register with generic serial driver */ + serial_register_uart(SERHND_DTUART, &qcom_uart_driver, uart); + + dt_device_set_used_by(dev, DOMID_XEN); + + return 0; +} + +DT_DEVICE_START(qcom_uart, "QCOM UART", DEVICE_SERIAL) + .dt_match =3D qcom_uart_dt_match, + .init =3D qcom_uart_init, +DT_DEVICE_END + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.43.0 From nobody Wed May 22 00:54:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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b=kopJppY+vRvxMYGbii77qInqB6MqZA+gBrr8lXP4kFkyIKXuLXDj+bM7w9pd/GnYuHoaQUDAvZGstqiZEKFUKeBYNfEAaa+vaZcgEC9sXiCn7Qi98ro06Ohk0Mnp5stfsaYVNwASYDvaF7Iy9vf9YPBeD5PHv+o0ShzKjYB/gXzN6mmj+fO4/8KpSXXg+7JtjR7dwivnrdb33U0Ap2wU1tNp1Vj/gnhfWvuccY7GxLx4WvwEVJTGmDZU1m+hKTGShCQyYsBsp+VB8d7C33wkMfR7x8GvJD10yN0CogjYfDWmwi+fuZ/o21WC/y0W60ZBGjPdPmTDtZg6USF38JdFXg== From: Volodymyr Babchuk To: "xen-devel@lists.xenproject.org" CC: Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH 3/3] arm: platform: qcom: add basic support SA8155P SoC Thread-Topic: [PATCH 3/3] arm: platform: qcom: add basic support SA8155P SoC Thread-Index: AQHagW1LlGLM/ZuGTEiUoHPlQw1VXw== Date: Fri, 29 Mar 2024 00:08:57 +0000 Message-ID: <20240329000822.3363568-4-volodymyr_babchuk@epam.com> References: <20240329000822.3363568-1-volodymyr_babchuk@epam.com> In-Reply-To: <20240329000822.3363568-1-volodymyr_babchuk@epam.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.43.0 x-ms-publictraffictype: Email x-ms-traffictypediagnostic: GV1PR03MB10456:EE_|DBBPR03MB10269:EE_ x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="utf-8" Qualcomm SA8155P is the automotive variant of SM8150 aka Snapdragon 855. This patch adds very basic support for the platform. We need to handle Qualcomm-specific SMC to workaround quirk in the QCOM SCM driver in the Linux kernel. Basically the driver tries multiple different SMCs to determine which calling convention is supported by a SoC. If all calls fail it decides that the SoC uses "legacy SMC" and tries to communicate with SCM by issuing SMC with funcid =3D 1. Problem is that Xen has own understanding on how such SMC should be handled. It interprets this SMC as legacy PSCI_cpu_off and happily turns of Linux boot CPU. To workaround this, we pretend that we support QCOM_SCM_INFO_IS_CALL_AVAIL, this will make the driver use the latest calling convention. All subsequent calls will fail anyways and the driver will terminate self gracefully. This is not a big deal, because right now (with Linux 6.8) even on baremetal setup the driver fails anyways, because it does not know how to work with this SoC. Signed-off-by: Volodymyr Babchuk --- xen/arch/arm/platforms/Makefile | 1 + xen/arch/arm/platforms/qcom.c | 77 +++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+) create mode 100644 xen/arch/arm/platforms/qcom.c diff --git a/xen/arch/arm/platforms/Makefile b/xen/arch/arm/platforms/Makef= ile index 8632f4115f..6873735ef0 100644 --- a/xen/arch/arm/platforms/Makefile +++ b/xen/arch/arm/platforms/Makefile @@ -9,5 +9,6 @@ obj-$(CONFIG_ALL_PLAT) +=3D sunxi.o obj-$(CONFIG_ALL64_PLAT) +=3D thunderx.o obj-$(CONFIG_ALL64_PLAT) +=3D xgene-storm.o obj-$(CONFIG_ALL64_PLAT) +=3D brcm-raspberry-pi.o +obj-$(CONFIG_ALL64_PLAT) +=3D qcom.o obj-$(CONFIG_MPSOC_PLATFORM) +=3D xilinx-zynqmp.o obj-$(CONFIG_MPSOC_PLATFORM) +=3D xilinx-zynqmp-eemi.o diff --git a/xen/arch/arm/platforms/qcom.c b/xen/arch/arm/platforms/qcom.c new file mode 100644 index 0000000000..77e9c58649 --- /dev/null +++ b/xen/arch/arm/platforms/qcom.c @@ -0,0 +1,77 @@ +/* + * xen/arch/arm/platforms/qcom.c + * + * Qualcomm SoCs specific code + * + * Volodymyr Babchuk + * + * Copyright (c) 2024 EPAM Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF)) +#define QCOM_SCM_SVC_INFO 0x06 +#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01 + +#define ARM_SMCCC_SIP_QCOM_SCM_IS_CALL_AVAIL \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_64, \ + ARM_SMCCC_OWNER_SIP, \ + SCM_SMC_FNID(QCOM_SCM_SVC_INFO, \ + QCOM_SCM_INFO_IS_CALL_AVAIL)) + +static const char * const sa8155p_dt_compat[] __initconst =3D +{ + "qcom,sa8155p", + NULL +}; + +static bool sa8155p_smc(struct cpu_user_regs *regs) +{ + uint32_t funcid =3D get_user_reg(regs, 0); + + switch ( funcid ) { + case ARM_SMCCC_SIP_QCOM_SCM_IS_CALL_AVAIL: + /* + * We need to implement this specific call only to make Linux + * counterpart happy: QCOM SCM driver in Linux tries to + * determine calling convention by issuing this particular + * SMC. If it receives an error it assumes that platform uses + * legacy calling convention and tries to issue SMC with + * funcid =3D 1. Xen interprets this as PSCI_cpu_off and turns + * off Linux boot vCPU. + */ + set_user_reg(regs, 0, ARM_SMCCC_SUCCESS); + set_user_reg(regs, 1, 1); + return true; + default: + return false; + } +} + +PLATFORM_START(sa8155p, "Qualcomm SA8155P") + .compatible =3D sa8155p_dt_compat, + .smc =3D sa8155p_smc +PLATFORM_END + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.43.0