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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v6 3/3] xen/arm: arm32: Add emulation of Debug Data Transfer Registers Date: Thu, 7 Mar 2024 12:39:43 +0000 Message-ID: <20240307123943.1991755-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240307123943.1991755-1-ayan.kumar.halder@amd.com> References: <20240307123943.1991755-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEA:EE_|CY8PR12MB8195:EE_ X-MS-Office365-Filtering-Correlation-Id: 41aa4874-edf2-44d1-00a1-08dc3ea3c8fc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Mar 2024 12:40:35.1223 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41aa4874-edf2-44d1-00a1-08dc3ea3c8fc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8195 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1709815258090100003 Content-Type: text/plain; charset="utf-8" When user enables HVC_DCC config option in Linux, it invokes access to debug transfer register (i.e. DBGDTRTXINT). As this register is not emulated, Xen injects an undefined exception to the guest and Linux crashes. To prevent this crash, introduce a partial emulation of DBGDTR[TR]XINT (the= se registers share the same encoding) as RAZ/WI and DBGDSCRINT as TXfull. Refer ARM DDI 0487J.a ID042523, G8.3.19, DBGDTRTXint: "If TXfull is set to 1, set DTRTX to UNKNOWN". As a pre-requisite, DBGOSLSR should be emulated in the same way as its AArc= h64 variant (i.e. OSLSR_EL1). This is to ensure that DBGOSLSR.OSLK is 0, which allows us to skip the emulation of DBGDSCREXT (TXfull is treated as UNK/SBZ= P) and focus on DBGDSCRINT. DBGOSLSR.OSLM[1] is set to 1 to mantain consistency with Arm64. Take the opportunity to fix the minimum EL for DBGDSCRINT, which should be = 0. Signed-off-by: Ayan Kumar Halder Signed-off-by: Michal Orzel Acked-by: Julien Grall --- Changes from v1 :- 1. DBGDTR_EL0 does not emulate RXfull. This is to avoid giving the OS= any indication that the RX buffer is full and is waiting to be read. 2. In Arm32, DBGOSLSR is emulated. Also DBGDTRTXINT is emulated at EL0 only. 3. Fixed the commit message and inline code comments. v2 :- 1. Split the patch into two (separate patches for arm64 and arm32). 2. Fixed in line comments and style related issues. 3. Updated commit message to mention DBGDSCRINT handling. v3 :- 1. The original emulation of DBGDSCRINT is retained when 'partial_emulation' is false. 2. If 'partial_emulation' is false, then access to DBGDTRTXINT will lead to undefined exception. v4 :- 1. Invoked "goto fail" from "default:" to ensure compliance with MISRA 15.3. v5 :- 1. Reword the commit message 2. Remove the 'return' at the end of function. SUPPORT.md | 3 ++ xen/arch/arm/include/asm/cpregs.h | 2 + xen/arch/arm/vcpreg.c | 62 ++++++++++++++++++++++--------- 3 files changed, 49 insertions(+), 18 deletions(-) diff --git a/SUPPORT.md b/SUPPORT.md index afbd820084..e0ff30cfe9 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -115,6 +115,9 @@ Only the following system registers are security suppor= ted: DBGDTR_EL0 DBGDTRTX_EL0 DBGDTRRX_EL0 + DBGDSCRINT + DBGDTRTXINT + DBGDTRRXINT =20 ### ARM Scalable Vector Extension (SVE/SVE2) =20 diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/c= pregs.h index 6b083de204..aec9e8f329 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -75,6 +75,8 @@ #define DBGDIDR p14,0,c0,c0,0 /* Debug ID Register */ #define DBGDSCRINT p14,0,c0,c1,0 /* Debug Status and Control Intern= al */ #define DBGDSCREXT p14,0,c0,c2,2 /* Debug Status and Control Extern= al */ +#define DBGDTRRXINT p14,0,c0,c5,0 /* Debug Data Transfer Register, R= eceive */ +#define DBGDTRTXINT p14,0,c0,c5,0 /* Debug Data Transfer Register, T= ransmit */ #define DBGVCR p14,0,c0,c7,0 /* Vector Catch */ #define DBGBVR0 p14,0,c0,c0,4 /* Breakpoint Value 0 */ #define DBGBCR0 p14,0,c0,c0,5 /* Breakpoint Control 0 */ diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index a2d0500704..b203f4a142 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -493,11 +493,12 @@ void do_cp14_32(struct cpu_user_regs *regs, const uni= on hsr hsr) * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 * * Unhandled: - * DBGOSLSR * DBGPRCR */ case HSR_CPREG32(DBGOSLAR): return handle_wo_wi(regs, regidx, cp32.read, hsr, 1); + case HSR_CPREG32(DBGOSLSR): + return handle_ro_read_val(regs, regidx, cp32.read, hsr, 1, 1U << 3= ); case HSR_CPREG32(DBGOSDLR): return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); =20 @@ -509,8 +510,6 @@ void do_cp14_32(struct cpu_user_regs *regs, const union= hsr hsr) * * Unhandled: * DBGDCCINT - * DBGDTRRXint - * DBGDTRTXint * DBGWFAR * DBGDTRTXext * DBGDTRRXext, @@ -548,12 +547,27 @@ void do_cp14_32(struct cpu_user_regs *regs, const uni= on hsr hsr) break; } =20 + /* + * Xen doesn't expose a real (or emulated) Debug Communications Channel + * (DCC) to a domain. Yet the Arm ARM implies this is not an optional + * feature. So some domains may start to probe it. For instance, the + * HVC_DCC driver in Linux (since f377775dc083 and at least up to v6.7= ), + * will try to write some characters and check if the transmit buffer = has + * emptied. + */ case HSR_CPREG32(DBGDSCRINT): /* - * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis - * is set to 0, which we emulated below. + * By setting TX status bit (only if partial emulation is enabled)= to + * indicate the transmit buffer is full, we would hint the OS that= the + * DCC is probably not working. + * + * Bit 29: TX full + * + * Accessible at EL0 only if DBGDSCRext.UDCCdis is set to 0. We em= ulate + * this as RAZ/WI in the next case. So RO at both EL0 and EL1. */ - return handle_ro_raz(regs, regidx, cp32.read, hsr, 1); + return handle_ro_read_val(regs, regidx, cp32.read, hsr, 0, + partial_emulation ? (1U << 29) : 0); =20 case HSR_CPREG32(DBGDSCREXT): /* @@ -562,6 +576,18 @@ void do_cp14_32(struct cpu_user_regs *regs, const unio= n hsr hsr) */ return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); =20 + /* DBGDTR[TR]XINT share the same encoding */ + case HSR_CPREG32(DBGDTRTXINT): + /* + * Emulate as RAZ/WI (only if partial emulation is enabled) to pre= vent + * injecting undefined exception. + * Accessible at EL0 only if DBGDSCREXT is set to 0. We emulate th= at + * register as RAZ/WI. + */ + if ( !partial_emulation ) + goto fail; + return handle_raz_wi(regs, regidx, cp32.read, hsr, 0); + case HSR_CPREG32(DBGVCR): case HSR_CPREG32(DBGBVR0): case HSR_CPREG32(DBGBCR0): @@ -591,17 +617,20 @@ void do_cp14_32(struct cpu_user_regs *regs, const uni= on hsr hsr) * And all other unknown registers. */ default: - gdprintk(XENLOG_ERR, - "%s p14, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", - cp32.read ? "mrc" : "mcr", - cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->= pc); - gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#"PRIregister"= \n", - hsr.bits & HSR_CP32_REGS_MASK); - inject_undef_exception(regs, hsr); - return; + goto fail; } =20 advance_pc(regs, hsr); + return; + + fail: + gdprintk(XENLOG_ERR, + "%s p14, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", + cp32.read ? "mrc" : "mcr", + cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#"PRIregister"\n", + hsr.bits & HSR_CP32_REGS_MASK); + inject_undef_exception(regs, hsr); } =20 void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr) @@ -659,10 +688,7 @@ void do_cp14_dbg(struct cpu_user_regs *regs, const uni= on hsr hsr) * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 * * Unhandled: - * DBGDTRTXint - * DBGDTRRXint - * - * And all other unknown registers. + * All unknown registers. */ gdprintk(XENLOG_ERR, "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", --=20 2.25.1