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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v6 1/3] xen/arm: Introduce CONFIG_PARTIAL_EMULATION and "partial-emulation" cmd option Date: Thu, 7 Mar 2024 12:39:41 +0000 Message-ID: <20240307123943.1991755-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240307123943.1991755-1-ayan.kumar.halder@amd.com> References: <20240307123943.1991755-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AA:EE_|CH3PR12MB8971:EE_ X-MS-Office365-Filtering-Correlation-Id: ff8503de-184a-4303-da77-08dc3ea3c5da X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Mar 2024 12:40:29.8407 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff8503de-184a-4303-da77-08dc3ea3c5da X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8971 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1709815248061100001 Content-Type: text/plain; charset="utf-8" There can be situations when the registers cannot be emulated to their full functionality. This can be due to the complexity involved. In such cases, o= ne can emulate those registers as RAZ/WI for example. We call them as partial emulation. Some registers are non-optional and as such there is nothing preventing an = OS from accessing them. Instead of injecting undefined exception (which might result in crashing a guest), one may want to prefer a partial emulation to let the guest running (in some cases accepting the fact that it might result in unwanted behavior= ). A suitable example of this (as seen in subsequent patches) is emulation of DBGDTRTX_EL0 (on Arm64) and DBGDTRTXINT(on Arm32). These non-optional registers can be emulated as RAZ/WI and they can be enclosed within CONFIG_PARTIAL_EMULATION. Further, "partial-emulation" command line option allows us to enable/disable partial emulation at run time. While CONFIG_PARTIAL_EMULATION enables support for partial emulation at compile time (i.e. adds code for partial emulation), this option may be enabled or disabled by Yocto or other build systems. However if the build system turns this option on, users can use scripts like Imagebuilder to generate uboot-script which will append "partial-emulation=3Dtrue" to xen command line to turn on the partial emula= tion. Thus, it helps to avoid rebuilding xen. By default, "CONFIG_PARTIAL_EMULATION=3Dy" and "partial-emulation=3Dfalse". This is done so that Xen supports partial emulation. However, customers are fully aware when they enable partial emulation. It's important to note that enabling such support might result in unwanted/non-spec compliant behavior. Added a note in SUPPORT.md to clarify the security support for partial emulation. Signed-off-by: Ayan Kumar Halder Signed-off-by: Michal Orzel Acked-by: Julien Grall --- Changes from v1 :- 1. New patch introduced in v2. v2 :- 1. Reordered the patches so that the config and command line option is introduced in the first patch. v3 :- 1. Defined a macro 'partial_emulation' to reduce if-defs. 2. Fixed style issues. v4 :- 1. Added a note in SUPPORT.md. v5 :- 1. Dropped R-b 2. Update the commit message and Kconfig message. 3. Update 'SUPPORT.md' message. SUPPORT.md | 9 +++++++++ docs/misc/xen-command-line.pandoc | 11 +++++++++++ xen/arch/arm/Kconfig | 9 +++++++++ xen/arch/arm/include/asm/traps.h | 6 ++++++ xen/arch/arm/traps.c | 9 +++++++++ 5 files changed, 44 insertions(+) diff --git a/SUPPORT.md b/SUPPORT.md index 7eb6875cfa..b49da114ab 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -102,6 +102,15 @@ Extension to the GICv3 interrupt controller to support= MSI. =20 Status: Experimental =20 +### ARM/Partial Emulation + +Enable partial emulation of registers, otherwise considered unimplemented, +that would normally trigger a fault injection. + + Status: Supported, with caveats + +Only the following system registers are security supported: + ### ARM Scalable Vector Extension (SVE/SVE2) =20 Arm64 domains can use Scalable Vector Extension (SVE/SVE2). diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line= .pandoc index 02896598df..023c5e7225 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -1942,6 +1942,17 @@ This option is ignored in **pv-shim** mode. =20 > Default: `on` =20 +### partial-emulation (arm) +> `=3D ` + +> Default: `false` + +Flag to enable or disable partial emulation of system/coprocessor register= s. +Only effective if CONFIG_PARTIAL_EMULATION is enabled. + +**WARNING: Enabling this option might result in unwanted/non-spec compliant +behavior.** + ### pci =3D List of [ serr=3D, perr=3D ] =20 diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 40f834bb71..f8139a773a 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -234,6 +234,15 @@ config STATIC_EVTCHN This option enables establishing static event channel communication between domains on a dom0less system (domU-domU as well as domU-dom0). =20 +config PARTIAL_EMULATION + bool "Enable partial emulation of system/coprocessor registers" + default y + help + This option enables partial emulation of registers to prevent possible + guests crashing when accessing registers which are not optional but have + not been emulated to their complete functionality. Enabling this might + result in unwanted/non-spec compliant behavior. + endmenu =20 menu "ARM errata workaround via the alternative framework" diff --git a/xen/arch/arm/include/asm/traps.h b/xen/arch/arm/include/asm/tr= aps.h index 883dae368e..9a60dbf70e 100644 --- a/xen/arch/arm/include/asm/traps.h +++ b/xen/arch/arm/include/asm/traps.h @@ -10,6 +10,12 @@ # include #endif =20 +#ifdef CONFIG_PARTIAL_EMULATION +extern bool partial_emulation; +#else +#define partial_emulation false +#endif + /* * GUEST_BUG_ON is intended for checking that the guest state has not been * corrupted in hardware and/or that the hardware behaves as we diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 9c10e8f78c..d1c7a6c516 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -42,6 +42,15 @@ #include #include =20 +/* + * partial_emulation: If true, partial emulation for system/coprocessor + * registers will be enabled. + */ +#ifdef CONFIG_PARTIAL_EMULATION +bool __ro_after_init partial_emulation =3D false; +boolean_param("partial-emulation", partial_emulation); +#endif + /* The base of the stack must always be double-word aligned, which means * that both the kernel half of struct cpu_user_regs (which is pushed in * entry.S) and struct cpu_info (which lives at the bottom of a Xen --=20 2.25.1 From nobody Fri May 10 18:45:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1709815254; cv=pass; d=zohomail.com; s=zohoarc; b=KgI8XqIN+8cspTcqqS0tLf8/uNOAfbUtWfKTchAXkwL0ydwm6ebkaKlLlypbZzQkA04QZQ3y62psDYOI4x7HpRC66lL7o7JgEvT4WuZa/L+mt+xhTcAQa71qvMMIDSBas9DRU/+on96vQV2yMSilWO5NJxwDIfpMlJosE5Ce1UA= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Mar 2024 12:40:32.6190 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 77b989ad-e3b1-4ad5-2e4e-08dc3ea3c785 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9104 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1709815256105100001 Content-Type: text/plain; charset="utf-8" From: Michal Orzel Currently, if user enables HVC_DCC config option in Linux, it invokes access to debug data transfer registers (i.e. DBGDTRTX_EL0 on arm64, DBGDTRTXINT on arm32). As these registers are not emulated, Xen injects an undefined exception to the guest and Linux crashes. To prevent this crash, introduce a partial emulation of DBGDTR[TR]X_EL0 (these registers share the same encoding) as RAZ/WI and MDCCSR_EL0 as TXful= l. Refer ARM DDI 0487J.a ID042523, D19.3.8, DBGDTRTX_EL0 "If TXfull is set to 1, set DTRRX and DTRTX to UNKNOWN". Thus, any OS is expected to read MDCCSR_EL0 and check for TXfull before using DBGDTRTX_EL0. Linux does it via hvc_dcc_init() ---> hvc_dcc_check(), and returns -ENODEV in case TXfull bit is still set after writing a test character. This way we prevent the guest from making use of HVC DCC as a console. Signed-off-by: Michal Orzel Signed-off-by: Ayan Kumar Halder Acked-by: Julien Grall --- Changes from v1 :- 1. DBGDTR_EL0 does not emulate RXfull. This is to avoid giving the OS= any indication that the RX buffer is full and is waiting to be read. 2. In Arm32, DBGOSLSR is emulated. Also DBGDTRTXINT is emulated at EL0 only. 3. Fixed the commit message and inline code comments. v2 :- 1. Split the patch into two (separate patches for arm64 and arm32). 2. Removed the "fail" label. 3. Fixed the commit message. v3 :- 1. "HSR_SYSREG_MDCCSR_EL0" emulation differs based on whether=20 partial_emulation_enabled is true or not. 2. If partial_emulation_enabled is false, then access to HSR_SYSREG_DBGDTR_= EL0, HSR_SYSREG_DBGDTRTX_EL0 would lead to undefined exception.=20 v4 :- 1. Invoked "goto fail" from "default:" to ensure compliance with MISRA 15.3. v5 :- 1. Fixed style issues. 2. Removed R-b. 3. Removed HSR_SYSREG_ prefixes from registers. SUPPORT.md | 5 ++ xen/arch/arm/arm64/vsysreg.c | 69 +++++++++++++++++++--------- xen/arch/arm/include/asm/arm64/hsr.h | 3 ++ 3 files changed, 56 insertions(+), 21 deletions(-) diff --git a/SUPPORT.md b/SUPPORT.md index b49da114ab..afbd820084 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -111,6 +111,11 @@ that would normally trigger a fault injection. =20 Only the following system registers are security supported: =20 + MDCCSR_EL0 + DBGDTR_EL0 + DBGDTRTX_EL0 + DBGDTRRX_EL0 + ### ARM Scalable Vector Extension (SVE/SVE2) =20 Arm64 domains can use Scalable Vector Extension (SVE/SVE2). diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index b5d54c569b..c73b2c95ce 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -82,6 +82,7 @@ TVM_REG(CONTEXTIDR_EL1) void do_sysreg(struct cpu_user_regs *regs, const union hsr hsr) { + const struct hsr_sysreg sysreg =3D hsr.sysreg; int regidx =3D hsr.sysreg.reg; struct vcpu *v =3D current; =20 @@ -159,9 +160,6 @@ void do_sysreg(struct cpu_user_regs *regs, * * Unhandled: * MDCCINT_EL1 - * DBGDTR_EL0 - * DBGDTRRX_EL0 - * DBGDTRTX_EL0 * OSDTRRX_EL1 * OSDTRTX_EL1 * OSECCR_EL1 @@ -171,12 +169,42 @@ void do_sysreg(struct cpu_user_regs *regs, */ case HSR_SYSREG_MDSCR_EL1: return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * Xen doesn't expose a real (or emulated) Debug Communications Channel + * (DCC) to a domain. Yet the Arm ARM implies this is not an optional + * feature. So some domains may start to probe it. For instance, the + * HVC_DCC driver in Linux (since f377775dc083 and at least up to v6.7= ), + * will try to write some characters and check if the transmit buffer + * has emptied. + */ case HSR_SYSREG_MDCCSR_EL0: /* + * By setting TX status bit (only if partial emulation is enabled)= to + * indicate the transmit buffer is full, we would hint the OS that= the + * DCC is probably not working. + * + * Bit 29: TX full + * * Accessible at EL0 only if MDSCR_EL1.TDCC is set to 0. We emulat= e that * register as RAZ/WI above. So RO at both EL0 and EL1. */ - return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); + return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, 0, + partial_emulation ? (1U << 29) : 0); + + case HSR_SYSREG_DBGDTR_EL0: + /* DBGDTR[TR]X_EL0 share the same encoding */ + case HSR_SYSREG_DBGDTRTX_EL0: + /* + * Emulate as RAZ/WI (only if partial emulation is enabled) to pre= vent + * injecting undefined exception. + * Accessible at EL0 only if MDSCR_EL1.TDCC is set to 0. We emulat= e that + * register as RAZ/WI. + */ + if ( !partial_emulation ) + goto fail; + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 0); + HSR_SYSREG_DBG_CASES(DBGBVR): HSR_SYSREG_DBG_CASES(DBGBCR): HSR_SYSREG_DBG_CASES(DBGWVR): @@ -394,26 +422,25 @@ void do_sysreg(struct cpu_user_regs *regs, * And all other unknown registers. */ default: - { - const struct hsr_sysreg sysreg =3D hsr.sysreg; - - gdprintk(XENLOG_ERR, - "%s %d, %d, c%d, c%d, %d %s x%d @ 0x%"PRIregister"\n", - sysreg.read ? "mrs" : "msr", - sysreg.op0, sysreg.op1, - sysreg.crn, sysreg.crm, - sysreg.op2, - sysreg.read ? "=3D>" : "<=3D", - sysreg.reg, regs->pc); - gdprintk(XENLOG_ERR, - "unhandled 64-bit sysreg access %#"PRIregister"\n", - hsr.bits & HSR_SYSREG_REGS_MASK); - inject_undef_exception(regs, hsr); - return; - } + goto fail; } =20 regs->pc +=3D 4; + return; + + fail: + gdprintk(XENLOG_ERR, + "%s %d, %d, c%d, c%d, %d %s x%d @ 0x%"PRIregister"\n", + sysreg.read ? "mrs" : "msr", + sysreg.op0, sysreg.op1, + sysreg.crn, sysreg.crm, + sysreg.op2, + sysreg.read ? "=3D>" : "<=3D", + sysreg.reg, regs->pc); + gdprintk(XENLOG_ERR, + "unhandled 64-bit sysreg access %#"PRIregister"\n", + hsr.bits & HSR_SYSREG_REGS_MASK); + inject_undef_exception(regs, hsr); } =20 /* diff --git a/xen/arch/arm/include/asm/arm64/hsr.h b/xen/arch/arm/include/as= m/arm64/hsr.h index e691d41c17..1495ccddea 100644 --- a/xen/arch/arm/include/asm/arm64/hsr.h +++ b/xen/arch/arm/include/asm/arm64/hsr.h @@ -47,6 +47,9 @@ #define HSR_SYSREG_OSDLR_EL1 HSR_SYSREG(2,0,c1,c3,4) #define HSR_SYSREG_DBGPRCR_EL1 HSR_SYSREG(2,0,c1,c4,4) #define HSR_SYSREG_MDCCSR_EL0 HSR_SYSREG(2,3,c0,c1,0) +#define HSR_SYSREG_DBGDTR_EL0 HSR_SYSREG(2,3,c0,c4,0) +#define HSR_SYSREG_DBGDTRTX_EL0 HSR_SYSREG(2,3,c0,c5,0) +#define HSR_SYSREG_DBGDTRRX_EL0 HSR_SYSREG(2,3,c0,c5,0) =20 #define HSR_SYSREG_DBGBVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,4) #define HSR_SYSREG_DBGBCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,5) --=20 2.25.1 From nobody Fri May 10 18:45:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v6 3/3] xen/arm: arm32: Add emulation of Debug Data Transfer Registers Date: Thu, 7 Mar 2024 12:39:43 +0000 Message-ID: <20240307123943.1991755-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240307123943.1991755-1-ayan.kumar.halder@amd.com> References: <20240307123943.1991755-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEA:EE_|CY8PR12MB8195:EE_ X-MS-Office365-Filtering-Correlation-Id: 41aa4874-edf2-44d1-00a1-08dc3ea3c8fc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Mar 2024 12:40:35.1223 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41aa4874-edf2-44d1-00a1-08dc3ea3c8fc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8195 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1709815258090100003 Content-Type: text/plain; charset="utf-8" When user enables HVC_DCC config option in Linux, it invokes access to debug transfer register (i.e. DBGDTRTXINT). As this register is not emulated, Xen injects an undefined exception to the guest and Linux crashes. To prevent this crash, introduce a partial emulation of DBGDTR[TR]XINT (the= se registers share the same encoding) as RAZ/WI and DBGDSCRINT as TXfull. Refer ARM DDI 0487J.a ID042523, G8.3.19, DBGDTRTXint: "If TXfull is set to 1, set DTRTX to UNKNOWN". As a pre-requisite, DBGOSLSR should be emulated in the same way as its AArc= h64 variant (i.e. OSLSR_EL1). This is to ensure that DBGOSLSR.OSLK is 0, which allows us to skip the emulation of DBGDSCREXT (TXfull is treated as UNK/SBZ= P) and focus on DBGDSCRINT. DBGOSLSR.OSLM[1] is set to 1 to mantain consistency with Arm64. Take the opportunity to fix the minimum EL for DBGDSCRINT, which should be = 0. Signed-off-by: Ayan Kumar Halder Signed-off-by: Michal Orzel Acked-by: Julien Grall --- Changes from v1 :- 1. DBGDTR_EL0 does not emulate RXfull. This is to avoid giving the OS= any indication that the RX buffer is full and is waiting to be read. 2. In Arm32, DBGOSLSR is emulated. Also DBGDTRTXINT is emulated at EL0 only. 3. Fixed the commit message and inline code comments. v2 :- 1. Split the patch into two (separate patches for arm64 and arm32). 2. Fixed in line comments and style related issues. 3. Updated commit message to mention DBGDSCRINT handling. v3 :- 1. The original emulation of DBGDSCRINT is retained when 'partial_emulation' is false. 2. If 'partial_emulation' is false, then access to DBGDTRTXINT will lead to undefined exception. v4 :- 1. Invoked "goto fail" from "default:" to ensure compliance with MISRA 15.3. v5 :- 1. Reword the commit message 2. Remove the 'return' at the end of function. SUPPORT.md | 3 ++ xen/arch/arm/include/asm/cpregs.h | 2 + xen/arch/arm/vcpreg.c | 62 ++++++++++++++++++++++--------- 3 files changed, 49 insertions(+), 18 deletions(-) diff --git a/SUPPORT.md b/SUPPORT.md index afbd820084..e0ff30cfe9 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -115,6 +115,9 @@ Only the following system registers are security suppor= ted: DBGDTR_EL0 DBGDTRTX_EL0 DBGDTRRX_EL0 + DBGDSCRINT + DBGDTRTXINT + DBGDTRRXINT =20 ### ARM Scalable Vector Extension (SVE/SVE2) =20 diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/c= pregs.h index 6b083de204..aec9e8f329 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -75,6 +75,8 @@ #define DBGDIDR p14,0,c0,c0,0 /* Debug ID Register */ #define DBGDSCRINT p14,0,c0,c1,0 /* Debug Status and Control Intern= al */ #define DBGDSCREXT p14,0,c0,c2,2 /* Debug Status and Control Extern= al */ +#define DBGDTRRXINT p14,0,c0,c5,0 /* Debug Data Transfer Register, R= eceive */ +#define DBGDTRTXINT p14,0,c0,c5,0 /* Debug Data Transfer Register, T= ransmit */ #define DBGVCR p14,0,c0,c7,0 /* Vector Catch */ #define DBGBVR0 p14,0,c0,c0,4 /* Breakpoint Value 0 */ #define DBGBCR0 p14,0,c0,c0,5 /* Breakpoint Control 0 */ diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index a2d0500704..b203f4a142 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -493,11 +493,12 @@ void do_cp14_32(struct cpu_user_regs *regs, const uni= on hsr hsr) * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 * * Unhandled: - * DBGOSLSR * DBGPRCR */ case HSR_CPREG32(DBGOSLAR): return handle_wo_wi(regs, regidx, cp32.read, hsr, 1); + case HSR_CPREG32(DBGOSLSR): + return handle_ro_read_val(regs, regidx, cp32.read, hsr, 1, 1U << 3= ); case HSR_CPREG32(DBGOSDLR): return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); =20 @@ -509,8 +510,6 @@ void do_cp14_32(struct cpu_user_regs *regs, const union= hsr hsr) * * Unhandled: * DBGDCCINT - * DBGDTRRXint - * DBGDTRTXint * DBGWFAR * DBGDTRTXext * DBGDTRRXext, @@ -548,12 +547,27 @@ void do_cp14_32(struct cpu_user_regs *regs, const uni= on hsr hsr) break; } =20 + /* + * Xen doesn't expose a real (or emulated) Debug Communications Channel + * (DCC) to a domain. Yet the Arm ARM implies this is not an optional + * feature. So some domains may start to probe it. For instance, the + * HVC_DCC driver in Linux (since f377775dc083 and at least up to v6.7= ), + * will try to write some characters and check if the transmit buffer = has + * emptied. + */ case HSR_CPREG32(DBGDSCRINT): /* - * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis - * is set to 0, which we emulated below. + * By setting TX status bit (only if partial emulation is enabled)= to + * indicate the transmit buffer is full, we would hint the OS that= the + * DCC is probably not working. + * + * Bit 29: TX full + * + * Accessible at EL0 only if DBGDSCRext.UDCCdis is set to 0. We em= ulate + * this as RAZ/WI in the next case. So RO at both EL0 and EL1. */ - return handle_ro_raz(regs, regidx, cp32.read, hsr, 1); + return handle_ro_read_val(regs, regidx, cp32.read, hsr, 0, + partial_emulation ? (1U << 29) : 0); =20 case HSR_CPREG32(DBGDSCREXT): /* @@ -562,6 +576,18 @@ void do_cp14_32(struct cpu_user_regs *regs, const unio= n hsr hsr) */ return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); =20 + /* DBGDTR[TR]XINT share the same encoding */ + case HSR_CPREG32(DBGDTRTXINT): + /* + * Emulate as RAZ/WI (only if partial emulation is enabled) to pre= vent + * injecting undefined exception. + * Accessible at EL0 only if DBGDSCREXT is set to 0. We emulate th= at + * register as RAZ/WI. + */ + if ( !partial_emulation ) + goto fail; + return handle_raz_wi(regs, regidx, cp32.read, hsr, 0); + case HSR_CPREG32(DBGVCR): case HSR_CPREG32(DBGBVR0): case HSR_CPREG32(DBGBCR0): @@ -591,17 +617,20 @@ void do_cp14_32(struct cpu_user_regs *regs, const uni= on hsr hsr) * And all other unknown registers. */ default: - gdprintk(XENLOG_ERR, - "%s p14, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", - cp32.read ? "mrc" : "mcr", - cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->= pc); - gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#"PRIregister"= \n", - hsr.bits & HSR_CP32_REGS_MASK); - inject_undef_exception(regs, hsr); - return; + goto fail; } =20 advance_pc(regs, hsr); + return; + + fail: + gdprintk(XENLOG_ERR, + "%s p14, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", + cp32.read ? "mrc" : "mcr", + cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#"PRIregister"\n", + hsr.bits & HSR_CP32_REGS_MASK); + inject_undef_exception(regs, hsr); } =20 void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr) @@ -659,10 +688,7 @@ void do_cp14_dbg(struct cpu_user_regs *regs, const uni= on hsr hsr) * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 * * Unhandled: - * DBGDTRTXint - * DBGDTRRXint - * - * And all other unknown registers. + * All unknown registers. */ gdprintk(XENLOG_ERR, "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", --=20 2.25.1