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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , Ayan Kumar Halder Subject: [XEN v4 2/3] xen/arm: arm64: Add emulation of Debug Data Transfer Registers Date: Wed, 31 Jan 2024 12:10:48 +0000 Message-ID: <20240131121049.225044-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240131121049.225044-1-ayan.kumar.halder@amd.com> References: <20240131121049.225044-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D6:EE_|CH0PR12MB8551:EE_ X-MS-Office365-Filtering-Correlation-Id: ad937851-3f65-4330-8dbe-08dc22562672 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: i6EgjIQDpl29VgWpO5SNz8tRbuXyDKXaOcheGEHwR+Y2GHKYABO5SXyfUTBqBrCoeX6PrwYk9YlwAi4umnjmgDBpRnNQkQah/lsmeqJUSsJx3cG4lGMH8nAlFIqbT6M5yCjwCJq05LPC9z6NQB1L1hPwsIEx5Av5riL6PWjuw+n9SzElqtqAvNLVbf8OGOW7XZ8oXuUeSg17aENVwPyI0ztdFtG7n5kSs+dUzTyRgqEKbmTMlfBeIrdBjG5i1Sa+xQ/EIqxdLhJDvpCKKBlP4zoQPjBUV/EBQlI1zgEhWV15AqTVDSzRlzX3KgdmSrwDWn31zUHIFmVAgvmPXP52e3CXMFUrZBAxytClAZpYzZl/1GkXOJaTPeGvmSmvBl/jJHG7G3ISXFfI/MZsAyZCjQDtaGX8SYEKkqlwoQSEFSgwscBmdpRCSJ/cSI/Ho+FqcznQE94VRldJwHn5JHkXGvVQGIsH8QOjTaq5RKmXUW8jkf0imKWEurVTeVfAG46ANqTCY6wJa88nxJA37R/BK6pBlV/8x6IOXrHOW44PHnlWtXhJBG4wtVRablwMN6k5xKuTEVslGY6mGOIZ6NI19jywgeJtReqosA7pHsJfTAF/dQ0lkSPMxY3UdDJZESZlpcQYZUy9DjescWUjezZave7IsAv2NKzp/Jddoxy/hfh2oh8BpyTqnmHhcPdM0RPaNL7k3/uXTVvo+NwZx4Kgy7aaVdhcjnNDdTD2JpNaC7+vbU5/RmkdyOte2vT/zxHWchHWYdu5s+scsAMuwjTEJA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(346002)(376002)(136003)(230922051799003)(64100799003)(186009)(82310400011)(1800799012)(451199024)(46966006)(36840700001)(40470700004)(6916009)(316002)(70206006)(54906003)(478600001)(70586007)(6666004)(8936002)(8676002)(4326008)(1076003)(5660300002)(26005)(426003)(2616005)(336012)(2906002)(83380400001)(47076005)(81166007)(40460700003)(82740400003)(86362001)(40480700001)(41300700001)(36756003)(103116003)(36860700001)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jan 2024 12:14:18.5934 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad937851-3f65-4330-8dbe-08dc22562672 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8551 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1706703287563100001 Content-Type: text/plain; charset="utf-8" From: Michal Orzel Currently, if user enables HVC_DCC config option in Linux, it invokes access to debug data transfer registers (i.e. DBGDTRTX_EL0 on arm64, DBGDTRTXINT on arm32). As these registers are not emulated, Xen injects an undefined exception to the guest and Linux crashes. To prevent this crash, introduce a partial emulation of DBGDTR[TR]X_EL0 (these registers share the same encoding) as RAZ/WI and MDCCSR_EL0 as TXful= l. Refer ARM DDI 0487J.a ID042523, D19.3.8, DBGDTRTX_EL0 "If TXfull is set to 1, set DTRRX and DTRTX to UNKNOWN". Thus, any OS is expected to read MDCCSR_EL0 and check for TXfull before using DBGDTRTX_EL0. Linux does it via hvc_dcc_init() ---> hvc_dcc_check(), and returns -ENODEV in case TXfull bit is still set after writing a test character. This way we prevent the guest from making use of HVC DCC as a console. Signed-off-by: Michal Orzel Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel --- Changes from v1 :- 1. DBGDTR_EL0 does not emulate RXfull. This is to avoid giving the OS= any indication that the RX buffer is full and is waiting to be read. 2. In Arm32, DBGOSLSR is emulated. Also DBGDTRTXINT is emulated at EL0 only. 3. Fixed the commit message and inline code comments. v2 :- 1. Split the patch into two (separate patches for arm64 and arm32). 2. Removed the "fail" label. 3. Fixed the commit message. v3 :- 1. "HSR_SYSREG_MDCCSR_EL0" emulation differs based on whether=20 partial_emulation_enabled is true or not. 2. If partial_emulation_enabled is false, then access to HSR_SYSREG_DBGDTR_= EL0, HSR_SYSREG_DBGDTRTX_EL0 would lead to undefined exception.=20 xen/arch/arm/arm64/vsysreg.c | 28 ++++++++++++++++++++++++---- xen/arch/arm/include/asm/arm64/hsr.h | 3 +++ 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index b5d54c569b..94f0a6c384 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -159,9 +159,6 @@ void do_sysreg(struct cpu_user_regs *regs, * * Unhandled: * MDCCINT_EL1 - * DBGDTR_EL0 - * DBGDTRRX_EL0 - * DBGDTRTX_EL0 * OSDTRRX_EL1 * OSDTRTX_EL1 * OSECCR_EL1 @@ -173,10 +170,32 @@ void do_sysreg(struct cpu_user_regs *regs, return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); case HSR_SYSREG_MDCCSR_EL0: /* + * Xen doesn't expose a real (or emulated) Debug Communications Ch= annel + * (DCC) to a domain. Yet the Arm ARM implies this is not an optio= nal + * feature. So some domains may start to probe it. For instance, t= he + * HVC_DCC driver in Linux (since f377775dc083 and at least up to = v6.7), + * will try to write some characters and check if the transmit buf= fer + * has emptied. + * + * By setting TX status bit (only if partial emulation is enabled)= to + * indicate the transmit buffer is full, we would hint the OS that= the + * DCC is probably not working. + * + * Bit 29: TX full + * * Accessible at EL0 only if MDSCR_EL1.TDCC is set to 0. We emulat= e that * register as RAZ/WI above. So RO at both EL0 and EL1. */ - return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); + return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, 0, + partial_emulation ? (1U << 29) : 0); + + case HSR_SYSREG_DBGDTR_EL0: + /* DBGDTR[TR]X_EL0 share the same encoding */ + case HSR_SYSREG_DBGDTRTX_EL0: + if ( !partial_emulation ) + goto fail; + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 0); + HSR_SYSREG_DBG_CASES(DBGBVR): HSR_SYSREG_DBG_CASES(DBGBCR): HSR_SYSREG_DBG_CASES(DBGWVR): @@ -394,6 +413,7 @@ void do_sysreg(struct cpu_user_regs *regs, * And all other unknown registers. */ default: + fail: { const struct hsr_sysreg sysreg =3D hsr.sysreg; =20 diff --git a/xen/arch/arm/include/asm/arm64/hsr.h b/xen/arch/arm/include/as= m/arm64/hsr.h index e691d41c17..1495ccddea 100644 --- a/xen/arch/arm/include/asm/arm64/hsr.h +++ b/xen/arch/arm/include/asm/arm64/hsr.h @@ -47,6 +47,9 @@ #define HSR_SYSREG_OSDLR_EL1 HSR_SYSREG(2,0,c1,c3,4) #define HSR_SYSREG_DBGPRCR_EL1 HSR_SYSREG(2,0,c1,c4,4) #define HSR_SYSREG_MDCCSR_EL0 HSR_SYSREG(2,3,c0,c1,0) +#define HSR_SYSREG_DBGDTR_EL0 HSR_SYSREG(2,3,c0,c4,0) +#define HSR_SYSREG_DBGDTRTX_EL0 HSR_SYSREG(2,3,c0,c5,0) +#define HSR_SYSREG_DBGDTRRX_EL0 HSR_SYSREG(2,3,c0,c5,0) =20 #define HSR_SYSREG_DBGBVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,4) #define HSR_SYSREG_DBGBCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,5) --=20 2.25.1