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Wed, 10 Jan 2024 07:34:33 -0800 (PST) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: Roger Pau Monne , Jan Beulich , Andrew Cooper , Wei Liu Subject: [PATCH] x86/nmi: ensure Global Performance Counter Control is setup correctly Date: Wed, 10 Jan 2024 16:34:00 +0100 Message-ID: <20240110153400.64017-1-roger.pau@citrix.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1704900894105100001 When Architectural Performance Monitoring is available, the PERF_GLOBAL_CTRL MSR contains per-counter enable bits that is ANDed with the enable bit in t= he counter EVNTSEL MSR in order for a PMC counter to be enabled. So far the watchdog code seems to have relied on the PERF_GLOBAL_CTRL enable bits being set by default, but at least on some Intel Sapphire and Emerald Rapids this is no longer the case, and Xen reports: Testing NMI watchdog on all CPUs: 0 40 stuck The first CPU on each socket is started with PERF_GLOBAL_CTRL zeroed, so PM= C0 doesn't start counting when the enable bit in EVNTSEL0 is set, due to the relevant enable bit in PERF_GLOBAL_CTRL not being set. Fix by detecting when Architectural Performance Monitoring is available and making sure the enable bit for PMC0 is set in PERF_GLOBAL_CTRL. Signed-off-by: Roger Pau Monn=C3=A9 --- The fact that it's only the first CPU on each socket that's started with PERF_GLOBAL_CTRL clear looks like a firmware bug to me, but in any case mak= ing sure PERF_GLOBAL_CTRL is properly setup should be done regardless. --- xen/arch/x86/nmi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c index dc79c25e3ffd..7a6601c4fd31 100644 --- a/xen/arch/x86/nmi.c +++ b/xen/arch/x86/nmi.c @@ -335,6 +335,19 @@ static void setup_p6_watchdog(unsigned counter) nmi_p6_event_width > BITS_PER_LONG ) return; =20 + if ( cpu_has_arch_perfmon ) + { + uint64_t global_ctrl; + + rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, global_ctrl); + /* + * Make sure PMC0 is enabled in global control, as the enable bit = in + * PERF_GLOBAL_CTRL is AND'ed with the enable bit in EVNTSEL0. + */ + if ( !(global_ctrl & 1) ) + wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, global_ctrl | 1); + } + clear_msr_range(MSR_P6_EVNTSEL(0), 2); clear_msr_range(MSR_P6_PERFCTR(0), 2); =20 --=20 2.43.0