From nobody Mon Feb 9 06:49:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701354936; cv=none; d=zohomail.com; s=zohoarc; b=SFf/EiozqnPMg6nkCf1Wswbxy0kqyDFY2BQBfEcbVM5t1CYPCXfKWeuXOcB+OqKkBMYeITroxVqj9/oSStXVJ/M23iplHUTFLGUuFbsuutkgcm58NLzlhYNmwXeigwvee8s7emRpFKKgdnLLCSN+akChgTTA5yTObuwVDB/r6yU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701354936; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=d0Ga5ikdsdqlhyMzLOc2LbcPBfD9RM1dLJtf4FVVs78=; b=a50cUFpPKRKEb6V/P9ecJyvD1eYUiZEO8s8YIP51nZtKdtqTiVZO956jkkYLyMqts3FXt5/1SUruEKLrNMbGttWLCHVpcqH4uK4rN9WO6G4xkk4SrwxxNuxyMWwgmFgW2w/a/H+Lbs5h5EWts5LFUF8s58aDXNMe8wCtQcXCmCU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1701354936080340.88316332545025; Thu, 30 Nov 2023 06:35:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r8i89-0000Lu-O3; Thu, 30 Nov 2023 09:35:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i86-0000BJ-WE; Thu, 30 Nov 2023 09:35:03 -0500 Received: from mgamail.intel.com ([192.55.52.43]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i85-0001d0-3b; Thu, 30 Nov 2023 09:35:02 -0500 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 06:34:56 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga005.jf.intel.com with ESMTP; 30 Nov 2023 06:34:47 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701354901; x=1732890901; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FbB6vbX6bR4dqU1fCV07ghJ+c5nYYHlqh35CAqrTsmY=; b=B/nP++8jsG+K2z9pnGPDpayNbQ2YXtdACARmebKqiqXEGl2dBrcX2657 +x9QBSlx/lW+m7eC7n0j/cto7yJ0HGWtogRPlwzdRUdDyRWm4b3hlV7kr RR2jmSPoh1YtS63KNKdQdrkKb9he9RXVOLzBDQXY3R3uSeGfmGDpzzkhR IxUoGFo4l/wJXoEJidYaie/2IxKy3KIlm/oH4TJkNgHQKiNVQpAzmmrUJ 5cSP0OwXrF9xa9lMRLbozr+t7EBVzuFm/yyotH5eWr5aE/ZfZae/7cEjc vAy1XwoG/5jPlErXBfKWblmwi2Xffi4lpVjcQ/ChqzxP/u9adri9ir9iF Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="479532317" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="479532317" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="942730130" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="942730130" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Richard Henderson , "Michael S . Tsirkin" , Jason Wang , Nicholas Piggin , Daniel Henrique Barboza , Igor Mammedov , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , David Gibson , Harsh Prateek Bora , Stefano Stabellini , Anthony Perard , Paul Durrant , Gerd Hoffmann , Peter Maydell , Alistair Francis , "Edgar E . Iglesias" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Bin Meng , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-ppc@nongnu.org, xen-devel@lists.xenproject.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: Nina Schoetterl-Glausch , Thomas Huth , Zhiyuan Lv , Zhenyu Wang , Yongwei Ma , Zhao Liu Subject: [RFC 28/41] hw/core/slot: Maintain the core queue in CPU slot Date: Thu, 30 Nov 2023 22:41:50 +0800 Message-Id: <20231130144203.2307629-29-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> References: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.43; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1701354939028000001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Maintain the cores queue at cpu-slot to facilitate direct traversal of all cores. Signed-off-by: Zhao Liu --- hw/core/cpu-slot.c | 43 ++++++++++++++++++++++++++++++++++++++ include/hw/core/cpu-slot.h | 9 ++++++++ include/hw/cpu/core.h | 2 ++ 3 files changed, 54 insertions(+) diff --git a/hw/core/cpu-slot.c b/hw/core/cpu-slot.c index 5aef5b0189c2..a6b7d98dea18 100644 --- a/hw/core/cpu-slot.c +++ b/hw/core/cpu-slot.c @@ -22,6 +22,40 @@ =20 #include "hw/core/cpu-slot.h" =20 +static void cpu_slot_add_topo_info(CPUTopoState *root, CPUTopoState *child) +{ + CPUSlot *slot =3D CPU_SLOT(root); + CPUTopoLevel level =3D CPU_TOPO_LEVEL(child); + + if (level =3D=3D CPU_TOPO_CORE) { + QTAILQ_INSERT_TAIL(&slot->cores, CPU_CORE(child), node); + } + return; +} + +static void cpu_slot_del_topo_info(CPUTopoState *root, CPUTopoState *child) +{ + CPUSlot *slot =3D CPU_SLOT(root); + CPUTopoLevel level =3D CPU_TOPO_LEVEL(child); + + if (level =3D=3D CPU_TOPO_CORE) { + QTAILQ_REMOVE(&slot->cores, CPU_CORE(child), node); + } + return; +} + +static void cpu_slot_update_topo_info(CPUTopoState *root, CPUTopoState *ch= ild, + bool is_realize) +{ + g_assert(child->parent); + + if (is_realize) { + cpu_slot_add_topo_info(root, child); + } else { + cpu_slot_del_topo_info(root, child); + } +} + static void cpu_slot_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -31,12 +65,21 @@ static void cpu_slot_class_init(ObjectClass *oc, void *= data) dc->user_creatable =3D false; =20 tc->level =3D CPU_TOPO_ROOT; + tc->update_topo_info =3D cpu_slot_update_topo_info; +} + +static void cpu_slot_instance_init(Object *obj) +{ + CPUSlot *slot =3D CPU_SLOT(obj); + + QTAILQ_INIT(&slot->cores); } =20 static const TypeInfo cpu_slot_type_info =3D { .name =3D TYPE_CPU_SLOT, .parent =3D TYPE_CPU_TOPO, .class_init =3D cpu_slot_class_init, + .instance_init =3D cpu_slot_instance_init, .instance_size =3D sizeof(CPUSlot), }; =20 diff --git a/include/hw/core/cpu-slot.h b/include/hw/core/cpu-slot.h index 718c8ecaa751..d2a1160562be 100644 --- a/include/hw/core/cpu-slot.h +++ b/include/hw/core/cpu-slot.h @@ -22,17 +22,26 @@ #define CPU_SLOT_H =20 #include "hw/core/cpu-topo.h" +#include "hw/cpu/core.h" #include "hw/qdev-core.h" =20 #define TYPE_CPU_SLOT "cpu-slot" =20 OBJECT_DECLARE_SIMPLE_TYPE(CPUSlot, CPU_SLOT) =20 +/** + * CPUSlot: + * @cores: Queue consisting of all the cores in the topology tree + * where the cpu-slot is the root. cpu-slot can maintain similar + * queues for other topology levels to facilitate traversal + * when necessary. + */ struct CPUSlot { /*< private >*/ CPUTopoState parent_obj; =20 /*< public >*/ + QTAILQ_HEAD(, CPUCore) cores; }; =20 #endif /* CPU_SLOT_H */ diff --git a/include/hw/cpu/core.h b/include/hw/cpu/core.h index 591240861efb..65dc10931190 100644 --- a/include/hw/cpu/core.h +++ b/include/hw/cpu/core.h @@ -40,6 +40,8 @@ struct CPUCore { * "-device"/"device_add"? */ int plugged_threads; + + QTAILQ_ENTRY(CPUCore) node; }; =20 #endif --=20 2.34.1