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d="scan'208";a="128715171" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Stefano Stabellini , Roberto Bagnara , Nicola Vetrini , Simone Ballarin Subject: [PATCH 3/3] xen/MISRA: Remove nonstandard inline keywords Date: Wed, 22 Nov 2023 14:27:33 +0000 Message-ID: <20231122142733.1818331-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20231122142733.1818331-1-andrew.cooper3@citrix.com> References: <20231122142733.1818331-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1700663297481100005 The differences between inline, __inline and __inline__ keywords are a vestigial remnant of older C standards, and in Xen we use inline almost exclusively. Replace __inline and __inline__ with regular inline, and remove their exceptions from the MISRA configuration. Signed-off-by: Andrew Cooper Reviewed-by: Simone Ballarin Reviewed-by: Stefano Stabellini --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Stefano Stabellini CC: Roberto Bagnara CC: Nicola Vetrini CC: Simone Ballarin I'm entirely guessing at the Eclair configuration. --- .../eclair_analysis/ECLAIR/toolchain.ecl | 6 +++--- docs/misra/C-language-toolchain.rst | 2 +- xen/arch/x86/include/asm/apic.h | 20 +++++++++---------- xen/include/acpi/cpufreq/cpufreq.h | 4 ++-- xen/include/xen/bitops.h | 4 ++-- xen/include/xen/compiler.h | 7 +++---- 6 files changed, 21 insertions(+), 22 deletions(-) diff --git a/automation/eclair_analysis/ECLAIR/toolchain.ecl b/automation/e= clair_analysis/ECLAIR/toolchain.ecl index e6cd289b5e92..71a1e2cce029 100644 --- a/automation/eclair_analysis/ECLAIR/toolchain.ecl +++ b/automation/eclair_analysis/ECLAIR/toolchain.ecl @@ -15,7 +15,7 @@ _Static_assert: see Section \"2.1 C Language\" of "GCC_MANUAL". asm, __asm__: see Sections \"6.48 Alternate Keywords\" and \"6.47 How = to Use Inline Assembly Language in C Code\" of "GCC_MANUAL". __volatile__: see Sections \"6.48 Alternate Keywords\" and \"6.47.2.1 = Volatile\" of "GCC_MANUAL". - __const__, __inline__, __inline: see Section \"6.48 Alternate Keywords= \" of "GCC_MANUAL". + __const__ : see Section \"6.48 Alternate Keywords\" of "GCC_MANUAL". typeof, __typeof__: see Section \"6.7 Referring to a Type with typeof\= " of "GCC_MANUAL". __alignof__, __alignof: see Sections \"6.48 Alternate Keywords\" and \= "6.44 Determining the Alignment of Functions, Types or Variables\" of "GCC_= MANUAL". __attribute__: see Section \"6.39 Attribute Syntax\" of "GCC_MANUAL". @@ -23,8 +23,8 @@ __builtin_va_arg: non-documented GCC extension. __builtin_offsetof: see Section \"6.53 Support for offsetof\" of "GCC_= MANUAL". " --config=3DSTD.tokenext,behavior+=3D{c99, GCC_ARM64, "^(_Static_assert|asm|= __asm__|__volatile__|__const__|__inline__|typeof|__typeof__|__alignof__|__a= ttribute__|__builtin_types_compatible_p|__builtin_va_arg|__builtin_offsetof= )$"} --config=3DSTD.tokenext,behavior+=3D{c99, GCC_X86_64, "^(_Static_assert|asm= |__asm__|__volatile__|__const__|__inline__|__inline|typeof|__typeof__|__ali= gnof__|__alignof|__attribute__|__builtin_types_compatible_p|__builtin_va_ar= g|__builtin_offsetof)$"} +-config=3DSTD.tokenext,behavior+=3D{c99, GCC_ARM64, "^(_Static_assert|asm|= __asm__|__volatile__|__const__|typeof|__typeof__|__alignof__|__attribute__|= __builtin_types_compatible_p|__builtin_va_arg|__builtin_offsetof)$"} +-config=3DSTD.tokenext,behavior+=3D{c99, GCC_X86_64, "^(_Static_assert|asm= |__asm__|__volatile__|__const__|typeof|__typeof__|__alignof__|__alignof|__a= ttribute__|__builtin_types_compatible_p|__builtin_va_arg|__builtin_offsetof= )$"} -doc_end =20 -doc_begin=3D"Non-documented GCC extension." diff --git a/docs/misra/C-language-toolchain.rst b/docs/misra/C-language-to= olchain.rst index 2866cb191b1a..b7c2000992ac 100644 --- a/docs/misra/C-language-toolchain.rst +++ b/docs/misra/C-language-toolchain.rst @@ -84,7 +84,7 @@ The table columns are as follows: see Sections "6.48 Alternate Keywords" and "6.47 How to Use Inli= ne Assembly Language in C Code" of GCC_MANUAL. __volatile__: see Sections "6.48 Alternate Keywords" and "6.47.2.1 Volatile" o= f GCC_MANUAL. - __const__, __inline__, __inline: + __const__: see Section "6.48 Alternate Keywords" of GCC_MANUAL. typeof, __typeof__: see Section "6.7 Referring to a Type with typeof" of GCC_MANUAL. diff --git a/xen/arch/x86/include/asm/apic.h b/xen/arch/x86/include/asm/api= c.h index 486d689478b2..b20fae7ebc6a 100644 --- a/xen/arch/x86/include/asm/apic.h +++ b/xen/arch/x86/include/asm/apic.h @@ -49,12 +49,12 @@ const struct genapic *apic_x2apic_probe(void); * Basic functions accessing APICs. */ =20 -static __inline void apic_mem_write(unsigned long reg, u32 v) +static inline void apic_mem_write(unsigned long reg, u32 v) { *((volatile u32 *)(APIC_BASE+reg)) =3D v; } =20 -static __inline u32 apic_mem_read(unsigned long reg) +static inline u32 apic_mem_read(unsigned long reg) { return *((volatile u32 *)(APIC_BASE+reg)); } @@ -63,7 +63,7 @@ static __inline u32 apic_mem_read(unsigned long reg) * access the 64-bit ICR register. */ =20 -static __inline void apic_wrmsr(unsigned long reg, uint64_t msr_content) +static inline void apic_wrmsr(unsigned long reg, uint64_t msr_content) { if (reg =3D=3D APIC_DFR || reg =3D=3D APIC_ID || reg =3D=3D APIC_LDR || reg =3D=3D APIC_LVR) @@ -72,7 +72,7 @@ static __inline void apic_wrmsr(unsigned long reg, uint64= _t msr_content) wrmsrl(MSR_X2APIC_FIRST + (reg >> 4), msr_content); } =20 -static __inline uint64_t apic_rdmsr(unsigned long reg) +static inline uint64_t apic_rdmsr(unsigned long reg) { uint64_t msr_content; =20 @@ -83,7 +83,7 @@ static __inline uint64_t apic_rdmsr(unsigned long reg) return msr_content; } =20 -static __inline void apic_write(unsigned long reg, u32 v) +static inline void apic_write(unsigned long reg, u32 v) { =20 if ( x2apic_enabled ) @@ -92,7 +92,7 @@ static __inline void apic_write(unsigned long reg, u32 v) apic_mem_write(reg, v); } =20 -static __inline u32 apic_read(unsigned long reg) +static inline u32 apic_read(unsigned long reg) { if ( x2apic_enabled ) return apic_rdmsr(reg); @@ -100,7 +100,7 @@ static __inline u32 apic_read(unsigned long reg) return apic_mem_read(reg); } =20 -static __inline u64 apic_icr_read(void) +static inline u64 apic_icr_read(void) { u32 lo, hi; =20 @@ -115,7 +115,7 @@ static __inline u64 apic_icr_read(void) return ((u64)lo) | (((u64)hi) << 32); } =20 -static __inline void apic_icr_write(u32 low, u32 dest) +static inline void apic_icr_write(u32 low, u32 dest) { if ( x2apic_enabled ) apic_wrmsr(APIC_ICR, low | ((uint64_t)dest << 32)); @@ -126,13 +126,13 @@ static __inline void apic_icr_write(u32 low, u32 dest) } } =20 -static __inline bool apic_isr_read(uint8_t vector) +static inline bool apic_isr_read(uint8_t vector) { return (apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)) >> (vector & 0x1f)) & 1; } =20 -static __inline u32 get_apic_id(void) /* Get the physical APIC id */ +static inline u32 get_apic_id(void) { u32 id =3D apic_read(APIC_ID); return x2apic_enabled ? id : GET_xAPIC_ID(id); diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/= cpufreq.h index b0c860f0ec21..3456d4c95f98 100644 --- a/xen/include/acpi/cpufreq/cpufreq.h +++ b/xen/include/acpi/cpufreq/cpufreq.h @@ -148,7 +148,7 @@ extern int cpufreq_driver_getavg(unsigned int cpu, unsi= gned int flag); extern int cpufreq_update_turbo(int cpuid, int new_state); extern int cpufreq_get_turbo_status(int cpuid); =20 -static __inline__ int=20 +static inline int __cpufreq_governor(struct cpufreq_policy *policy, unsigned int event) { return policy->governor->governor(policy, event); @@ -179,7 +179,7 @@ extern struct cpufreq_driver cpufreq_driver; =20 int cpufreq_register_driver(const struct cpufreq_driver *); =20 -static __inline__ +static inline void cpufreq_verify_within_limits(struct cpufreq_policy *policy, unsigned int min, unsigned int max) { diff --git a/xen/include/xen/bitops.h b/xen/include/xen/bitops.h index edd6817d5356..a88d45475c40 100644 --- a/xen/include/xen/bitops.h +++ b/xen/include/xen/bitops.h @@ -127,7 +127,7 @@ static inline int generic_fls64(__u64 x) # endif #endif =20 -static __inline__ int get_bitmask_order(unsigned int count) +static inline int get_bitmask_order(unsigned int count) { int order; =20 @@ -135,7 +135,7 @@ static __inline__ int get_bitmask_order(unsigned int co= unt) return order; /* We could be slightly more clever with -1 here... */ } =20 -static __inline__ int get_count_order(unsigned int count) +static inline int get_count_order(unsigned int count) { int order; =20 diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compiler.h index 04b8bc18df0e..16d554f2a593 100644 --- a/xen/include/xen/compiler.h +++ b/xen/include/xen/compiler.h @@ -20,9 +20,8 @@ #define likely(x) __builtin_expect(!!(x),1) #define unlikely(x) __builtin_expect(!!(x),0) =20 -#define inline __inline__ -#define always_inline __inline__ __attribute__ ((__always_inline__)) -#define gnu_inline __inline__ __attribute__ ((__gnu_inline__)) +#define always_inline inline __attribute__((__always_inline__)) +#define gnu_inline inline __attribute__((__gnu_inline__)) #define noinline __attribute__((__noinline__)) =20 #define noreturn __attribute__((__noreturn__)) @@ -83,7 +82,7 @@ * inline functions not expanded inline get placed in .init.text. */ #include -#define __inline__ __inline__ __init +#define inline inline __init #endif =20 #define __attribute_pure__ __attribute__((__pure__)) --=20 2.30.2