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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v5 1/2] xen/arm32: head: Introduce enable_{boot,secondary}_cpu_mm() Date: Mon, 20 Nov 2023 14:48:58 +0000 Message-ID: <20231120144859.170965-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231120144859.170965-1-ayan.kumar.halder@amd.com> References: <20231120144859.170965-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026367:EE_|PH7PR12MB7258:EE_ X-MS-Office365-Filtering-Correlation-Id: 64c7e579-785f-478b-522f-08dbe9d7e259 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YRa1wklsbmrpKW043pvyjzCoXUq+7tvnrkDePI4U6NBDKqTSW4jZ2caJyZqPMWut023mHpiJVTyzBjuVzq6imaGC8FEeg788RKwRFvGuCISOB+lwx0NyycfH5XRkm8/FSreL2htSGIksgedHc5/HOgtmz+1xErBvsDNdpoJGdK/3DxGVXe0puJZaQSCL8FLE7LqpbxH7dCKHrFhemkv2O5+9Q/SrwTE6ffikU4B3uMpb+LCHTr1tJIl8zKblGRnoXKkxOb3A4VsehcZCo8M3IgzOywzOvlnSz+0rh2NRJbAMLbX56ivunIWdb081AvtrD+2mwLBFEAOyX5b8DQnu22lpBS+PjvQY78FyjhoH88W5irpYnWuVIRS9Ytqx9zLxSe9XH/LQUwr5rKYUwS8t/9bzKA2jEYpvYinCowTwHGA+rlnZEUyOFrzUjlv7zJZwc6Ie2BvVf86j5fRb7li+0DZ5gbiQvdzl8Rxgv90LCFo4Eowzg4KFB6JpVtGlnag2MJB1KR4oU1ccjlrQ/iRYnUxm57Xf34b2HukLLoPkYUlIPFZbsiJgNYlIbkB2vKAeV5AczruDHQUEbMtxR/nWHluETzssBLQpStC+J9zYMsFLQnrnkQoz2yk50IUAwuxLylqSUB8MH7J5NqsgMbep1q8hXvktarrqwkycXKwCZtFn1x5Ovce3Wa6KpXK/jqXsSkrywjahNa46W+wRzLzSXsuFhfEU/CPqyTbMaCOyPSMY9EB3hpJnqHJQkej4Qur/a9YgkW8Qv4z+WjpnZwWtyv3Co7CLIvDBDXpGM3we1dY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(346002)(396003)(39860400002)(136003)(230922051799003)(82310400011)(1800799012)(64100799003)(451199024)(186009)(36840700001)(46966006)(40470700004)(336012)(426003)(6666004)(2616005)(478600001)(1076003)(26005)(83380400001)(8936002)(40480700001)(82740400003)(6916009)(70206006)(54906003)(316002)(4326008)(70586007)(8676002)(81166007)(47076005)(36860700001)(356005)(5660300002)(2906002)(40460700003)(103116003)(86362001)(36756003)(41300700001)(21314003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Nov 2023 14:49:22.6552 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64c7e579-785f-478b-522f-08dbe9d7e259 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026367.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7258 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1700491800242100001 Content-Type: text/plain; charset="utf-8" All the MMU related functionality have been clubbed together in enable_boot_cpu_mm() for booting primary cpu and enable_secondary_cpu_mm() = for booting secondary cpus. This is done in preparation for moving the code related to MMU in MMU speci= fic file and in order to support non MMU cpus in future. This is based on d2f8df5b3ede ("xen/arm64: head.S: Introduce enable_{boot,s= econdary}_cpu_mm()"). Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from :- v1 - 1. Added a proper commit message. 2. Some style and other fixes suggested in v1.=20 v2 - 1. Updated the comment on top of enable_boot_cpu_mm() and enable_secondary_cpu_mm() ie mentioned the input and output registers. 2. Updated the comment inside enable_boot_cpu_mm(). v3 - 1. No changes. v4 - 1. Fixed a comment in enable_boot_cpu_mm()=20 xen/arch/arm/arm32/head.S | 102 ++++++++++++++++++++++++++++++-------- 1 file changed, 80 insertions(+), 22 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 3011fb34aa..52fbb180ef 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -201,13 +201,11 @@ past_zImage: =20 bl check_cpu_mode bl cpu_init - bl create_page_tables =20 - /* Address in the runtime mapping to jump to after the MMU is enab= led */ mov_w lr, primary_switched - b enable_mmu + b enable_boot_cpu_mm + primary_switched: - bl setup_fixmap #ifdef CONFIG_EARLY_PRINTK /* Use a virtual address to access the UART. */ mov_w r11, EARLY_UART_VIRTUAL_ADDRESS @@ -249,27 +247,11 @@ GLOBAL(init_secondary) #endif bl check_cpu_mode bl cpu_init - bl create_page_tables =20 - /* Address in the runtime mapping to jump to after the MMU is enab= led */ mov_w lr, secondary_switched - b enable_mmu -secondary_switched: - /* - * Non-boot CPUs need to move on to the proper pagetables, which w= ere - * setup in prepare_secondary_mm. - * - * XXX: This is not compliant with the Arm Arm. - */ - mov_w r4, init_ttbr /* VA of HTTBR value stashed by CPU 0= */ - ldrd r4, r5, [r4] /* Actual value */ - dsb - mcrr CP64(r4, r5, HTTBR) - dsb - isb - flush_xen_tlb_local r0 - pt_enforce_wxn r0 + b enable_secondary_cpu_mm =20 +secondary_switched: #ifdef CONFIG_EARLY_PRINTK /* Use a virtual address to access the UART. */ mov_w r11, EARLY_UART_VIRTUAL_ADDRESS @@ -692,6 +674,82 @@ ready_to_switch: mov pc, lr ENDPROC(switch_to_runtime_mapping) =20 +/* + * Enable mm (turn on the data cache and the MMU) for secondary CPUs. + * The function will return to the virtual address provided in LR (e.g. the + * runtime mapping). + * + * Inputs: + * r9 : paddr(start) + * r10: phys offset + * lr : Virtual address to return to. + * + * Output: + * r12: Was a temporary mapping created? + * + * Clobbers r0 - r6 + */ +enable_secondary_cpu_mm: + mov r6, lr + + bl create_page_tables + + /* Address in the runtime mapping to jump to after the MMU is enab= led */ + mov_w lr, 1f + b enable_mmu +1: + /* + * Non-boot CPUs need to move on to the proper pagetables, which w= ere + * setup in prepare_secondary_mm. + * + * XXX: This is not compliant with the Arm Arm. + */ + mov_w r4, init_ttbr /* VA of HTTBR value stashed by CPU 0= */ + ldrd r4, r5, [r4] /* Actual value */ + dsb + mcrr CP64(r4, r5, HTTBR) + dsb + isb + flush_xen_tlb_local r0 + pt_enforce_wxn r0 + + /* Return to the virtual address requested by the caller. */ + mov pc, r6 +ENDPROC(enable_secondary_cpu_mm) + +/* + * Enable mm (turn on the data cache and the MMU) for the boot CPU. + * The function will return to the virtual address provided in LR (e.g. the + * runtime mapping). + * + * Inputs: + * r9 : paddr(start) + * r10: phys offset + * lr : Virtual address to return to. + * + * Output: + * r12: Was a temporary mapping created? + * + * Clobbers r0 - r6 + */ +enable_boot_cpu_mm: + mov r6, lr + + bl create_page_tables + + /* Address in the runtime mapping to jump to after the MMU is enab= led */ + mov_w lr, 1f + b enable_mmu +1: + mov lr, r6 + + /* + * Prepare the fixmap. The function will return to the virtual add= ress + * requested by the caller. + */ + b setup_fixmap +ENDPROC(enable_boot_cpu_mm) + /* * Remove the 1:1 map from the page-tables. It is not easy to keep track * where the 1:1 map was mapped, so we will look for the top-level entry --=20 2.25.1