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Fri, 17 Nov 2023 01:48:12 -0800 (PST) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH 1/3] amd-vi: use the same IOMMU page table levels for PV and HVM Date: Fri, 17 Nov 2023 10:47:47 +0100 Message-ID: <20231117094749.81091-2-roger.pau@citrix.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231117094749.81091-1-roger.pau@citrix.com> References: <20231117094749.81091-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1700214511414100001 Using different page table levels for HVM or PV guest is not helpful, and is not inline with the IOMMU implementation used by the other architecture ven= dor (VT-d). Switch to uniformly use DEFAULT_DOMAIN_ADDRESS_WIDTH in order to set the AM= D-Vi page table levels. Note using the max RAM address for PV was bogus anyway, as there's no guara= ntee there can't be device MMIO or reserved regions past the maximum RAM region. Signed-off-by: Roger Pau Monn=C3=A9 Acked-by: Andrew Cooper , although... --- xen/drivers/passthrough/amd/pci_amd_iommu.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/xen/drivers/passthrough/amd/pci_amd_iommu.c b/xen/drivers/pass= through/amd/pci_amd_iommu.c index 6bc73dc21052..f9e749d74da2 100644 --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -359,21 +359,17 @@ int __read_mostly amd_iommu_min_paging_mode =3D 1; static int cf_check amd_iommu_domain_init(struct domain *d) { struct domain_iommu *hd =3D dom_iommu(d); + int pgmode =3D amd_iommu_get_paging_mode( + 1UL << (DEFAULT_DOMAIN_ADDRESS_WIDTH - PAGE_SHIFT)); + + if ( pgmode < 0 ) + return pgmode; =20 /* - * Choose the number of levels for the IOMMU page tables. - * - PV needs 3 or 4, depending on whether there is RAM (including hot= plug - * RAM) above the 512G boundary. - * - HVM could in principle use 3 or 4 depending on how much guest - * physical address space we give it, but this isn't known yet so us= e 4 - * unilaterally. - * - Unity maps may require an even higher number. + * Choose the number of levels for the IOMMU page tables, taking into + * account unity maps. */ - hd->arch.amd.paging_mode =3D max(amd_iommu_get_paging_mode( - is_hvm_domain(d) - ? 1UL << (DEFAULT_DOMAIN_ADDRESS_WIDTH - PAGE_SHIFT) - : get_upper_mfn_bound() + 1), - amd_iommu_min_paging_mode); + hd->arch.amd.paging_mode =3D max(pgmode, amd_iommu_min_paging_mode); =20 return 0; } --=20 2.42.0