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d="scan'208";a="126012812" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Alejandro Vallejo , "Stefano Stabellini" , Xenia Ragiadakou Subject: [PATCH v2 1/2] x86/ucode: Move vendor specifics back out of early_microcode_init() Date: Thu, 26 Oct 2023 21:55:38 +0100 Message-ID: <20231026205539.3261811-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20231026205539.3261811-1-andrew.cooper3@citrix.com> References: <20231026205539.3261811-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1698353783621100002 I know it was me who dropped microcode_init_{intel,amd}() in c/s dd5f07997f29 ("x86/ucode: Rationalise startup and family/model checks"), but times have moved on. We've gained new conditional support, and a wish to compile-time specialise Xen to single platform. (Re)introduce ucode_probe_{amd,intel}() and move the recent vendor specific additions back out. Encode the conditional support state in the NULL-ness = of hooks as it's already done on other paths. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Alejandro Vallejo CC: Stefano Stabellini CC: Xenia Ragiadakou v2: * Undo unintentinal operand inversion in early_microcode_init() --- xen/arch/x86/cpu/microcode/amd.c | 10 +++++++++- xen/arch/x86/cpu/microcode/core.c | 16 +++++----------- xen/arch/x86/cpu/microcode/intel.c | 12 ++++++++++-- xen/arch/x86/cpu/microcode/private.h | 16 ++++++++++------ 4 files changed, 34 insertions(+), 20 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/= amd.c index 75fc84e445ce..17e68697d5bf 100644 --- a/xen/arch/x86/cpu/microcode/amd.c +++ b/xen/arch/x86/cpu/microcode/amd.c @@ -434,9 +434,17 @@ static struct microcode_patch *cf_check cpu_request_mi= crocode( return patch; } =20 -const struct microcode_ops __initconst_cf_clobber amd_ucode_ops =3D { +static const struct microcode_ops __initconst_cf_clobber amd_ucode_ops =3D= { .cpu_request_microcode =3D cpu_request_microcode, .collect_cpu_info =3D collect_cpu_info, .apply_microcode =3D apply_microcode, .compare_patch =3D compare_patch, }; + +void __init ucode_probe_amd(struct microcode_ops *ops) +{ + if ( boot_cpu_data.x86 < 0x10 ) + return; + + *ops =3D amd_ucode_ops; +} diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode= /core.c index 65ebeb50deea..3fd1f516e042 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -847,25 +847,19 @@ int __init early_microcode_init(unsigned long *module= _map, { const struct cpuinfo_x86 *c =3D &boot_cpu_data; int rc =3D 0; - bool can_load =3D false; =20 switch ( c->x86_vendor ) { case X86_VENDOR_AMD: - if ( c->x86 >=3D 0x10 ) - { - ucode_ops =3D amd_ucode_ops; - can_load =3D true; - } + ucode_probe_amd(&ucode_ops); break; =20 case X86_VENDOR_INTEL: - ucode_ops =3D intel_ucode_ops; - can_load =3D intel_can_load_microcode(); + ucode_probe_intel(&ucode_ops); break; } =20 - if ( !ucode_ops.apply_microcode ) + if ( !ucode_ops.collect_cpu_info ) { printk(XENLOG_INFO "Microcode loading not available\n"); return -ENODEV; @@ -882,10 +876,10 @@ int __init early_microcode_init(unsigned long *module= _map, * * Take the hint in either case and ignore the microcode interface. */ - if ( this_cpu(cpu_sig).rev =3D=3D ~0 || !can_load ) + if ( !ucode_ops.apply_microcode || this_cpu(cpu_sig).rev =3D=3D ~0 ) { printk(XENLOG_INFO "Microcode loading disabled due to: %s\n", - can_load ? "rev =3D ~0" : "HW toggle"); + ucode_ops.apply_microcode ? "rev =3D ~0" : "HW toggle"); ucode_ops.apply_microcode =3D NULL; return -ENODEV; } diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcod= e/intel.c index 060c529a6e5d..96f34b336b21 100644 --- a/xen/arch/x86/cpu/microcode/intel.c +++ b/xen/arch/x86/cpu/microcode/intel.c @@ -385,7 +385,7 @@ static struct microcode_patch *cf_check cpu_request_mic= rocode( return patch; } =20 -bool __init intel_can_load_microcode(void) +static bool __init can_load_microcode(void) { uint64_t mcu_ctrl; =20 @@ -398,9 +398,17 @@ bool __init intel_can_load_microcode(void) return !(mcu_ctrl & MCU_CONTROL_DIS_MCU_LOAD); } =20 -const struct microcode_ops __initconst_cf_clobber intel_ucode_ops =3D { +static const struct microcode_ops __initconst_cf_clobber intel_ucode_ops = =3D { .cpu_request_microcode =3D cpu_request_microcode, .collect_cpu_info =3D collect_cpu_info, .apply_microcode =3D apply_microcode, .compare_patch =3D compare_patch, }; + +void __init ucode_probe_intel(struct microcode_ops *ops) +{ + *ops =3D intel_ucode_ops; + + if ( !can_load_microcode() ) + ops->apply_microcode =3D NULL; +} diff --git a/xen/arch/x86/cpu/microcode/private.h b/xen/arch/x86/cpu/microc= ode/private.h index d80787205a5e..b58611e908aa 100644 --- a/xen/arch/x86/cpu/microcode/private.h +++ b/xen/arch/x86/cpu/microcode/private.h @@ -60,13 +60,17 @@ struct microcode_ops { const struct microcode_patch *new, const struct microcode_patch *o= ld); }; =20 -/** - * Checks whether we can perform microcode updates on this Intel system +/* + * Microcode loading falls into one of 3 states. + * - No support at all + * - Read-only (locked by firmware, or we're virtualised) + * - Loading available * - * @return True iff the microcode update facilities are enabled + * These are encoded by (not) filling in ops->collect_cpu_info (i.e. no + * support available) and (not) ops->apply_microcode (i.e. read only). + * Otherwise, all hooks must be filled in. */ -bool intel_can_load_microcode(void); - -extern const struct microcode_ops amd_ucode_ops, intel_ucode_ops; +void ucode_probe_amd(struct microcode_ops *ops); +void ucode_probe_intel(struct microcode_ops *ops); =20 #endif /* ASM_X86_MICROCODE_PRIVATE_H */ --=20 2.30.2 From nobody Fri May 17 03:00:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1698353788; cv=none; d=zohomail.com; s=zohoarc; b=MQ/fhruyUJmBeHk23PLLlkJTY1G6LT11M1woqWI3Vk1djorhTfVQWNrR49X9uXAGRb8McRbFsJytTcql5RMkkebh3czW1WZZqkUIW21s/2lPyDzgZIsaBlMtiI4BAh1MivUIdm/GGKeOyo92/C+X9WBRL5qDgJZ7w54XY6fyQ8A= ARC-Message-Signature: i=1; a=rsa-sha256; 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d="scan'208";a="129566477" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Alejandro Vallejo , Stefano Stabellini , Xenia Ragiadakou Subject: [PATCH v2 2/2] x86/Kconfig: Introduce CONFIG_{AMD,INTEL} and conditionalise ucode Date: Thu, 26 Oct 2023 21:55:39 +0100 Message-ID: <20231026205539.3261811-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20231026205539.3261811-1-andrew.cooper3@citrix.com> References: <20231026205539.3261811-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1698353789552100001 We eventually want to be able to build a stripped down Xen for a single platform. Make a start with CONFIG_{AMD,INTEL} (hidden behind EXPERT, but available to randconfig), and adjust the microcode logic. No practical change. Signed-off-by: Andrew Cooper Acked-by: Roger Pau Monn=C3=A9 Acked-by: Stefano Stabellini --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Alejandro Vallejo CC: Stefano Stabellini CC: Xenia Ragiadakou I've intentionally ignored the other vendors for now. They can be put into Kconfig by whomever figures out the actual dependencies between their init routines. v2: * Tweak text --- xen/arch/x86/Kconfig | 2 ++ xen/arch/x86/Kconfig.cpu | 22 ++++++++++++++++++++++ xen/arch/x86/cpu/microcode/Makefile | 4 ++-- xen/arch/x86/cpu/microcode/private.h | 9 +++++++++ 4 files changed, 35 insertions(+), 2 deletions(-) create mode 100644 xen/arch/x86/Kconfig.cpu diff --git a/xen/arch/x86/Kconfig b/xen/arch/x86/Kconfig index eac77573bd75..d9eacdd7e0fa 100644 --- a/xen/arch/x86/Kconfig +++ b/xen/arch/x86/Kconfig @@ -49,6 +49,8 @@ config HAS_CC_CET_IBT =20 menu "Architecture Features" =20 +source "arch/x86/Kconfig.cpu" + source "arch/Kconfig" =20 config PV diff --git a/xen/arch/x86/Kconfig.cpu b/xen/arch/x86/Kconfig.cpu new file mode 100644 index 000000000000..3c5d88fdfd16 --- /dev/null +++ b/xen/arch/x86/Kconfig.cpu @@ -0,0 +1,22 @@ +menu "Supported CPU vendors" + visible if EXPERT + +config AMD + bool "AMD" + default y + help + Detection, tunings and quirks for AMD platforms. + + May be turned off in builds targetting other vendors. Otherwise, + must be enabled for Xen to work suitably on AMD platforms. + +config INTEL + bool "Intel" + default y + help + Detection, tunings and quirks for Intel platforms. + + May be turned off in builds targetting other vendors. Otherwise, + must be enabled for Xen to work suitably on Intel platforms. + +endmenu diff --git a/xen/arch/x86/cpu/microcode/Makefile b/xen/arch/x86/cpu/microco= de/Makefile index aae235245b06..30d600544f45 100644 --- a/xen/arch/x86/cpu/microcode/Makefile +++ b/xen/arch/x86/cpu/microcode/Makefile @@ -1,3 +1,3 @@ -obj-y +=3D amd.o +obj-$(CONFIG_AMD) +=3D amd.o obj-y +=3D core.o -obj-y +=3D intel.o +obj-$(CONFIG_INTEL) +=3D intel.o diff --git a/xen/arch/x86/cpu/microcode/private.h b/xen/arch/x86/cpu/microc= ode/private.h index b58611e908aa..da556fe5060a 100644 --- a/xen/arch/x86/cpu/microcode/private.h +++ b/xen/arch/x86/cpu/microcode/private.h @@ -70,7 +70,16 @@ struct microcode_ops { * support available) and (not) ops->apply_microcode (i.e. read only). * Otherwise, all hooks must be filled in. */ +#ifdef CONFIG_AMD void ucode_probe_amd(struct microcode_ops *ops); +#else +static inline void ucode_probe_amd(struct microcode_ops *ops) {} +#endif + +#ifdef CONFIG_INTEL void ucode_probe_intel(struct microcode_ops *ops); +#else +static inline void ucode_probe_intel(struct microcode_ops *ops) {} +#endif =20 #endif /* ASM_X86_MICROCODE_PRIVATE_H */ --=20 2.30.2