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d="scan'208";a="122825024" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Jinoh Kang Subject: [PATCH 1/7] x86/emul: ASSERT that X86EMUL_DONE doesn't escape to callers Date: Fri, 15 Sep 2023 21:36:22 +0100 Message-ID: <20230915203628.837732-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230915203628.837732-1-andrew.cooper3@citrix.com> References: <20230915203628.837732-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1694810229759100001 This property is far from clear. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Jinoh Kang v2: * New --- xen/arch/x86/x86_emulate/x86_emulate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emul= ate/x86_emulate.c index e88245eae9fb..94caec1d142c 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -8651,6 +8651,12 @@ int x86_emulate_wrapper( =20 rc =3D x86_emulate(ctxt, ops); =20 + /* + * X86EMUL_DONE is an internal signal in the emulator, and is not expe= cted + * to ever escape out to callers. + */ + ASSERT(rc !=3D X86EMUL_DONE); + /* * Most retire flags should only be set for successful instruction * emulation. --=20 2.30.2 From nobody Thu Dec 26 20:13:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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d="scan'208";a="125538999" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Jinoh Kang Subject: [PATCH 2/7] x86/emul: Fix and extend #DB trap handling Date: Fri, 15 Sep 2023 21:36:23 +0100 Message-ID: <20230915203628.837732-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230915203628.837732-1-andrew.cooper3@citrix.com> References: <20230915203628.837732-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1694810242964100003 Lots of this is very very broken, but we need to start somewhere. First, the bugfix. Hooks which use X86EMUL_DONE to skip the general emulat= ion still need to evaluate singlestep as part of completing the instruction. Defer the logic until X86EMUL_DONE has been converted to X86EMUL_OKAY. Second, the improvement. PENDING_DBG, INTERRUPTIBILITY and ACTIVITY are internal pipeline state which Intel exposed to software in the VMCS, and AMD exposed a subset of in the VMCB. Importantly, bits set in PENDING_DBG can survive across multiple instruction boundaries if e.g. delivery of #DB is delayed by a MovSS. For now, introduce a full pending_dbg field into the retire union. This ke= eps the sh_page_fault() and init_context() paths working but in due course the field will want to lose the "retire" infix. In addition, set singlestep into pending_dbg as appropriate. Leave the old singlestep bitfield in place until we can adjust the callers to the new scheme. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Jinoh Kang v2: * Only evaluate singlestep on X86EMUL_OKAY, but do so after X86EMUL_DONE h= as been adjusted to X86EMUL_OKAY. * Adjust comments in light of X86EMUL_DONE not getting back to callers. --- xen/arch/x86/x86_emulate/x86_emulate.c | 20 +++++++++++++------- xen/arch/x86/x86_emulate/x86_emulate.h | 14 +++++++++++--- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emul= ate/x86_emulate.c index 94caec1d142c..de7f99500e3f 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -8379,13 +8379,6 @@ x86_emulate( if ( !mode_64bit() ) _regs.r(ip) =3D (uint32_t)_regs.r(ip); =20 - /* Should a singlestep #DB be raised? */ - if ( rc =3D=3D X86EMUL_OKAY && singlestep && !ctxt->retire.mov_ss ) - { - ctxt->retire.singlestep =3D true; - ctxt->retire.sti =3D false; - } - if ( rc !=3D X86EMUL_DONE ) *ctxt->regs =3D _regs; else @@ -8394,6 +8387,19 @@ x86_emulate( rc =3D X86EMUL_OKAY; } =20 + /* Should a singlestep #DB be raised? */ + if ( rc =3D=3D X86EMUL_OKAY && singlestep ) + { + ctxt->retire.pending_dbg |=3D X86_DR6_BS; + + /* BROKEN - TODO, merge into pending_dbg. */ + if ( !ctxt->retire.mov_ss ) + { + ctxt->retire.singlestep =3D true; + ctxt->retire.sti =3D false; + } + } + ctxt->regs->eflags &=3D ~X86_EFLAGS_RF; =20 done: diff --git a/xen/arch/x86/x86_emulate/x86_emulate.h b/xen/arch/x86/x86_emul= ate/x86_emulate.h index 698750267a90..fbc023c37e34 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.h +++ b/xen/arch/x86/x86_emulate/x86_emulate.h @@ -588,15 +588,23 @@ struct x86_emulate_ctxt /* Canonical opcode (see below) (valid only on X86EMUL_OKAY). */ unsigned int opcode; =20 - /* Retirement state, set by the emulator (valid only on X86EMUL_OKAY).= */ + /* + * Retirement state, set by the emulator (valid only on X86EMUL_OKAY). + * + * TODO: all this state should be input/output from the VMCS PENDING_D= BG, + * INTERRUPTIBILITY and ACTIVITIY fields. + */ union { - uint8_t raw; + unsigned long raw; struct { + /* Accumulated %dr6 trap bits, positive polarity. */ + unsigned int pending_dbg; + bool hlt:1; /* Instruction HLTed. */ bool mov_ss:1; /* Instruction sets MOV-SS irq shadow. */ bool sti:1; /* Instruction sets STI irq shadow. */ bool unblock_nmi:1; /* Instruction clears NMI blocking. */ - bool singlestep:1; /* Singlestepping was active. */ + bool singlestep:1; /* Singlestepping was active. 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d="scan'208";a="121464506" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Jinoh Kang Subject: [PATCH 3/7] x86/pv: Fix the determiniation of whether to inject #DB Date: Fri, 15 Sep 2023 21:36:24 +0100 Message-ID: <20230915203628.837732-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230915203628.837732-1-andrew.cooper3@citrix.com> References: <20230915203628.837732-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1694810232511100001 We long ago fixed the emulator to not inject exceptions behind our back. Therefore, assert that that a PV event (including interrupts, because that would be buggy too) isn't pending, rather than skipping the #DB injection if one is. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Jinoh Kang v2: * Drop X86EMUL_DONE adjustment. --- xen/arch/x86/pv/emul-priv-op.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 142bc4818cb5..0d9f84f458ba 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -1358,14 +1358,17 @@ int pv_emulate_privileged_op(struct cpu_user_regs *= regs) switch ( rc ) { case X86EMUL_OKAY: + ASSERT(!curr->arch.pv.trap_bounce.flags); + if ( ctxt.ctxt.retire.singlestep ) ctxt.bpmatch |=3D DR_STEP; + if ( ctxt.bpmatch ) { curr->arch.dr6 |=3D ctxt.bpmatch | DR_STATUS_RESERVED_ONE; - if ( !(curr->arch.pv.trap_bounce.flags & TBF_EXCEPTION) ) - pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); + pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); } + /* fall through */ case X86EMUL_RETRY: return EXCRET_fault_fixed; --=20 2.30.2 From nobody Thu Dec 26 20:13:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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d="scan'208";a="121464505" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Jinoh Kang Subject: [PATCH 4/7] x86/pv: Drop priv_op_ctxt.bpmatch and use pending_dbg instead Date: Fri, 15 Sep 2023 21:36:25 +0100 Message-ID: <20230915203628.837732-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230915203628.837732-1-andrew.cooper3@citrix.com> References: <20230915203628.837732-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1694810232895100003 With a full pending_dbg field in x86_emulate_ctxt, use it rather than using= a local bpmatch field. This simplifies the X86EMUL_OKAY path as singlestep is already accumulated = by x86_emulate() when appropriate. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Jinoh Kang v2: * Tweak commit message to avoid referencing X86EMUL_DONE. --- xen/arch/x86/pv/emul-priv-op.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 0d9f84f458ba..2f73ed0682e1 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -34,7 +34,6 @@ struct priv_op_ctxt { unsigned long base, limit; } cs; char *io_emul_stub; - unsigned int bpmatch; }; =20 /* I/O emulation helpers. Use non-standard calling conventions. */ @@ -367,7 +366,8 @@ static int cf_check read_io( if ( !guest_io_okay(port, bytes, curr, ctxt->regs) ) return X86EMUL_UNHANDLEABLE; =20 - poc->bpmatch =3D check_guest_io_breakpoint(curr, port, bytes); + poc->ctxt.retire.pending_dbg |=3D + check_guest_io_breakpoint(curr, port, bytes); =20 if ( admin_io_okay(port, bytes, currd) ) { @@ -472,7 +472,8 @@ static int cf_check write_io( if ( !guest_io_okay(port, bytes, curr, ctxt->regs) ) return X86EMUL_UNHANDLEABLE; =20 - poc->bpmatch =3D check_guest_io_breakpoint(curr, port, bytes); + poc->ctxt.retire.pending_dbg |=3D + check_guest_io_breakpoint(curr, port, bytes); =20 if ( admin_io_okay(port, bytes, currd) ) { @@ -636,7 +637,8 @@ static int cf_check rep_ins( return X86EMUL_EXCEPTION; } =20 - poc->bpmatch =3D check_guest_io_breakpoint(curr, port, bytes_per_rep); + poc->ctxt.retire.pending_dbg |=3D + check_guest_io_breakpoint(curr, port, bytes_per_rep); =20 while ( *reps < goal ) { @@ -658,7 +660,7 @@ static int cf_check rep_ins( =20 ++*reps; =20 - if ( poc->bpmatch || hypercall_preempt_check() ) + if ( poc->ctxt.retire.pending_dbg || hypercall_preempt_check() ) break; =20 /* x86_emulate() clips the repetition count to ensure we don't wra= p. */ @@ -703,7 +705,8 @@ static int cf_check rep_outs( return X86EMUL_EXCEPTION; } =20 - poc->bpmatch =3D check_guest_io_breakpoint(curr, port, bytes_per_rep); + poc->ctxt.retire.pending_dbg |=3D + check_guest_io_breakpoint(curr, port, bytes_per_rep); =20 while ( *reps < goal ) { @@ -726,7 +729,7 @@ static int cf_check rep_outs( =20 ++*reps; =20 - if ( poc->bpmatch || hypercall_preempt_check() ) + if ( poc->ctxt.retire.pending_dbg || hypercall_preempt_check() ) break; =20 /* x86_emulate() clips the repetition count to ensure we don't wra= p. */ @@ -1360,12 +1363,9 @@ int pv_emulate_privileged_op(struct cpu_user_regs *r= egs) case X86EMUL_OKAY: ASSERT(!curr->arch.pv.trap_bounce.flags); =20 - if ( ctxt.ctxt.retire.singlestep ) - ctxt.bpmatch |=3D DR_STEP; - - if ( ctxt.bpmatch ) + if ( ctxt.ctxt.retire.pending_dbg ) { - curr->arch.dr6 |=3D ctxt.bpmatch | DR_STATUS_RESERVED_ONE; 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d="scan'208";a="125539000" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Jinoh Kang Subject: [PATCH 5/7] x86: Introduce x86_merge_dr6() Date: Fri, 15 Sep 2023 21:36:26 +0100 Message-ID: <20230915203628.837732-6-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230915203628.837732-1-andrew.cooper3@citrix.com> References: <20230915203628.837732-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1694810240928100001 The current logic used to update %dr6 when injecting #DB is buggy. The SDM/APM documention on %dr6 updates is far from ideal, but does at least make clear that it's non-trivial. The actual behaviour is to overwrite B{0..3} and accumulate all other bits. Introduce x86_merge_dr6() to perform the operaton properly. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Jinoh Kang v2: * Extend commit message --- xen/arch/x86/debug.c | 20 ++++++++++++++++++++ xen/arch/x86/include/asm/debugreg.h | 7 +++++++ xen/arch/x86/include/asm/x86-defns.h | 7 +++++++ 3 files changed, 34 insertions(+) diff --git a/xen/arch/x86/debug.c b/xen/arch/x86/debug.c index 127fe83021cd..bfcd83ea4d0b 100644 --- a/xen/arch/x86/debug.c +++ b/xen/arch/x86/debug.c @@ -3,6 +3,7 @@ * Copyright (C) 2023 XenServer. */ #include +#include =20 #include =20 @@ -28,6 +29,25 @@ unsigned int x86_adj_dr6_rsvd(const struct cpu_policy *p= , unsigned int dr6) return dr6; } =20 +unsigned int x86_merge_dr6(const struct cpu_policy *p, unsigned int dr6, + unsigned int new) +{ + /* Flip dr6 to have positive polarity. */ + dr6 ^=3D X86_DR6_DEFAULT; + + /* Sanity check that only known values are passed in. */ + ASSERT(!(dr6 & ~X86_DR6_KNOWN_MASK)); + ASSERT(!(new & ~X86_DR6_KNOWN_MASK)); + + /* Breakpoint matches are overridden. All other bits accumulate. */ + dr6 =3D (dr6 & ~X86_DR6_BP_MASK) | new; + + /* Flip dr6 back to having default polarity. */ + dr6 ^=3D X86_DR6_DEFAULT; + + return x86_adj_dr6_rsvd(p, dr6); +} + unsigned int x86_adj_dr7_rsvd(const struct cpu_policy *p, unsigned int dr7) { unsigned int zeros =3D X86_DR7_ZEROS; diff --git a/xen/arch/x86/include/asm/debugreg.h b/xen/arch/x86/include/asm= /debugreg.h index 39ba312b84ee..e98a9ce977fa 100644 --- a/xen/arch/x86/include/asm/debugreg.h +++ b/xen/arch/x86/include/asm/debugreg.h @@ -89,4 +89,11 @@ struct cpu_policy; unsigned int x86_adj_dr6_rsvd(const struct cpu_policy *p, unsigned int dr6= ); unsigned int x86_adj_dr7_rsvd(const struct cpu_policy *p, unsigned int dr7= ); =20 +/* + * Merge new bits into dr6. 'new' is always given in positive polarity, + * matching the Intel VMCS PENDING_DBG semantics. + */ +unsigned int x86_merge_dr6(const struct cpu_policy *p, unsigned int dr6, + unsigned int new); + #endif /* _X86_DEBUGREG_H */ diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/as= m/x86-defns.h index 5838631ef634..edfecc89bd08 100644 --- a/xen/arch/x86/include/asm/x86-defns.h +++ b/xen/arch/x86/include/asm/x86-defns.h @@ -116,6 +116,13 @@ #define X86_DR6_BT (_AC(1, UL) << 15) /* Task switch = */ #define X86_DR6_RTM (_AC(1, UL) << 16) /* #DB/#BP in RTM reg= ion (INV) */ =20 +#define X86_DR6_BP_MASK \ + (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3) + +#define X86_DR6_KNOWN_MASK \ + (X86_DR6_BP_MASK | X86_DR6_BLD | X86_DR6_BD | X86_DR6_BS | \ + X86_DR6_BT | X86_DR6_RTM) + #define X86_DR6_ZEROS _AC(0x00001000, UL) /* %dr6 bits forced t= o 0 */ #define X86_DR6_DEFAULT _AC(0xffff0ff0, UL) /* Default %dr6 value= */ =20 --=20 2.30.2 From nobody Thu Dec 26 20:13:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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d="scan'208";a="122825025" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Jinoh Kang Subject: [PATCH 6/7] x86: Extend x86_event with a pending_dbg field Date: Fri, 15 Sep 2023 21:36:27 +0100 Message-ID: <20230915203628.837732-7-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230915203628.837732-1-andrew.cooper3@citrix.com> References: <20230915203628.837732-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1694810229920100003 ... using the Intel VMCS PENDING_DBG semantics, and sharing storage with cr= 2. This requires working around anonymous union bugs in obsolete versions of G= CC, which in turn needs to drop unnecessary const qualifiers. Also introduce a pv_inject_DB() wrapper use this field nicely. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Jinoh Kang v2: * Split out of prior patch. --- xen/arch/x86/include/asm/domain.h | 18 ++++++++++++++++-- xen/arch/x86/include/asm/hvm/hvm.h | 3 ++- xen/arch/x86/x86_emulate/x86_emulate.h | 5 ++++- 3 files changed, 22 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/d= omain.h index c2d9fc333be5..fd1f306222be 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -729,15 +729,29 @@ static inline void pv_inject_hw_exception(unsigned in= t vector, int errcode) pv_inject_event(&event); } =20 +static inline void pv_inject_DB(unsigned long pending_dbg) +{ + struct x86_event event =3D { + .vector =3D X86_EXC_DB, + .type =3D X86_EVENTTYPE_HW_EXCEPTION, + .error_code =3D X86_EVENT_NO_EC, + }; + + event.pending_dbg =3D pending_dbg; + + pv_inject_event(&event); +} + static inline void pv_inject_page_fault(int errcode, unsigned long cr2) { - const struct x86_event event =3D { + struct x86_event event =3D { .vector =3D X86_EXC_PF, .type =3D X86_EVENTTYPE_HW_EXCEPTION, .error_code =3D errcode, - .cr2 =3D cr2, }; =20 + event.cr2 =3D cr2; + pv_inject_event(&event); } =20 diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/= hvm/hvm.h index 6d53713fc3a9..ea966f4429f9 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -532,9 +532,10 @@ static inline void hvm_inject_page_fault(int errcode, = unsigned long cr2) .vector =3D X86_EXC_PF, .type =3D X86_EVENTTYPE_HW_EXCEPTION, .error_code =3D errcode, - .cr2 =3D cr2, }; =20 + event.cr2 =3D cr2; + hvm_inject_event(&event); } =20 diff --git a/xen/arch/x86/x86_emulate/x86_emulate.h b/xen/arch/x86/x86_emul= ate/x86_emulate.h index fbc023c37e34..e567a9b635d9 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.h +++ b/xen/arch/x86/x86_emulate/x86_emulate.h @@ -78,7 +78,10 @@ struct x86_event { uint8_t type; /* X86_EVENTTYPE_* */ uint8_t insn_len; /* Instruction length */ int32_t error_code; /* X86_EVENT_NO_EC if n/a */ - unsigned long cr2; /* Only for X86_EXC_PF h/w exception */ + union { + unsigned long cr2; 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d="scan'208";a="125538997" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Jinoh Kang Subject: [PATCH 7/7] x86/pv: Rewrite %dr6 handling Date: Fri, 15 Sep 2023 21:36:28 +0100 Message-ID: <20230915203628.837732-8-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230915203628.837732-1-andrew.cooper3@citrix.com> References: <20230915203628.837732-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1694810246496100001 All #DB exceptions result in an update of %dr6, but this isn't handled properly by Xen for any guest type. Remove all ad-hoc dr6 handling, leaving it to pv_inject_event() in most cas= es and using the new x86_merge_dr6() helper. In do_debug(), swap the dr6 to pending_dbg in order to operate entirely with positive polarity. Among other things, this helps spot RTM/BLD in the diagnostic message. Drop the unconditional v->arch.dr6 adjustment. pv_inject_event() performs = the adjustment in the common case, but retain the prior behaviour if a debugger= is attached. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Jinoh Kang v2: * Split pieces out into an earlier patch. * Extend do_debug() to use pending_dbg entirely, rather than have the same variable used with different polarity at different times. --- xen/arch/x86/pv/emul-priv-op.c | 5 +---- xen/arch/x86/pv/emulate.c | 9 +++++++-- xen/arch/x86/pv/ro-page-fault.c | 4 ++-- xen/arch/x86/pv/traps.c | 17 +++++++++++++---- xen/arch/x86/traps.c | 23 +++++++++++------------ 5 files changed, 34 insertions(+), 24 deletions(-) diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 2f73ed0682e1..fe2011f28e34 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -1364,10 +1364,7 @@ int pv_emulate_privileged_op(struct cpu_user_regs *r= egs) ASSERT(!curr->arch.pv.trap_bounce.flags); =20 if ( ctxt.ctxt.retire.pending_dbg ) - { - curr->arch.dr6 |=3D ctxt.ctxt.retire.pending_dbg | DR_STATUS_R= ESERVED_ONE; - pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); - } + pv_inject_DB(ctxt.ctxt.retire.pending_dbg); =20 /* fall through */ case X86EMUL_RETRY: diff --git a/xen/arch/x86/pv/emulate.c b/xen/arch/x86/pv/emulate.c index e7a1c0a2cc4f..29425a0a00ec 100644 --- a/xen/arch/x86/pv/emulate.c +++ b/xen/arch/x86/pv/emulate.c @@ -71,10 +71,15 @@ void pv_emul_instruction_done(struct cpu_user_regs *reg= s, unsigned long rip) { regs->rip =3D rip; regs->eflags &=3D ~X86_EFLAGS_RF; + if ( regs->eflags & X86_EFLAGS_TF ) { - current->arch.dr6 |=3D DR_STEP | DR_STATUS_RESERVED_ONE; - pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); + /* + * TODO, this should generally use TF from the start of the + * instruction. It's only a latent bug for now, as this path isn't + * used for any instruction which modifies eflags. + */ + pv_inject_DB(X86_DR6_BS); } } =20 diff --git a/xen/arch/x86/pv/ro-page-fault.c b/xen/arch/x86/pv/ro-page-faul= t.c index cad28ef928ad..f6bb33556e72 100644 --- a/xen/arch/x86/pv/ro-page-fault.c +++ b/xen/arch/x86/pv/ro-page-fault.c @@ -389,8 +389,8 @@ int pv_ro_page_fault(unsigned long addr, struct cpu_use= r_regs *regs) =20 /* Fallthrough */ case X86EMUL_OKAY: - if ( ctxt.retire.singlestep ) - pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); + if ( ctxt.retire.pending_dbg ) + pv_inject_DB(ctxt.retire.pending_dbg); =20 /* Fallthrough */ case X86EMUL_RETRY: diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c index 74f333da7e1c..553b04bca956 100644 --- a/xen/arch/x86/pv/traps.c +++ b/xen/arch/x86/pv/traps.c @@ -13,6 +13,7 @@ #include =20 #include +#include #include #include #include @@ -50,9 +51,9 @@ void pv_inject_event(const struct x86_event *event) tb->cs =3D ti->cs; tb->eip =3D ti->address; =20 - if ( event->type =3D=3D X86_EVENTTYPE_HW_EXCEPTION && - vector =3D=3D X86_EXC_PF ) + switch ( vector | -(event->type =3D=3D X86_EVENTTYPE_SW_INTERRUPT) ) { + case X86_EXC_PF: curr->arch.pv.ctrlreg[2] =3D event->cr2; arch_set_cr2(curr, event->cr2); =20 @@ -62,9 +63,17 @@ void pv_inject_event(const struct x86_event *event) error_code |=3D PFEC_user_mode; =20 trace_pv_page_fault(event->cr2, error_code); - } - else + break; + + case X86_EXC_DB: + curr->arch.dr6 =3D x86_merge_dr6(curr->domain->arch.cpu_policy, + curr->arch.dr6, event->pending_dbg); + /* Fallthrough */ + + default: trace_pv_trap(vector, regs->rip, use_error_code, error_code); + break; + } =20 if ( use_error_code ) { diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index dead728ce329..447edc827b3a 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1887,11 +1887,11 @@ void do_device_not_available(struct cpu_user_regs *= regs) /* SAF-1-safe */ void do_debug(struct cpu_user_regs *regs) { - unsigned long dr6; + unsigned long pending_dbg; struct vcpu *v =3D current; =20 - /* Stash dr6 as early as possible. */ - dr6 =3D read_debugreg(6); + /* Stash dr6 as early as possible, operating with positive polarity. */ + pending_dbg =3D read_debugreg(6) ^ X86_DR6_DEFAULT; =20 /* * At the time of writing (March 2018), on the subject of %dr6: @@ -1963,13 +1963,13 @@ void do_debug(struct cpu_user_regs *regs) * If however we do, safety measures need to be enacted. Use a big * hammer and clear all debug settings. */ - if ( dr6 & (DR_TRAP3 | DR_TRAP2 | DR_TRAP1 | DR_TRAP0) ) + if ( pending_dbg & X86_DR6_BP_MASK ) { unsigned int bp, dr7 =3D read_debugreg(7); =20 for ( bp =3D 0; bp < 4; ++bp ) { - if ( (dr6 & (1u << bp)) && /* Breakpoint triggered? */ + if ( (pending_dbg & (1u << bp)) && /* Breakpoint triggered= ? */ (dr7 & (3u << (bp * DR_ENABLE_SIZE))) && /* Enabled? = */ ((dr7 & (3u << ((bp * DR_CONTROL_SIZE) + /* Insn? */ DR_CONTROL_SHIFT))) =3D=3D DR_RW_EXEC= UTE) ) @@ -1990,24 +1990,23 @@ void do_debug(struct cpu_user_regs *regs) * so ensure the message is ratelimited. */ gprintk(XENLOG_WARNING, - "Hit #DB in Xen context: %04x:%p [%ps], stk %04x:%p, dr6 %= lx\n", + "Hit #DB in Xen context: %04x:%p [%ps], stk %04x:%p, pendi= ng_dbg %lx\n", regs->cs, _p(regs->rip), _p(regs->rip), - regs->ss, _p(regs->rsp), dr6); + regs->ss, _p(regs->rsp), pending_dbg); =20 return; } =20 - /* Save debug status register where guest OS can peek at it */ - v->arch.dr6 |=3D (dr6 & ~X86_DR6_DEFAULT); - v->arch.dr6 &=3D (dr6 | ~X86_DR6_DEFAULT); - if ( guest_kernel_mode(v, regs) && v->domain->debugger_attached ) { + /* Save debug status register where gdbsx can peek at it */ + v->arch.dr6 =3D x86_merge_dr6(v->domain->arch.cpu_policy, + v->arch.dr6, pending_dbg); domain_pause_for_debugger(); return; } =20 - pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); + pv_inject_DB(pending_dbg); } =20 /* SAF-1-safe */ --=20 2.30.2