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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Gerd Hoffmann , "Michael S . Tsirkin" , Akihiko Odaki , Stefano Stabellini , Anthony PERARD , "Antonio Caggiano" , "Dr . David Alan Gilbert" , Robert Beckett , "Dmitry Osipenko" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , CC: , Gurchetan Singh , Albert Esteve , , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alyssa Ross , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Huang Rui Subject: [QEMU PATCH v5 10/13] virtio-gpu: Resource UUID Date: Fri, 15 Sep 2023 19:11:27 +0800 Message-ID: <20230915111130.24064-11-ray.huang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915111130.24064-1-ray.huang@amd.com> References: <20230915111130.24064-1-ray.huang@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017099:EE_|LV8PR12MB9406:EE_ X-MS-Office365-Filtering-Correlation-Id: 415fb7bd-8e7f-4477-9200-08dbb5dcc70e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TV7L0dSpc9+RG+zqytEuk2ScpZm3DXBUQonJ2iaXkpWuhczfNspy7BsdSUdRI4nnrMEPue6Xp3XSSG9eY1aL47xF2ZaEF/J1UhbxnLHDa+wx8cKqiYqs0521J50AkqQ3Dp/+OyDsEpkOLCeviCMBJJHk3Pj1ONYuv98//7F+EDRpGmdrsns9E4Onoa11GfAIKm/B9AACjN0UoFapPhDTSxor02GoPxNJhHzwm4oYcXFrEi8s0ikNunK2eGYlBbAFZIU94Hr2lGc14stTtbqLXGsjQRihBY92WJy3GFOgfh0zhiUuKN4nLUHv5baSoIC3iFoSvCvZ6gRyvMW06Rv4/smoGHirI8d7UkgokS8H0s8lAgtsmiPQuYFzkWKmP+hxCGYocN11swQkQpjrGvZSmcGLKqnO482Tf8MeyNM4Qvx9N71N0myB3aFY/mqbZj0jQ7Q5e8fsToBE8GE7W/xmPEvjJ3Qx2yzDYQd7ISGAX/VEY03HYZTc1PTFrnKc0t/guVUwuRxV1qXfGB2NVLJ/72yX4qlH6DCuzWgSj9fXxkdVIsrkkGJU9iVH3k8+LxC28JLxQAS7kE+Kh5XTK3XQcGOxhKv1pJvUrxat3QekymlfGj6sPSq/Vnh30b8aANrBrxILU1LoHssZOLoVCjQP+OmW/VnxHEMts/HoBEOEtLlSzrNHi/GgRKrUau9wefLUbwF6vxf1c+xwKlDFntSZB5kBz8kveMNAec8LmbiqBnuOxNWE9pVg0u90Qe1y+jnTAYaBnv3lOQu659nGNkBIZF6hBi4ddV8qmiqdxkyb+eY= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(346002)(39860400002)(136003)(396003)(376002)(186009)(451199024)(82310400011)(1800799009)(40470700004)(36840700001)(46966006)(83380400001)(70206006)(2906002)(6666004)(36756003)(7416002)(4326008)(54906003)(70586007)(8676002)(8936002)(40460700003)(41300700001)(5660300002)(86362001)(47076005)(81166007)(110136005)(2616005)(356005)(921005)(478600001)(7696005)(336012)(36860700001)(316002)(426003)(26005)(16526019)(82740400003)(1076003)(40480700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 11:13:23.9329 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 415fb7bd-8e7f-4477-9200-08dbb5dcc70e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017099.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9406 Received-SPF: softfail client-ip=2a01:111:f400:7eab::62c; envelope-from=Ray.Huang@amd.com; helo=NAM11-CO1-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1694776457252100002 Content-Type: text/plain; charset="utf-8" From: Antonio Caggiano Enable resource UUID feature and implement command resource assign UUID. This is done by introducing a hash table to map resource IDs to their UUIDs. Signed-off-by: Antonio Caggiano Signed-off-by: Huang Rui --- V4 -> V5: - Add virtio migration handling for uuid (Akihiko) - Adjust sequence to allocate gpu resource before virglrender resource creation (Akihiko) - Clean up (Akihiko) hw/display/trace-events | 1 + hw/display/virtio-gpu-base.c | 2 ++ hw/display/virtio-gpu-virgl.c | 21 ++++++++++++ hw/display/virtio-gpu.c | 58 ++++++++++++++++++++++++++++++++++ include/hw/virtio/virtio-gpu.h | 6 ++++ 5 files changed, 88 insertions(+) diff --git a/hw/display/trace-events b/hw/display/trace-events index 2336a0ca15..54d6894c59 100644 --- a/hw/display/trace-events +++ b/hw/display/trace-events @@ -41,6 +41,7 @@ virtio_gpu_cmd_res_create_blob(uint32_t res, uint64_t siz= e) "res 0x%x, size %" P virtio_gpu_cmd_res_unref(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_back_attach(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_back_detach(uint32_t res) "res 0x%x" +virtio_gpu_cmd_res_assign_uuid(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_xfer_toh_2d(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_xfer_toh_3d(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_xfer_fromh_3d(uint32_t res) "res 0x%x" diff --git a/hw/display/virtio-gpu-base.c b/hw/display/virtio-gpu-base.c index 4f2b0ba1f3..f44388715c 100644 --- a/hw/display/virtio-gpu-base.c +++ b/hw/display/virtio-gpu-base.c @@ -236,6 +236,8 @@ virtio_gpu_base_get_features(VirtIODevice *vdev, uint64= _t features, features |=3D (1 << VIRTIO_GPU_F_CONTEXT_INIT); } =20 + features |=3D (1 << VIRTIO_GPU_F_RESOURCE_UUID); + return features; } =20 diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index 563a6f2f58..8a017dbeb4 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -36,11 +36,20 @@ static void virgl_cmd_create_resource_2d(VirtIOGPU *g, { struct virtio_gpu_resource_create_2d c2d; struct virgl_renderer_resource_create_args args; + struct virtio_gpu_simple_resource *res; =20 VIRTIO_GPU_FILL_CMD(c2d); trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format, c2d.width, c2d.height); =20 + res =3D g_new0(struct virtio_gpu_simple_resource, 1); + if (!res) { + cmd->error =3D VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY; + return; + } + res->resource_id =3D c2d.resource_id; + QTAILQ_INSERT_HEAD(&g->reslist, res, next); + args.handle =3D c2d.resource_id; args.target =3D 2; args.format =3D c2d.format; @@ -60,11 +69,20 @@ static void virgl_cmd_create_resource_3d(VirtIOGPU *g, { struct virtio_gpu_resource_create_3d c3d; struct virgl_renderer_resource_create_args args; + struct virtio_gpu_simple_resource *res; =20 VIRTIO_GPU_FILL_CMD(c3d); trace_virtio_gpu_cmd_res_create_3d(c3d.resource_id, c3d.format, c3d.width, c3d.height, c3d.depth); =20 + res =3D g_new0(struct virtio_gpu_simple_resource, 1); + if (!res) { + cmd->error =3D VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY; + return; + } + res->resource_id =3D c3d.resource_id; + QTAILQ_INSERT_HEAD(&g->reslist, res, next); + args.handle =3D c3d.resource_id; args.target =3D c3d.target; args.format =3D c3d.format; @@ -682,6 +700,9 @@ void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, /* TODO add security */ virgl_cmd_ctx_detach_resource(g, cmd); break; + case VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID: + virtio_gpu_resource_assign_uuid(g, cmd); + break; case VIRTIO_GPU_CMD_GET_CAPSET_INFO: virgl_cmd_get_capset_info(g, cmd); break; diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c index cc4c1f81bb..44414c1c5e 100644 --- a/hw/display/virtio-gpu.c +++ b/hw/display/virtio-gpu.c @@ -966,6 +966,38 @@ virtio_gpu_resource_detach_backing(VirtIOGPU *g, virtio_gpu_cleanup_mapping(g, res); } =20 +void virtio_gpu_resource_assign_uuid(VirtIOGPU *g, + struct virtio_gpu_ctrl_command *cmd) +{ + struct virtio_gpu_simple_resource *res; + struct virtio_gpu_resource_assign_uuid assign; + struct virtio_gpu_resp_resource_uuid resp; + QemuUUID *uuid; + + VIRTIO_GPU_FILL_CMD(assign); + virtio_gpu_bswap_32(&assign, sizeof(assign)); + trace_virtio_gpu_cmd_res_assign_uuid(assign.resource_id); + + res =3D virtio_gpu_find_check_resource(g, assign.resource_id, false, _= _func__, &cmd->error); + if (!res) { + return; + } + + memset(&resp, 0, sizeof(resp)); + resp.hdr.type =3D VIRTIO_GPU_RESP_OK_RESOURCE_UUID; + + uuid =3D g_hash_table_lookup(g->resource_uuids, GUINT_TO_POINTER(assig= n.resource_id)); + if (!uuid) { + uuid =3D g_new(QemuUUID, 1); + qemu_uuid_generate(uuid); + g_hash_table_insert(g->resource_uuids, GUINT_TO_POINTER(assign.res= ource_id), uuid); + res->has_uuid =3D true; + } + + memcpy(resp.uuid, uuid, sizeof(QemuUUID)); + virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp)); +} + void virtio_gpu_simple_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd) { @@ -1014,6 +1046,9 @@ void virtio_gpu_simple_process_cmd(VirtIOGPU *g, case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING: virtio_gpu_resource_detach_backing(g, cmd); break; + case VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID: + virtio_gpu_resource_assign_uuid(g, cmd); + break; default: cmd->error =3D VIRTIO_GPU_RESP_ERR_UNSPEC; break; @@ -1208,6 +1243,7 @@ static int virtio_gpu_save(QEMUFile *f, void *opaque,= size_t size, VirtIOGPU *g =3D opaque; struct virtio_gpu_simple_resource *res; int i; + QemuUUID *uuid; =20 /* in 2d mode we should never find unprocessed commands here */ assert(QTAILQ_EMPTY(&g->cmdq)); @@ -1224,9 +1260,17 @@ static int virtio_gpu_save(QEMUFile *f, void *opaque= , size_t size, } qemu_put_buffer(f, (void *)pixman_image_get_data(res->image), pixman_image_get_stride(res->image) * res->height); + + qemu_put_byte(f, res->has_uuid); + if (res->has_uuid) { + uuid =3D g_hash_table_lookup(g->resource_uuids, GUINT_TO_POINT= ER(res->resource_id)); + qemu_put_buffer(f, (void *)uuid, sizeof(QemuUUID)); + } } qemu_put_be32(f, 0); /* end of list */ =20 + g_hash_table_destroy(g->resource_uuids); + return vmstate_save_state(f, &vmstate_virtio_gpu_scanouts, g, NULL); } =20 @@ -1239,9 +1283,12 @@ static int virtio_gpu_load(QEMUFile *f, void *opaque= , size_t size, uint32_t resource_id, pformat; void *bits =3D NULL; int i; + QemuUUID *uuid =3D NULL; =20 g->hostmem =3D 0; =20 + g->resource_uuids =3D g_hash_table_new_full(NULL, NULL, NULL, g_free); + resource_id =3D qemu_get_be32(f); while (resource_id !=3D 0) { res =3D virtio_gpu_find_resource(g, resource_id); @@ -1292,6 +1339,12 @@ static int virtio_gpu_load(QEMUFile *f, void *opaque= , size_t size, qemu_get_buffer(f, (void *)pixman_image_get_data(res->image), pixman_image_get_stride(res->image) * res->height); =20 + res->has_uuid =3D qemu_get_byte(f); + if (res->has_uuid) { + qemu_get_buffer(f, (void *)uuid, sizeof(QemuUUID)); + g_hash_table_insert(g->resource_uuids, GUINT_TO_POINTER(res->r= esource_id), uuid); + } + /* restore mapping */ for (i =3D 0; i < res->iov_cnt; i++) { hwaddr len =3D res->iov[i].iov_len; @@ -1393,12 +1446,15 @@ void virtio_gpu_device_realize(DeviceState *qdev, E= rror **errp) QTAILQ_INIT(&g->reslist); QTAILQ_INIT(&g->cmdq); QTAILQ_INIT(&g->fenceq); + + g->resource_uuids =3D g_hash_table_new_full(NULL, NULL, NULL, g_free); } =20 static void virtio_gpu_device_unrealize(DeviceState *qdev) { VirtIOGPU *g =3D VIRTIO_GPU(qdev); =20 + g_hash_table_destroy(g->resource_uuids); g_clear_pointer(&g->ctrl_bh, qemu_bh_delete); g_clear_pointer(&g->cursor_bh, qemu_bh_delete); g_clear_pointer(&g->reset_bh, qemu_bh_delete); @@ -1452,6 +1508,8 @@ void virtio_gpu_reset(VirtIODevice *vdev) g_free(cmd); } =20 + g_hash_table_remove_all(g->resource_uuids); + virtio_gpu_base_reset(VIRTIO_GPU_BASE(vdev)); } =20 diff --git a/include/hw/virtio/virtio-gpu.h b/include/hw/virtio/virtio-gpu.h index b9adc28071..67b39fccec 100644 --- a/include/hw/virtio/virtio-gpu.h +++ b/include/hw/virtio/virtio-gpu.h @@ -63,6 +63,8 @@ struct virtio_gpu_simple_resource { MemoryRegion *region; #endif =20 + bool has_uuid; + QTAILQ_ENTRY(virtio_gpu_simple_resource) next; }; =20 @@ -208,6 +210,8 @@ struct VirtIOGPU { QTAILQ_HEAD(, VGPUDMABuf) bufs; VGPUDMABuf *primary[VIRTIO_GPU_MAX_SCANOUTS]; } dmabuf; + + GHashTable *resource_uuids; }; =20 struct VirtIOGPUClass { @@ -285,6 +289,8 @@ void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g, struct iovec *iov, uint32_t count); void virtio_gpu_cleanup_mapping(VirtIOGPU *g, struct virtio_gpu_simple_resource *res); +void virtio_gpu_resource_assign_uuid(VirtIOGPU *g, + struct virtio_gpu_ctrl_command *cmd); void virtio_gpu_process_cmdq(VirtIOGPU *g); void virtio_gpu_device_realize(DeviceState *qdev, Error **errp); void virtio_gpu_reset(VirtIODevice *vdev); --=20 2.34.1