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The motivation for exposing HWCR.TscFreqSel was to avoid warning messages f= rom Linux. It has been agreed that Linux should be changed instead to not complaint about missing HWCR.TscFreqSel when running virtualized. The relation between HWCR.TscFreqSel and PSTATE0 is not clearly written dow= n in the PPR, but it's natural for OSes to attempt to fetch the P0 frequency if = the TSC is stated to increment at the P0 frequency. Exposing PSTATEn (PSTATE0 at least) with all zeroes is not a suitable solut= ion because the PstateEn bit is read-write, and OSes could legitimately attempt= to set PstateEn=3D1 which Xen couldn't handle. Furthermore, the TscFreqSel bit is model specific and was never safe to exp= ose like this in the first place.=C2=A0 At a minimum it should have had a tools= tack adjustment to know not to migrate such a VM. Therefore, simply remove the bit.=C2=A0 Note the HWCR itself is an architec= tural register, and does need to be accessible by the guest. Since HWCR contains both architectural and non-architectural bits, going forward care must be t= aken to assert the exposed value is correct on newer CPU families. Reported-by: Sol=C3=A8ne Rapenne Link: https://github.com/QubesOS/qubes-issues/issues/8502 Fixes: 14b95b3b8546 ('x86/AMD: expose HWCR.TscFreqSel to guests') Signed-off-by: Roger Pau Monn=C3=A9 Reviewed-by: Andrew Cooper --- Changes since v2: - Adjust commit message. --- xen/arch/x86/msr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 3f0450259cdf..c33dc78cd8f6 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -240,8 +240,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) case MSR_K8_HWCR: if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) goto gp_fault; - *val =3D get_cpu_family(cp->basic.raw_fms, NULL, NULL) >=3D 0x10 - ? K8_HWCR_TSC_FREQ_SEL : 0; + *val =3D 0; break; =20 case MSR_VIRT_SPEC_CTRL: --=20 2.42.0