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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Andrew Cooper , George Dunlap , "Jan Beulich" , Julien Grall , "Stefano Stabellini" , Wei Liu Subject: [PATCH v7 1/2] xen/vpci: header: status register handler Date: Wed, 13 Sep 2023 10:35:46 -0400 Message-ID: <20230913143550.14565-2-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230913143550.14565-1-stewart.hildebrand@amd.com> References: <20230913143550.14565-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB73:EE_|SJ0PR12MB5453:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f605ac4-6fb6-474e-ee99-08dbb466e7d3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2023 14:37:07.0897 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f605ac4-6fb6-474e-ee99-08dbb466e7d3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5453 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1694615857182100001 Content-Type: text/plain; charset="utf-8" Introduce a handler for the PCI status register, with ability to mask the capabilities bit. The status register contains RsvdZ bits, read-only bits, = and write-1-to-clear bits, so introduce bitmasks to handle these in vPCI. If a = bit in the bitmask is set, then the special meaning applies: rsvdz_mask: read as zero, guest write ignore (write zero to hardware) ro_mask: read normal, guest write ignore (preserve on write to hardware) rw1c_mask: read normal, write 1 to clear The RsvdZ naming was borrowed from the PCI Express Base 4.0 specification. Xen preserves the value of read-only bits on write to hardware, discarding = the guests write value. The mask_cap_list flag will be set in a follow-on patch. Signed-off-by: Stewart Hildebrand Reviewed-by: Jan Beulich --- v6->v7: * re-work args passed to vpci_add_register_mask() (called in init_bars()) * also check for overlap of (rsvdz_mask & ro_mask) in add_register() * slightly adjust masking operation in vpci_write_helper() v5->v6: * remove duplicate PCI_STATUS_CAP_LIST in constant definition * style fixup in constant definitions * s/res_mask/rsvdz_mask/ * combine a new masking operation into single line * preserve r/o bits on write * get rid of status_read. Instead, use rsvdz_mask for conditionally masking PCI_STATUS_CAP_LIST bit * add comment about PCI_STATUS_CAP_LIST and rsvdp behavior * add sanity checks in add_register * move mask_cap_list from struct vpci_header to local variable v4->v5: * add support for res_mask * add support for ro_mask (squash ro_mask patch) * add constants for reserved, read-only, and rw1c masks v3->v4: * move mask_cap_list setting to the capabilities patch * single pci_conf_read16 in status_read * align mask_cap_list bitfield in struct vpci_header * change to rw1c bit mask instead of treating whole register as rw1c * drop subsystem prefix on renamed add_register function v2->v3: * new patch --- xen/drivers/vpci/header.c | 16 +++++++++++ xen/drivers/vpci/vpci.c | 55 +++++++++++++++++++++++++++++--------- xen/include/xen/pci_regs.h | 9 +++++++ xen/include/xen/vpci.h | 8 ++++++ 4 files changed, 76 insertions(+), 12 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 767c1ba718d7..af267b75ac31 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -521,6 +521,7 @@ static int cf_check init_bars(struct pci_dev *pdev) struct vpci_header *header =3D &pdev->vpci->header; struct vpci_bar *bars =3D header->bars; int rc; + bool mask_cap_list =3D false; =20 switch ( pci_conf_read8(pdev->sbdf, PCI_HEADER_TYPE) & 0x7f ) { @@ -544,6 +545,21 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; =20 + /* + * Utilize rsvdz_mask to hide PCI_STATUS_CAP_LIST from the guest for n= ow. If + * support for rsvdp (reserved & preserved) is added in the future, the + * rsvdp mask should be used instead. + */ + rc =3D vpci_add_register_mask(pdev->vpci, vpci_hw_read16, vpci_hw_writ= e16, + PCI_STATUS, 2, NULL, + PCI_STATUS_RSVDZ_MASK | + (mask_cap_list ? PCI_STATUS_CAP_LIST := 0), + PCI_STATUS_RO_MASK & + ~(mask_cap_list ? PCI_STATUS_CAP_LIST = : 0), + PCI_STATUS_RW1C_MASK); + if ( rc ) + return rc; + if ( pdev->ignore_bars ) return 0; =20 diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 3bec9a4153da..b4cde7db1b3f 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -29,6 +29,9 @@ struct vpci_register { unsigned int offset; void *private; struct list_head node; + uint32_t rsvdz_mask; + uint32_t ro_mask; + uint32_t rw1c_mask; }; =20 #ifdef __XEN__ @@ -145,9 +148,16 @@ uint32_t cf_check vpci_hw_read32( return pci_conf_read32(pdev->sbdf, reg); } =20 -int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, - vpci_write_t *write_handler, unsigned int offset, - unsigned int size, void *data) +void cf_check vpci_hw_write16( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) +{ + pci_conf_write16(pdev->sbdf, reg, val); +} + +static int add_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data, uint32_t rsvdz_mask, + uint32_t ro_mask, uint32_t rw1c_mask) { struct list_head *prev; struct vpci_register *r; @@ -155,7 +165,8 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t *r= ead_handler, /* Some sanity checks. */ if ( (size !=3D 1 && size !=3D 2 && size !=3D 4) || offset >=3D PCI_CFG_SPACE_EXP_SIZE || (offset & (size - 1)) || - (!read_handler && !write_handler) ) + (!read_handler && !write_handler) || (rsvdz_mask & ro_mask) || + (rsvdz_mask & rw1c_mask) || (ro_mask & rw1c_mask) ) return -EINVAL; =20 r =3D xmalloc(struct vpci_register); @@ -167,6 +178,9 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t *r= ead_handler, r->size =3D size; r->offset =3D offset; r->private =3D data; + r->rsvdz_mask =3D rsvdz_mask & (0xffffffffU >> (32 - 8 * size)); + r->ro_mask =3D ro_mask & (0xffffffffU >> (32 - 8 * size)); + r->rw1c_mask =3D rw1c_mask & (0xffffffffU >> (32 - 8 * size)); =20 spin_lock(&vpci->lock); =20 @@ -193,6 +207,23 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t *= read_handler, return 0; } =20 +int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data) +{ + return add_register(vpci, read_handler, write_handler, offset, size, d= ata, + 0, 0, 0); +} + +int vpci_add_register_mask(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offse= t, + unsigned int size, void *data, uint32_t rsvdz_m= ask, + uint32_t ro_mask, uint32_t rw1c_mask) +{ + return add_register(vpci, read_handler, write_handler, offset, size, d= ata, + rsvdz_mask, ro_mask, rw1c_mask); +} + int vpci_remove_register(struct vpci *vpci, unsigned int offset, unsigned int size) { @@ -376,6 +407,7 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, u= nsigned int size) } =20 val =3D r->read(pdev, r->offset, r->private); + val &=3D ~r->rsvdz_mask; =20 /* Check if the read is in the middle of a register. */ if ( r->offset < emu.offset ) @@ -407,26 +439,25 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg,= unsigned int size) =20 /* * Perform a maybe partial write to a register. - * - * Note that this will only work for simple registers, if Xen needs to - * trap accesses to rw1c registers (like the status PCI header register) - * the logic in vpci_write will have to be expanded in order to correctly - * deal with them. */ static void vpci_write_helper(const struct pci_dev *pdev, const struct vpci_register *r, unsigned int = size, unsigned int offset, uint32_t data) { + uint32_t val =3D 0; + ASSERT(size <=3D r->size); =20 - if ( size !=3D r->size ) + if ( (size !=3D r->size) || r->ro_mask ) { - uint32_t val; - val =3D r->read(pdev, r->offset, r->private); + val &=3D ~r->rw1c_mask; data =3D merge_result(val, data, size, offset); } =20 + data &=3D ~(r->rsvdz_mask | r->ro_mask); + data |=3D val & r->ro_mask; + r->write(pdev, r->offset, data & (0xffffffffU >> (32 - 8 * r->size)), r->private); } diff --git a/xen/include/xen/pci_regs.h b/xen/include/xen/pci_regs.h index 84b18736a85d..b72131729db6 100644 --- a/xen/include/xen/pci_regs.h +++ b/xen/include/xen/pci_regs.h @@ -66,6 +66,15 @@ #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ +#define PCI_STATUS_RSVDZ_MASK 0x0006 + +#define PCI_STATUS_RO_MASK (PCI_STATUS_IMM_READY | PCI_STATUS_INTERRUPT |= \ + PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ | PCI_STATUS_UDF | \ + PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) +#define PCI_STATUS_RW1C_MASK (PCI_STATUS_PARITY | \ + PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_REC_TARGET_ABORT | \ + PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_SIG_SYSTEM_ERROR | \ + PCI_STATUS_DETECTED_PARITY) =20 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision = */ #define PCI_REVISION_ID 0x08 /* Revision ID */ diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 0b8a2a3c745b..7a5cca29e54c 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -37,6 +37,12 @@ int __must_check vpci_add_register(struct vpci *vpci, vpci_write_t *write_handler, unsigned int offset, unsigned int size, void *data); +int __must_check vpci_add_register_mask(struct vpci *vpci, + vpci_read_t *read_handler, + vpci_write_t *write_handler, + unsigned int offset, unsigned int = size, + void *data, uint32_t rsvdz_mask, + uint32_t ro_mask, uint32_t rw1c_ma= sk); int __must_check vpci_remove_register(struct vpci *vpci, unsigned int offs= et, unsigned int size); =20 @@ -50,6 +56,8 @@ uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read32( const struct pci_dev *pdev, unsigned int reg, void *data); +void cf_check vpci_hw_write16( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data= ); =20 /* * Check for pending vPCI operations on this vcpu. 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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Andrew Cooper , George Dunlap , "Jan Beulich" , Julien Grall , "Stefano Stabellini" , Wei Liu , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v7 2/2] xen/vpci: header: filter PCI capabilities Date: Wed, 13 Sep 2023 10:35:47 -0400 Message-ID: <20230913143550.14565-3-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230913143550.14565-1-stewart.hildebrand@amd.com> References: <20230913143550.14565-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC1:EE_|DS0PR12MB6462:EE_ X-MS-Office365-Filtering-Correlation-Id: 62e4bd03-0863-4e68-c1bf-08dbb466f63c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2023 14:37:31.2960 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62e4bd03-0863-4e68-c1bf-08dbb466f63c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6462 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1694615878088100001 Content-Type: text/plain; charset="utf-8" Currently, Xen vPCI only supports virtualizing the MSI and MSI-X capabiliti= es. Hide all other PCI capabilities (including extended capabilities) from domU= s for now, even though there may be certain devices/drivers that depend on being = able to discover certain capabilities. We parse the physical PCI capabilities linked list and add vPCI register handlers for the next elements, inserting our own next value, thus presenti= ng a modified linked list to the domU. Introduce helper functions vpci_hw_read8 and vpci_read_val. The vpci_read_v= al helper function returns a fixed value, which may be used for RAZ registers,= or registers whose value doesn't change. Introduce pci_find_next_cap_ttl() helper while adapting the logic from pci_find_next_cap() to suit our needs, and implement the existing pci_find_next_cap() in terms of the new helper. Signed-off-by: Stewart Hildebrand Reviewed-by: Jan Beulich --- v6->v7: * no change v5->v6: * add register handlers before status register handler in init_bars() * s/header->mask_cap_list/mask_cap_list/ v4->v5: * use more appropriate types, continued * get rid of unnecessary hook function * add Jan's R-b v3->v4: * move mask_cap_list setting to this patch * leave pci_find_next_cap signature alone * use more appropriate types v2->v3: * get rid of > 0 in loop condition * implement pci_find_next_cap in terms of new pci_find_next_cap_ttl functio= n so that hypothetical future callers wouldn't be required to pass &ttl. * change NULL to (void *)0 for RAZ value passed to vpci_read_val * change type of ttl to unsigned int * remember to mask off the low 2 bits of next in the initial loop iteration * change return type of pci_find_next_cap and pci_find_next_cap_ttl * avoid wrapping the PCI_STATUS_CAP_LIST condition by using ! instead of = =3D=3D 0 v1->v2: * change type of ttl to int * use switch statement instead of if/else * adapt existing pci_find_next_cap helper instead of rolling our own * pass ttl as in/out * "pass through" the lower 2 bits of the next pointer * squash helper functions into this patch to avoid transient dead code situ= ation * extended capabilities RAZ/WI --- xen/drivers/pci/pci.c | 26 +++++++++----- xen/drivers/vpci/header.c | 76 +++++++++++++++++++++++++++++++++++++++ xen/drivers/vpci/vpci.c | 12 +++++++ xen/include/xen/pci.h | 3 ++ xen/include/xen/vpci.h | 5 +++ 5 files changed, 113 insertions(+), 9 deletions(-) diff --git a/xen/drivers/pci/pci.c b/xen/drivers/pci/pci.c index 3569ccb24e9e..8799d60c2156 100644 --- a/xen/drivers/pci/pci.c +++ b/xen/drivers/pci/pci.c @@ -39,31 +39,39 @@ unsigned int pci_find_cap_offset(pci_sbdf_t sbdf, unsig= ned int cap) return 0; } =20 -unsigned int pci_find_next_cap(pci_sbdf_t sbdf, unsigned int pos, - unsigned int cap) +unsigned int pci_find_next_cap_ttl(pci_sbdf_t sbdf, unsigned int pos, + bool (*is_match)(unsigned int), + unsigned int cap, unsigned int *ttl) { - u8 id; - int ttl =3D 48; + unsigned int id; =20 - while ( ttl-- ) + while ( (*ttl)-- ) { pos =3D pci_conf_read8(sbdf, pos); if ( pos < 0x40 ) break; =20 - pos &=3D ~3; - id =3D pci_conf_read8(sbdf, pos + PCI_CAP_LIST_ID); + id =3D pci_conf_read8(sbdf, (pos & ~3) + PCI_CAP_LIST_ID); =20 if ( id =3D=3D 0xff ) break; - if ( id =3D=3D cap ) + if ( (is_match && is_match(id)) || (!is_match && id =3D=3D cap) ) return pos; =20 - pos +=3D PCI_CAP_LIST_NEXT; + pos =3D (pos & ~3) + PCI_CAP_LIST_NEXT; } + return 0; } =20 +unsigned int pci_find_next_cap(pci_sbdf_t sbdf, unsigned int pos, + unsigned int cap) +{ + unsigned int ttl =3D 48; + + return pci_find_next_cap_ttl(sbdf, pos, NULL, cap, &ttl) & ~3; +} + /** * pci_find_ext_capability - Find an extended capability * @sbdf: PCI device to query diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index af267b75ac31..1e7dfe668ccf 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -513,6 +513,18 @@ static void cf_check rom_write( rom->addr =3D val & PCI_ROM_ADDRESS_MASK; } =20 +static bool cf_check vpci_cap_supported(unsigned int id) +{ + switch ( id ) + { + case PCI_CAP_ID_MSI: + case PCI_CAP_ID_MSIX: + return true; + default: + return false; + } +} + static int cf_check init_bars(struct pci_dev *pdev) { uint16_t cmd; @@ -545,6 +557,70 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; =20 + if ( !is_hardware_domain(pdev->domain) ) + { + if ( !(pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LI= ST) ) + { + /* RAZ/WI */ + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, (void *)0); + if ( rc ) + return rc; + } + else + { + /* Only expose capabilities to the guest that vPCI can handle.= */ + unsigned int next, ttl =3D 48; + + next =3D pci_find_next_cap_ttl(pdev->sbdf, PCI_CAPABILITY_LIST, + vpci_cap_supported, 0, &ttl); + + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &=3D ~3; + + if ( !next ) + /* + * If we don't have any supported capabilities to expose t= o the + * guest, mask the PCI_STATUS_CAP_LIST bit in the status + * register. + */ + mask_cap_list =3D true; + + while ( next && ttl ) + { + unsigned int pos =3D next; + + next =3D pci_find_next_cap_ttl(pdev->sbdf, + pos + PCI_CAP_LIST_NEXT, + vpci_cap_supported, 0, &ttl); + + rc =3D vpci_add_register(pdev->vpci, vpci_hw_read8, NULL, + pos + PCI_CAP_LIST_ID, 1, NULL); + if ( rc ) + return rc; + + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + pos + PCI_CAP_LIST_NEXT, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &=3D ~3; + } + } + + /* Extended capabilities RAZ/WI */ + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, 0x100, 4, + (void *)0); + if ( rc ) + return rc; + } + /* * Utilize rsvdz_mask to hide PCI_STATUS_CAP_LIST from the guest for n= ow. If * support for rsvdp (reserved & preserved) is added in the future, the diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index b4cde7db1b3f..e3b866aaf7a4 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -136,6 +136,18 @@ static void cf_check vpci_ignored_write( { } =20 +uint32_t cf_check vpci_read_val( + const struct pci_dev *pdev, unsigned int reg, void *data) +{ + return (uintptr_t)data; +} + +uint32_t cf_check vpci_hw_read8( + const struct pci_dev *pdev, unsigned int reg, void *data) +{ + return pci_conf_read8(pdev->sbdf, reg); +} + uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data) { diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index 251b8761a8e9..db927eeaeef2 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -194,6 +194,9 @@ int pci_mmcfg_read(unsigned int seg, unsigned int bus, int pci_mmcfg_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value); unsigned int pci_find_cap_offset(pci_sbdf_t sbdf, unsigned int cap); +unsigned int pci_find_next_cap_ttl(pci_sbdf_t sbdf, unsigned int pos, + bool (*is_match)(unsigned int), + unsigned int cap, unsigned int *ttl); unsigned int pci_find_next_cap(pci_sbdf_t sbdf, unsigned int pos, unsigned int cap); unsigned int pci_find_ext_capability(pci_sbdf_t sbdf, unsigned int cap); diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 7a5cca29e54c..b79efc49bad6 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -51,7 +51,12 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, un= signed int size); void vpci_write(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, uint32_t data); =20 +uint32_t cf_check vpci_read_val( + const struct pci_dev *pdev, unsigned int reg, void *data); + /* Passthrough handlers. */ +uint32_t cf_check vpci_hw_read8( + const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read32( --=20 2.42.0