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The reasoning for exposing HWCR.TscFreqSel was to avoid Linux from printing= a (bogus) warning message, but doing so at the cost of OpenBSD not booting is= not a suitable solution. In order to fix expose an empty HWCR. Fixes: 14b95b3b8546 ('x86/AMD: expose HWCR.TscFreqSel to guests') Signed-off-by: Roger Pau Monn=C3=A9 --- Not sure whether we want to expose something when is_cpufreq_controller() is true, seeing as there's a special wrmsr handler for the same MSR in that ca= se. Likely should be done for PV only, but also likely quite bogus. Missing reported by as the issue came from the QubesOS tracker. --- xen/arch/x86/msr.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 3f0450259cdf..964d500ff8a1 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -240,8 +240,12 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t= *val) case MSR_K8_HWCR: if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) goto gp_fault; - *val =3D get_cpu_family(cp->basic.raw_fms, NULL, NULL) >=3D 0x10 - ? K8_HWCR_TSC_FREQ_SEL : 0; + /* + * OpenBSD 7.3 accesses HWCR unconditionally if the TSC is reporte= d as + * Invariant. Do not set TSC_FREQ_SEL as that would trigger OpenB= SD to + * also poke at PSTATE0. + */ + *val =3D 0; break; =20 case MSR_VIRT_SPEC_CTRL: --=20 2.42.0