From nobody Sun May 19 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1694225931; cv=pass; d=zohomail.com; s=zohoarc; b=eN6wTajpoVp8gZEMrMnhxrjneMmbJMwqsOp2xir2lKs7x5/nOPaNd7pF/o2aaPS9tmkqLTnGQKgZy2cY6T2vBw4fFPbZjR+ZiqOiO94yP/sLt/Wq6U/J7dwEOkZ95O+8eeUKhqzvgIWD/hJY2UXlItTU3CquL2dAXy1ZUIL9gnM= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694225931; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RjGm0180x9ZTq619vf/+c98/7pcXUYOoX80SRHhD/4c=; b=N4BLBmlZNgO5ENaOlRGfvjMKiHBZhwjg9b/RYKZVuIC7Jmz0Gmx41rUbHGN9072MD5xLlP3qsKO6uPt4wF4CSy+zXi+6iQebsdYfGXxgLpC8vGkqu3QIxVytXA6Mjid5tJAj7YMQMHFfgEQZWtLd5W/ifI/om40FXT9cCz5Srnk= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1694225931781677.2708833242799; Fri, 8 Sep 2023 19:18:51 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.598342.933074 (Exim 4.92) (envelope-from ) id 1qenYE-0003EP-5N; Sat, 09 Sep 2023 02:18:22 +0000 Received: by outflank-mailman (output) from mailman id 598342.933074; Sat, 09 Sep 2023 02:18:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qenYE-0003EI-2g; Sat, 09 Sep 2023 02:18:22 +0000 Received: by outflank-mailman (input) for mailman id 598342; Sat, 09 Sep 2023 02:18:21 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qenYD-0002vo-03 for xen-devel@lists.xenproject.org; Sat, 09 Sep 2023 02:18:21 +0000 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on20602.outbound.protection.outlook.com [2a01:111:f400:7e8c::602]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 248f71a8-4eb7-11ee-8783-cb3800f73035; Sat, 09 Sep 2023 04:18:19 +0200 (CEST) Received: from SA0PR13CA0005.namprd13.prod.outlook.com (2603:10b6:806:130::10) by DM4PR12MB6446.namprd12.prod.outlook.com (2603:10b6:8:be::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6745.34; Sat, 9 Sep 2023 02:18:13 +0000 Received: from SN1PEPF0002BA4D.namprd03.prod.outlook.com (2603:10b6:806:130:cafe::11) by SA0PR13CA0005.outlook.office365.com (2603:10b6:806:130::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6792.11 via Frontend Transport; Sat, 9 Sep 2023 02:18:13 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SN1PEPF0002BA4D.mail.protection.outlook.com (10.167.242.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6792.11 via Frontend Transport; Sat, 9 Sep 2023 02:18:12 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 8 Sep 2023 21:18:11 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 8 Sep 2023 21:18:11 -0500 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Fri, 8 Sep 2023 21:18:09 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 248f71a8-4eb7-11ee-8783-cb3800f73035 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jr4mkQ3VphiVOmd2Ew90MY3z7xDt/B+zoZpt3NgRHvbglhlKjUOZIoXP3LXxztraQyISDnlL1Sm83L19UjCkQURrkvcKWX5OjjKi0Nv53XCSTMOI6fuelSUxr0xtotmVDd41Tb3bXpoPF6/sUTmQCsKWz1A3Ukluf2pkGmvKDigaAhn8wf/fzPPx0T3w2GxKjjYbvT/dSS5JO0J2wQaD+hxSE4QoKnwgRCzhpFBAZeWllqBn4XwSgX/i9N9jkhFpflYaW6a8A9Y17llH96ZJcONVOtKC9i8J523TA232XTi5rIF5Rt12iFTxCCvevz6KdDhTVc+IXdhQ4llTmFHxJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=RjGm0180x9ZTq619vf/+c98/7pcXUYOoX80SRHhD/4c=; b=bDPr8pcuXpqnEc76NXZQgoOoY0O+lM0djg/6zQEij+IjwVtd+SGWI39ltKyaVT4/yL3KH4zblorKPdLCmUZ5DyqqnNkBoQjm9XFJHbGna0coeMNo2SzvK+4oG63yTsVv8TpgkgKAceRBJt3eiMeAFBVoZZX7x29wshOxgjBHNzCaUgG9CM28JJRtIGMSQhCgTXeD7xxxUnHwXTouADl1GNkQzcttakRAG6V8fdC/29CqsNvAN5yGcdbvMDEuxMoxcP4+pRwNJjQmTO0zZUKFCGyxD44lvhGTexW9iBcsKlb12AjgiXKTnyiwtarPgTvoNre/lOSPzHfjB8nGrj3G8g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RjGm0180x9ZTq619vf/+c98/7pcXUYOoX80SRHhD/4c=; b=yICR2VVVPamJX1ZbfUbpYuGvFs/mTF+ap1LRCxxpdcFwsjMKKv2RuRdOlRtsN3RhiomA1mstRqM2giytROSJNsgegkDDylzUCG8THv6zAJh4FjnuDg0S099G7/6ytMpq66hbth/vei1x+xMRoyiCQUdtdHfkXltW0ZUCMuMbaBg= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , George Dunlap , Julien Grall , Stefano Stabellini , Paul Durrant , Kevin Tian Subject: [PATCH v6 1/4] xen/pci: convert pci_find_*cap* to pci_sbdf_t Date: Fri, 8 Sep 2023 22:16:25 -0400 Message-ID: <20230909021647.558115-2-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230909021647.558115-1-stewart.hildebrand@amd.com> References: <20230909021647.558115-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4D:EE_|DM4PR12MB6446:EE_ X-MS-Office365-Filtering-Correlation-Id: d656cc31-9064-4a9f-71af-08dbb0db047c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZKGeNJnhabWqqMDnRMuFb4SLYb97RzRz29d3vdmxhMZACGjt3dQwgtwrX85+CQllogmTrB/VVVvEmLndKb1usOrI8ae5ZIsd0Qgx/owHgnnVFKS+H1KYduPaHGtJuTHn3TuAGowlQQrTCi8ja5n33xe91jBQaxpXC9jdACsrNoP00685EjBZYccsSNNJHIyfqoYF3aqeyQAycWuLOUC1jc7L2C7q/rXWi+HiNZh+67LcozpjHU4E2mnVlZjFRB+lj/MtB8jipLgx7WJ00sXSxyirO+3KJOsFnJ6jNYrwCFK9eiKbNuBm9LpcimNDRNCry7V1a1hZymMVovGGGg5qy9emJtvWAjpfEInrnpmEvmZ+EbCU9aem7lDFD6v1aCcAWWXSvGKh28U6Ib1uiYEb2l8JSJ9btqvoKKVWXj/41dYj31wSZmWXbZxW4H5RW8bM1xF2quZ7otVAvJY84Ukc1BH7ofZZWtJcFHSD5pCkBMPQhWK7d0LhFpVFPpuBykjBv3hfkOXhs8OkDmLPsI+xeofFDTT6q2TjEGndVWKqnMgL5WpUjhjviClxlGFXkXc7YlRra61IKmUfEbKr68N2JkB6K29U1sYhp2i3b4xjrI3QdPCtuhzr9ZP2GYdBaJFWrUAgGLjeIU9R7aI3fPhHuSpNEOOQs3MXcl38xU90FsHNge2xC8ipDO1yds9NVTGpKSagboLMkBfxJm+/odQEbihgQlYf+cpRkyG7kk0s7LeBA41ST4k5ad4aMztGNlD+U4RG0N6UcEt0AmDNxfzfiA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(39860400002)(396003)(346002)(136003)(1800799009)(186009)(451199024)(82310400011)(40470700004)(46966006)(36840700001)(70206006)(81166007)(356005)(4326008)(6666004)(41300700001)(86362001)(40460700003)(26005)(1076003)(36756003)(82740400003)(47076005)(40480700001)(36860700001)(2906002)(2616005)(426003)(6916009)(336012)(83380400001)(478600001)(8676002)(8936002)(30864003)(5660300002)(54906003)(7416002)(44832011)(70586007)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2023 02:18:12.2022 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d656cc31-9064-4a9f-71af-08dbb0db047c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6446 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1694225933917100001 Content-Type: text/plain; charset="utf-8" Convert pci_find_*cap* functions and call sites to pci_sbdf_t, and remove s= ome now unused local variables. Also change to more appropriate types on lines = that are already being modified as a result of the pci_sbdf_t conversion. Signed-off-by: Stewart Hildebrand Reviewed-by: Jan Beulich Reviewed-by: Roger Pau Monn=C3=A9 --- I built with EXTRA_CFLAGS_XEN_CORE=3D"-Wunused-but-set-variable" (and unfortunately -Wno-error=3Dunused-but-set-variable too) to identify locatio= ns of unneeded local variables as a result of the change to pci_sbdf_t. v5->v6: * no change v4->v5: * add Jan's R-b v3->v4: * use more appropriate types on lines that are being modified anyway * remove "no functional change" from commit description v2->v3: * new patch --- xen/arch/x86/msi.c | 40 ++++++---------------- xen/drivers/char/ehci-dbgp.c | 3 +- xen/drivers/passthrough/amd/iommu_detect.c | 2 +- xen/drivers/passthrough/ats.c | 4 +-- xen/drivers/passthrough/ats.h | 6 ++-- xen/drivers/passthrough/msi.c | 6 ++-- xen/drivers/passthrough/pci.c | 21 +++++------- xen/drivers/passthrough/vtd/quirks.c | 10 ++---- xen/drivers/passthrough/vtd/x86/ats.c | 3 +- xen/drivers/pci/pci.c | 32 +++++++++-------- xen/drivers/vpci/msi.c | 4 +-- xen/drivers/vpci/msix.c | 4 +-- xen/include/xen/pci.h | 11 +++--- 13 files changed, 58 insertions(+), 88 deletions(-) diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c index 41b82f3e87cb..8d4fd43b10a6 100644 --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -283,7 +283,7 @@ static void msi_set_enable(struct pci_dev *dev, int ena= ble) u8 slot =3D PCI_SLOT(dev->devfn); u8 func =3D PCI_FUNC(dev->devfn); =20 - pos =3D pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSI); + pos =3D pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSI); if ( pos ) __msi_set_enable(seg, bus, slot, func, pos, enable); } @@ -291,12 +291,9 @@ static void msi_set_enable(struct pci_dev *dev, int en= able) static void msix_set_enable(struct pci_dev *dev, int enable) { int pos; - u16 control, seg =3D dev->seg; - u8 bus =3D dev->bus; - u8 slot =3D PCI_SLOT(dev->devfn); - u8 func =3D PCI_FUNC(dev->devfn); + uint16_t control; =20 - pos =3D pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSIX); + pos =3D pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSIX); if ( pos ) { control =3D pci_conf_read16(dev->sbdf, msix_control_reg(pos)); @@ -603,13 +600,10 @@ static int msi_capability_init(struct pci_dev *dev, struct msi_desc *entry; int pos; unsigned int i, mpos; - u16 control, seg =3D dev->seg; - u8 bus =3D dev->bus; - u8 slot =3D PCI_SLOT(dev->devfn); - u8 func =3D PCI_FUNC(dev->devfn); + uint16_t control; =20 ASSERT(pcidevs_locked()); - pos =3D pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSI); + pos =3D pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSI); if ( !pos ) return -ENODEV; control =3D pci_conf_read16(dev->sbdf, msi_control_reg(pos)); @@ -680,8 +674,8 @@ static u64 read_pci_mem_bar(u16 seg, u8 bus, u8 slot, u= 8 func, u8 bir, int vf) { struct pci_dev *pdev =3D pci_get_pdev(NULL, PCI_SBDF(seg, bus, slot, func)= ); - unsigned int pos =3D pci_find_ext_capability(seg, bus, - PCI_DEVFN(slot, func), + unsigned int pos =3D pci_find_ext_capability(PCI_SBDF(seg, bus, sl= ot, + func), PCI_EXT_CAP_ID_SRIOV); uint16_t ctrl =3D pci_conf_read16(PCI_SBDF(seg, bus, slot, func), pos + PCI_SRIOV_CTRL); @@ -772,8 +766,7 @@ static int msix_capability_init(struct pci_dev *dev, u8 slot =3D PCI_SLOT(dev->devfn); u8 func =3D PCI_FUNC(dev->devfn); bool maskall =3D msix->host_maskall, zap_on_error =3D false; - unsigned int pos =3D pci_find_cap_offset(seg, bus, slot, func, - PCI_CAP_ID_MSIX); + unsigned int pos =3D pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSIX); =20 if ( !pos ) return -ENODEV; @@ -1097,12 +1090,7 @@ static void _pci_cleanup_msix(struct arch_msix *msix) static void __pci_disable_msix(struct msi_desc *entry) { struct pci_dev *dev =3D entry->dev; - u16 seg =3D dev->seg; - u8 bus =3D dev->bus; - u8 slot =3D PCI_SLOT(dev->devfn); - u8 func =3D PCI_FUNC(dev->devfn); - unsigned int pos =3D pci_find_cap_offset(seg, bus, slot, func, - PCI_CAP_ID_MSIX); + unsigned int pos =3D pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSIX); u16 control =3D pci_conf_read16(dev->sbdf, msix_control_reg(entry->msi_attrib.pos)); bool maskall =3D dev->msix->host_maskall; @@ -1206,8 +1194,7 @@ void pci_cleanup_msi(struct pci_dev *pdev) =20 int pci_reset_msix_state(struct pci_dev *pdev) { - unsigned int pos =3D pci_find_cap_offset(pdev->seg, pdev->bus, pdev->s= bdf.dev, - pdev->sbdf.fn, PCI_CAP_ID_MSIX); + unsigned int pos =3D pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSIX); =20 ASSERT(pos); /* @@ -1229,10 +1216,6 @@ int pci_reset_msix_state(struct pci_dev *pdev) int pci_msi_conf_write_intercept(struct pci_dev *pdev, unsigned int reg, unsigned int size, uint32_t *data) { - u16 seg =3D pdev->seg; - u8 bus =3D pdev->bus; - u8 slot =3D PCI_SLOT(pdev->devfn); - u8 func =3D PCI_FUNC(pdev->devfn); struct msi_desc *entry; unsigned int pos; =20 @@ -1240,8 +1223,7 @@ int pci_msi_conf_write_intercept(struct pci_dev *pdev= , unsigned int reg, { entry =3D find_msi_entry(pdev, -1, PCI_CAP_ID_MSIX); pos =3D entry ? entry->msi_attrib.pos - : pci_find_cap_offset(seg, bus, slot, func, - PCI_CAP_ID_MSIX); + : pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSIX); ASSERT(pos); =20 if ( reg >=3D pos && reg < msix_pba_offset_reg(pos) + 4 ) diff --git a/xen/drivers/char/ehci-dbgp.c b/xen/drivers/char/ehci-dbgp.c index 72be4d9cc970..00cbdd5454dd 100644 --- a/xen/drivers/char/ehci-dbgp.c +++ b/xen/drivers/char/ehci-dbgp.c @@ -687,7 +687,8 @@ static unsigned int __init __find_dbgp(u8 bus, u8 slot,= u8 func) if ( (class >> 8) !=3D PCI_CLASS_SERIAL_USB_EHCI ) return 0; =20 - return pci_find_cap_offset(0, bus, slot, func, PCI_CAP_ID_EHCI_DEBUG); + return pci_find_cap_offset(PCI_SBDF(0, bus, slot, func), + PCI_CAP_ID_EHCI_DEBUG); } =20 static unsigned int __init find_dbgp(struct ehci_dbgp *dbgp, diff --git a/xen/drivers/passthrough/amd/iommu_detect.c b/xen/drivers/passt= hrough/amd/iommu_detect.c index 2317fa6a7d8d..cede44e6518f 100644 --- a/xen/drivers/passthrough/amd/iommu_detect.c +++ b/xen/drivers/passthrough/amd/iommu_detect.c @@ -27,7 +27,7 @@ static int __init get_iommu_msi_capabilities( { int pos; =20 - pos =3D pci_find_cap_offset(seg, bus, dev, func, PCI_CAP_ID_MSI); + pos =3D pci_find_cap_offset(PCI_SBDF(seg, bus, dev, func), PCI_CAP_ID_= MSI); =20 if ( !pos ) return -ENODEV; diff --git a/xen/drivers/passthrough/ats.c b/xen/drivers/passthrough/ats.c index 253f5c2e1042..0da183d057c5 100644 --- a/xen/drivers/passthrough/ats.c +++ b/xen/drivers/passthrough/ats.c @@ -24,11 +24,9 @@ boolean_param("ats", ats_enabled); int enable_ats_device(struct pci_dev *pdev, struct list_head *ats_list) { u32 value; - u16 seg =3D pdev->seg; - u8 bus =3D pdev->bus, devfn =3D pdev->devfn; int pos; =20 - pos =3D pci_find_ext_capability(seg, bus, devfn, PCI_EXT_CAP_ID_ATS); + pos =3D pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_ATS); BUG_ON(!pos); =20 if ( iommu_verbose ) diff --git a/xen/drivers/passthrough/ats.h b/xen/drivers/passthrough/ats.h index baa5f6a6dc04..f5e1d254e0d3 100644 --- a/xen/drivers/passthrough/ats.h +++ b/xen/drivers/passthrough/ats.h @@ -32,7 +32,8 @@ static inline int pci_ats_enabled(int seg, int bus, int d= evfn) u32 value; int pos; =20 - pos =3D pci_find_ext_capability(seg, bus, devfn, PCI_EXT_CAP_ID_ATS); + pos =3D pci_find_ext_capability(PCI_SBDF(seg, bus, devfn), + PCI_EXT_CAP_ID_ATS); BUG_ON(!pos); =20 value =3D pci_conf_read16(PCI_SBDF(seg, bus, devfn), pos + ATS_REG_CTL= ); @@ -45,7 +46,8 @@ static inline int pci_ats_device(int seg, int bus, int de= vfn) if ( !ats_enabled ) return 0; =20 - return pci_find_ext_capability(seg, bus, devfn, PCI_EXT_CAP_ID_ATS); + return pci_find_ext_capability(PCI_SBDF(seg, bus, devfn), + PCI_EXT_CAP_ID_ATS); } =20 #endif /* _ATS_H_ */ diff --git a/xen/drivers/passthrough/msi.c b/xen/drivers/passthrough/msi.c index fb78e2ebe8a4..13d904692ef8 100644 --- a/xen/drivers/passthrough/msi.c +++ b/xen/drivers/passthrough/msi.c @@ -24,8 +24,7 @@ int pdev_msi_init(struct pci_dev *pdev) =20 INIT_LIST_HEAD(&pdev->msi_list); =20 - pos =3D pci_find_cap_offset(pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn= ), - PCI_FUNC(pdev->devfn), PCI_CAP_ID_MSI); + pos =3D pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSI); if ( pos ) { uint16_t ctrl =3D pci_conf_read16(pdev->sbdf, msi_control_reg(pos)= ); @@ -33,8 +32,7 @@ int pdev_msi_init(struct pci_dev *pdev) pdev->msi_maxvec =3D multi_msi_capable(ctrl); } =20 - pos =3D pci_find_cap_offset(pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn= ), - PCI_FUNC(pdev->devfn), PCI_CAP_ID_MSIX); + pos =3D pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSIX); if ( pos ) { struct arch_msix *msix =3D xzalloc(struct arch_msix); diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index ed1f689227fa..04d00c7c37df 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -361,8 +361,7 @@ static struct pci_dev *alloc_pdev(struct pci_seg *pseg,= u8 bus, u8 devfn) break; =20 case DEV_TYPE_PCIe_ENDPOINT: - pos =3D pci_find_cap_offset(pseg->nr, bus, PCI_SLOT(devfn), - PCI_FUNC(devfn), PCI_CAP_ID_EXP); + pos =3D pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_EXP); BUG_ON(!pos); cap =3D pci_conf_read16(pdev->sbdf, pos + PCI_EXP_DEVCAP); if ( cap & PCI_EXP_DEVCAP_PHANTOM ) @@ -565,13 +564,12 @@ struct pci_dev *pci_get_pdev(const struct domain *d, = pci_sbdf_t sbdf) static void pci_enable_acs(struct pci_dev *pdev) { int pos; - u16 cap, ctrl, seg =3D pdev->seg; - u8 bus =3D pdev->bus; + uint16_t cap, ctrl; =20 if ( !is_iommu_enabled(pdev->domain) ) return; =20 - pos =3D pci_find_ext_capability(seg, bus, pdev->devfn, PCI_EXT_CAP_ID_= ACS); + pos =3D pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_ACS); if (!pos) return; =20 @@ -704,7 +702,7 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn, =20 if ( !pdev->info.is_virtfn && !pdev->vf_rlen[0] ) { - unsigned int pos =3D pci_find_ext_capability(seg, bus, devfn, + unsigned int pos =3D pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_SRIOV); uint16_t ctrl =3D pci_conf_read16(pdev->sbdf, pos + PCI_SRIOV_CTRL= ); =20 @@ -916,7 +914,8 @@ enum pdev_type pdev_type(u16 seg, u8 bus, u8 devfn) { u16 class_device, creg; u8 d =3D PCI_SLOT(devfn), f =3D PCI_FUNC(devfn); - int pos =3D pci_find_cap_offset(seg, bus, d, f, PCI_CAP_ID_EXP); + unsigned int pos =3D pci_find_cap_offset(PCI_SBDF(seg, bus, devfn), + PCI_CAP_ID_EXP); =20 class_device =3D pci_conf_read16(PCI_SBDF(seg, bus, d, f), PCI_CLASS_D= EVICE); switch ( class_device ) @@ -1184,10 +1183,7 @@ static int hest_match_pci(const struct acpi_hest_aer= _common *p, static bool hest_match_type(const struct acpi_hest_header *hest_hdr, const struct pci_dev *pdev) { - unsigned int pos =3D pci_find_cap_offset(pdev->seg, pdev->bus, - PCI_SLOT(pdev->devfn), - PCI_FUNC(pdev->devfn), - PCI_CAP_ID_EXP); + unsigned int pos =3D pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_EXP); u8 pcie =3D MASK_EXTR(pci_conf_read16(pdev->sbdf, pos + PCI_EXP_FLAGS), PCI_EXP_FLAGS_TYPE); =20 @@ -1258,8 +1254,7 @@ bool pcie_aer_get_firmware_first(const struct pci_dev= *pdev) { struct aer_hest_parse_info info =3D { .pdev =3D pdev }; =20 - return pci_find_cap_offset(pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn), - PCI_FUNC(pdev->devfn), PCI_CAP_ID_EXP) && + return pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_EXP) && apei_hest_parse(aer_hest_parse, &info) >=3D 0 && info.firmware_first; } diff --git a/xen/drivers/passthrough/vtd/quirks.c b/xen/drivers/passthrough= /vtd/quirks.c index 5d706a539788..5a56565ea883 100644 --- a/xen/drivers/passthrough/vtd/quirks.c +++ b/xen/drivers/passthrough/vtd/quirks.c @@ -495,8 +495,6 @@ int me_wifi_quirk(struct domain *domain, uint8_t bus, u= int8_t devfn, =20 void pci_vtd_quirk(const struct pci_dev *pdev) { - int seg =3D pdev->seg; - int bus =3D pdev->bus; int pos; bool ff; u32 val, val2; @@ -532,12 +530,10 @@ void pci_vtd_quirk(const struct pci_dev *pdev) /* Sandybridge-EP (Romley) */ case 0x3c00: /* host bridge */ case 0x3c01 ... 0x3c0b: /* root ports */ - pos =3D pci_find_ext_capability(seg, bus, pdev->devfn, - PCI_EXT_CAP_ID_ERR); + pos =3D pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_ERR); if ( !pos ) { - pos =3D pci_find_ext_capability(seg, bus, pdev->devfn, - PCI_EXT_CAP_ID_VNDR); + pos =3D pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_VND= R); while ( pos ) { val =3D pci_conf_read32(pdev->sbdf, pos + PCI_VNDR_HEADER); @@ -546,7 +542,7 @@ void pci_vtd_quirk(const struct pci_dev *pdev) pos +=3D PCI_VNDR_HEADER; break; } - pos =3D pci_find_next_ext_capability(seg, bus, pdev->devfn= , pos, + pos =3D pci_find_next_ext_capability(pdev->sbdf, pos, PCI_EXT_CAP_ID_VNDR); } ff =3D 0; diff --git a/xen/drivers/passthrough/vtd/x86/ats.c b/xen/drivers/passthroug= h/vtd/x86/ats.c index 9de419775f90..1f5913bed9d2 100644 --- a/xen/drivers/passthrough/vtd/x86/ats.c +++ b/xen/drivers/passthrough/vtd/x86/ats.c @@ -57,8 +57,7 @@ int ats_device(const struct pci_dev *pdev, const struct a= cpi_drhd_unit *drhd) return 0; =20 ats_drhd =3D find_ats_dev_drhd(drhd->iommu); - pos =3D pci_find_ext_capability(pdev->seg, pdev->bus, pdev->devfn, - PCI_EXT_CAP_ID_ATS); + pos =3D pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_ATS); =20 if ( pos && (ats_drhd =3D=3D NULL) ) { diff --git a/xen/drivers/pci/pci.c b/xen/drivers/pci/pci.c index c73a8c4124af..3569ccb24e9e 100644 --- a/xen/drivers/pci/pci.c +++ b/xen/drivers/pci/pci.c @@ -8,25 +8,25 @@ #include #include =20 -int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 func, u8 cap) +unsigned int pci_find_cap_offset(pci_sbdf_t sbdf, unsigned int cap) { u8 id; int max_cap =3D 48; u8 pos =3D PCI_CAPABILITY_LIST; u16 status; =20 - status =3D pci_conf_read16(PCI_SBDF(seg, bus, dev, func), PCI_STATUS); + status =3D pci_conf_read16(sbdf, PCI_STATUS); if ( (status & PCI_STATUS_CAP_LIST) =3D=3D 0 ) return 0; =20 while ( max_cap-- ) { - pos =3D pci_conf_read8(PCI_SBDF(seg, bus, dev, func), pos); + pos =3D pci_conf_read8(sbdf, pos); if ( pos < 0x40 ) break; =20 pos &=3D ~3; - id =3D pci_conf_read8(PCI_SBDF(seg, bus, dev, func), pos + PCI_CAP= _LIST_ID); + id =3D pci_conf_read8(sbdf, pos + PCI_CAP_LIST_ID); =20 if ( id =3D=3D 0xff ) break; @@ -39,19 +39,20 @@ int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 fun= c, u8 cap) return 0; } =20 -int pci_find_next_cap(u16 seg, u8 bus, unsigned int devfn, u8 pos, int cap) +unsigned int pci_find_next_cap(pci_sbdf_t sbdf, unsigned int pos, + unsigned int cap) { u8 id; int ttl =3D 48; =20 while ( ttl-- ) { - pos =3D pci_conf_read8(PCI_SBDF(seg, bus, devfn), pos); + pos =3D pci_conf_read8(sbdf, pos); if ( pos < 0x40 ) break; =20 pos &=3D ~3; - id =3D pci_conf_read8(PCI_SBDF(seg, bus, devfn), pos + PCI_CAP_LIS= T_ID); + id =3D pci_conf_read8(sbdf, pos + PCI_CAP_LIST_ID); =20 if ( id =3D=3D 0xff ) break; @@ -65,21 +66,21 @@ int pci_find_next_cap(u16 seg, u8 bus, unsigned int dev= fn, u8 pos, int cap) =20 /** * pci_find_ext_capability - Find an extended capability - * @seg/@bus/@devfn: PCI device to query + * @sbdf: PCI device to query * @cap: capability code * * Returns the address of the requested extended capability structure * within the device's PCI configuration space or 0 if the device does * not support it. */ -int pci_find_ext_capability(int seg, int bus, int devfn, int cap) +unsigned int pci_find_ext_capability(pci_sbdf_t sbdf, unsigned int cap) { - return pci_find_next_ext_capability(seg, bus, devfn, 0, cap); + return pci_find_next_ext_capability(sbdf, 0, cap); } =20 /** * pci_find_next_ext_capability - Find another extended capability - * @seg/@bus/@devfn: PCI device to query + * @sbdf: PCI device to query * @start: starting position * @cap: capability code * @@ -87,13 +88,14 @@ int pci_find_ext_capability(int seg, int bus, int devfn= , int cap) * within the device's PCI configuration space or 0 if the device does * not support it. */ -int pci_find_next_ext_capability(int seg, int bus, int devfn, int start, i= nt cap) +unsigned int pci_find_next_ext_capability(pci_sbdf_t sbdf, unsigned int st= art, + unsigned int cap) { u32 header; int ttl =3D 480; /* 3840 bytes, minimum 8 bytes per capability */ - int pos =3D max(start, 0x100); + unsigned int pos =3D max(start, 0x100U); =20 - header =3D pci_conf_read32(PCI_SBDF(seg, bus, devfn), pos); + header =3D pci_conf_read32(sbdf, pos); =20 /* * If we have no capabilities, this is indicated by cap ID, @@ -109,7 +111,7 @@ int pci_find_next_ext_capability(int seg, int bus, int = devfn, int start, int cap pos =3D PCI_EXT_CAP_NEXT(header); if ( pos < 0x100 ) break; - header =3D pci_conf_read32(PCI_SBDF(seg, bus, devfn), pos); + header =3D pci_conf_read32(sbdf, pos); } return 0; } diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c index 2814b63d2be7..a253ccbd7db7 100644 --- a/xen/drivers/vpci/msi.c +++ b/xen/drivers/vpci/msi.c @@ -184,9 +184,7 @@ static void cf_check mask_write( =20 static int cf_check init_msi(struct pci_dev *pdev) { - uint8_t slot =3D PCI_SLOT(pdev->devfn), func =3D PCI_FUNC(pdev->devfn); - unsigned int pos =3D pci_find_cap_offset(pdev->seg, pdev->bus, slot, f= unc, - PCI_CAP_ID_MSI); + unsigned int pos =3D pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSI); uint16_t control; int ret; =20 diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index 1be861343dba..d1126a417da9 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -659,14 +659,12 @@ int vpci_make_msix_hole(const struct pci_dev *pdev) static int cf_check init_msix(struct pci_dev *pdev) { struct domain *d =3D pdev->domain; - uint8_t slot =3D PCI_SLOT(pdev->devfn), func =3D PCI_FUNC(pdev->devfn); unsigned int msix_offset, i, max_entries; uint16_t control; struct vpci_msix *msix; int rc; =20 - msix_offset =3D pci_find_cap_offset(pdev->seg, pdev->bus, slot, func, - PCI_CAP_ID_MSIX); + msix_offset =3D pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSIX); if ( !msix_offset ) return 0; =20 diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index 7d8a7cd21301..ea6a4c9abf38 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -193,11 +193,12 @@ int pci_mmcfg_read(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 *value); int pci_mmcfg_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value); -int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 func, u8 cap); -int pci_find_next_cap(u16 seg, u8 bus, unsigned int devfn, u8 pos, int cap= ); -int pci_find_ext_capability(int seg, int bus, int devfn, int cap); -int pci_find_next_ext_capability(int seg, int bus, int devfn, int start, - int cap); +unsigned int pci_find_cap_offset(pci_sbdf_t sbdf, unsigned int cap); +unsigned int pci_find_next_cap(pci_sbdf_t sbdf, unsigned int pos, + unsigned int cap); +unsigned int pci_find_ext_capability(pci_sbdf_t sbdf, unsigned int cap); +unsigned int pci_find_next_ext_capability(pci_sbdf_t sbdf, unsigned int st= art, + unsigned int cap); const char *parse_pci(const char *, unsigned int *seg, unsigned int *bus, unsigned int *dev, unsigned int *func); const char *parse_pci_seg(const char *, unsigned int *seg, unsigned int *b= us, --=20 2.42.0 From nobody Sun May 19 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1694225945; cv=pass; d=zohomail.com; s=zohoarc; b=I7NmsGFiHLaqyqKB82ORX4b75oAGjsyr652yav2jrhavQF36q7asWnq/t1YUHa6QHry9U64ClCnaeoo4IpRlZWj+Lr5d+rv7zLpapKAG4qb+6fNYziUUVyPXtTOZ+oys9ZiOn6dNcqcaKwQhhvtIkHhA4+2QJ7uxCKJHEMKyCPo= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694225945; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Nr7OL8yPNaL5TrLID4oNgMxCjNkIO8tK0RAkzMUQ/ac=; b=JxNK/CA/qxs76myZG1EOII3pixHiIQJti8ow7kcCYFEeYz4l8uTCsFBzDcGYiNhhy4uCi9PY5w4281ddj5ZYAHzgLGRivwMjU8byYtqOtfZYONO89ZrWz7mNQ0p3L9ZuKYZD6BP8fhp91+4Myy5cBOQbv1hPwkhBu15L+EKQXFU= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1694225945259630.9015829299354; Fri, 8 Sep 2023 19:19:05 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.598346.933083 (Exim 4.92) (envelope-from ) id 1qenYX-0003eQ-IB; Sat, 09 Sep 2023 02:18:41 +0000 Received: by outflank-mailman (output) from mailman id 598346.933083; Sat, 09 Sep 2023 02:18:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qenYX-0003eJ-F5; Sat, 09 Sep 2023 02:18:41 +0000 Received: by outflank-mailman (input) for mailman id 598346; Sat, 09 Sep 2023 02:18:40 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qenYW-0003dU-6I for xen-devel@lists.xenproject.org; Sat, 09 Sep 2023 02:18:40 +0000 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2061b.outbound.protection.outlook.com [2a01:111:f400:7e89::61b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 2ed67621-4eb7-11ee-9b0d-b553b5be7939; Sat, 09 Sep 2023 04:18:38 +0200 (CEST) Received: from CY5PR15CA0007.namprd15.prod.outlook.com (2603:10b6:930:14::13) by CH2PR12MB4890.namprd12.prod.outlook.com (2603:10b6:610:63::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6768.30; Sat, 9 Sep 2023 02:18:31 +0000 Received: from CY4PEPF0000E9D0.namprd03.prod.outlook.com (2603:10b6:930:14:cafe::46) by CY5PR15CA0007.outlook.office365.com (2603:10b6:930:14::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6745.39 via Frontend Transport; Sat, 9 Sep 2023 02:18:31 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D0.mail.protection.outlook.com (10.167.241.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6792.11 via Frontend Transport; Sat, 9 Sep 2023 02:18:30 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 8 Sep 2023 21:18:30 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 8 Sep 2023 21:18:29 -0500 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Fri, 8 Sep 2023 21:18:28 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2ed67621-4eb7-11ee-9b0d-b553b5be7939 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lFsKkighMrLYKs3awVxLXMjlziUJ+0nLECxdgQrA8LjK10IK1mkoAs5HxX7XL99OS40oPgAhWsQZIKpJhXMOODuj1lip9KQLVx4/gDzNF/fziHvvhE6xsMkN4zHENAhqtLRBni5FxmcJOmoyrAVwg4SwArjRvZl3GbRAgB0ufob8iZ/264NF7yvXPHA90khIo610v5nBOPIFDZcc8nmdTf9vDYQBdRA9uPA/bmaKnwEb9CQf3xg+1RNr+PVSHVXB263nrRlbR863lSO7AFHziTfO4SdxxqVc2RyMg/gr5Mqh89txjcyYarISzwDF7RTKR4jWgEv45QlHzjNfQvnFuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Nr7OL8yPNaL5TrLID4oNgMxCjNkIO8tK0RAkzMUQ/ac=; b=HdVpMWvgodgABd/IPikqFDH+sP9EEKJuaP3xmCMgfTwEEPAz4xhLGggjEzv3mmnkWC2AMhcnAjnpej/W1kP8ZZb5hb2aVzXa96I8GsJzF/1SJjcPrYYnHYX1Jhoh/Y1ejmAr8HO3+miRuQBh6eOh62+DzdX5h6v4D8LP9016LTt3pyPRiXKaSqdrxCyHrlNrHa7zIj/lzgMSqUrkpr9Nq8HB8P1lCOXEihgbiz7OUtKK4y1rFyFa9B4jqr0CKyOnw/ojl5xRToi216V2/y1iXGMR7/Z5LeMpSxp8Oq/au9cNEHT80I/wFiBcTsxsFvh5b64d8JynROKGTt+rZzsOYg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Nr7OL8yPNaL5TrLID4oNgMxCjNkIO8tK0RAkzMUQ/ac=; b=bNNpnWxm+Fr2/aNSjM+g5GEyjcTa/WfI+/akQxPbDEXuzM3C8jspYc4x5IAo86FMVJWsSaxEY4M+5D8B98ZvN7LQrjcp9F8Cdm9hLMh9Tw4mLCrlByC+h2ej36z86T4D6Mn6swTwkySy3urMJUA8u+So3PcLIM5s6NNghFtpA5E= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH v6 2/4] x86/msi: rearrange read_pci_mem_bar slightly Date: Fri, 8 Sep 2023 22:16:26 -0400 Message-ID: <20230909021647.558115-3-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230909021647.558115-1-stewart.hildebrand@amd.com> References: <20230909021647.558115-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D0:EE_|CH2PR12MB4890:EE_ X-MS-Office365-Filtering-Correlation-Id: c00409e2-2501-4d1f-87e8-08dbb0db0f7e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Hz30fb/QY26eYjOKPYE6QKUy641/gvXPkBKJ4W0YttMxCuB4xNkE00Ss3iTzvsTUuTFWfh/4L8v8wuZi+GdAUwBRE2f4Ny9VAoa5QrRVs0FwTE/WueIymmdAHc1TbdTqjnF1LdowEb6Ar2LljUiPUtGWEELmj6+pdh9ZbW3Fq5rsAZ9tbkIB0ud3fLUwIuwzI7x/RfccyGFovzMt3t8wVL7gtg83K/C8HDEJQlwOkkq+gLqAhgb3V6DknDHMOixGSqBrxC/bkKD7JTyxofmwnQl1DCxkpmX1rJsS2yVOCKASewixR+aRmDMtBS9RK4mGtwr5E4xbSMfTX3QAGLaHAgYowziBGNKzagFLAfrXQHpkMi48yQVtE1sVHQk4UQfeI5WwCAB2Z1+0M9BlsgT7LTjOu78UR38lI+9vSIRhFvZWOSQ22skEuqXZBH/oQyOC9jzHXl6xQo5vVOg8YSTINVkgxmcV/myye5uC1VSp0OdCXQxFZRJfliO7VDerm+HwzZQVsoc356qOa3tR3SaTGlsapBQz0gjNoWFY+cfs3uu6e+ln5HeCLMoyC/k07g+wjacncVa7K7/bXJDstqp4cV4Tut7lBXfmxNUQCPu4FFqHpAo6dG1SXNtNzxPSz/vC5NJ+SXFJXL8fWXrA9IMQH2RDXUx3z2lxabVpNwoKaJKPnDqYgCt98k1IdWxNMKvWwBOQzSLi7sn9nGre5efhiGh1KLKaIRntTBaZEg5pVab8nTere4ecbzy2eBkUj4fbiIq+gyB/Sm4s6bh4KYZVuw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(346002)(396003)(39860400002)(136003)(1800799009)(186009)(82310400011)(451199024)(36840700001)(46966006)(40470700004)(70206006)(44832011)(5660300002)(8936002)(8676002)(4326008)(41300700001)(316002)(70586007)(6916009)(54906003)(478600001)(2906002)(966005)(26005)(2616005)(426003)(336012)(1076003)(47076005)(36860700001)(83380400001)(81166007)(356005)(82740400003)(40460700003)(86362001)(36756003)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2023 02:18:30.6240 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c00409e2-2501-4d1f-87e8-08dbb0db0f7e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4890 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1694225946088100001 Content-Type: text/plain; charset="utf-8" Use pdev->sbdf instead of the PCI_SBDF macro in calls to pci_* functions where appropriate. Move NULL check earlier. Suggested-by: Jan Beulich Signed-off-by: Stewart Hildebrand Reviewed-by: Jan Beulich Suggested-by tag added based on conversation at [1] --- v5->v6: * no change v4->v5: * add Jan's R-b v3->v4: * new patch Suggested-by tag added based on conversation at [1] [1] https://lists.xenproject.org/archives/html/xen-devel/2023-08/msg01886.h= tml --- xen/arch/x86/msi.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c index 8d4fd43b10a6..a78367d7cf5d 100644 --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -674,19 +674,19 @@ static u64 read_pci_mem_bar(u16 seg, u8 bus, u8 slot,= u8 func, u8 bir, int vf) { struct pci_dev *pdev =3D pci_get_pdev(NULL, PCI_SBDF(seg, bus, slot, func)= ); - unsigned int pos =3D pci_find_ext_capability(PCI_SBDF(seg, bus, sl= ot, - func), - PCI_EXT_CAP_ID_SRIOV); - uint16_t ctrl =3D pci_conf_read16(PCI_SBDF(seg, bus, slot, func), - pos + PCI_SRIOV_CTRL); - uint16_t num_vf =3D pci_conf_read16(PCI_SBDF(seg, bus, slot, func), - pos + PCI_SRIOV_NUM_VF); - uint16_t offset =3D pci_conf_read16(PCI_SBDF(seg, bus, slot, func), - pos + PCI_SRIOV_VF_OFFSET); - uint16_t stride =3D pci_conf_read16(PCI_SBDF(seg, bus, slot, func), - pos + PCI_SRIOV_VF_STRIDE); - - if ( !pdev || !pos || + unsigned int pos; + uint16_t ctrl, num_vf, offset, stride; + + if ( !pdev ) + return 0; + + pos =3D pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_SRIOV); + ctrl =3D pci_conf_read16(pdev->sbdf, pos + PCI_SRIOV_CTRL); + num_vf =3D pci_conf_read16(pdev->sbdf, pos + PCI_SRIOV_NUM_VF); + offset =3D pci_conf_read16(pdev->sbdf, pos + PCI_SRIOV_VF_OFFSET); + stride =3D pci_conf_read16(pdev->sbdf, pos + PCI_SRIOV_VF_STRIDE); + + if ( !pos || !(ctrl & PCI_SRIOV_CTRL_VFE) || !(ctrl & PCI_SRIOV_CTRL_MSE) || !num_vf || !offset || (num_vf > 1 && !stride) || --=20 2.42.0 From nobody Sun May 19 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1694225986; cv=pass; d=zohomail.com; s=zohoarc; b=noF6xLIZYio1gZUW5+GxY3+kyaMX0/mYee7NPhXaUCtV4C6ONPkHUA4kl3Od1+Rp0SpEiID0xEkIEZ/6uzXoAKe8OEMkzUCS2/zRmfNnq7bUHPL/L2KvFcPkKBYz8NFQ+gEUSallREnm422bmPydD8c2EqtM05fO6O9DNuU6Rv4= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694225986; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sMCuF10qBS80uuE3Gw9n2rizrqn0mnEqVqquOunu4kU=; b=LRCRum8V/DsF9nrw0Dsbr8YyCu9Ibh2iIeUpaN5eOSCnsLSOMWRhKaEPwu1iNQf7vUn4Vlt+COTTJpgfkcnTrXmAYxukUK+gqR9ITE20JaDTeBnKn224vKbhZEsDpS6o+8xj7cUlHFMWHGP+mkJsnyL9PEoIyc9MmAGiTt+aHrU= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1694225986145740.3719585141364; Fri, 8 Sep 2023 19:19:46 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.598357.933094 (Exim 4.92) (envelope-from ) id 1qenZC-0004X0-Sb; Sat, 09 Sep 2023 02:19:22 +0000 Received: by outflank-mailman (output) from mailman id 598357.933094; Sat, 09 Sep 2023 02:19:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qenZC-0004Wt-O7; Sat, 09 Sep 2023 02:19:22 +0000 Received: by outflank-mailman (input) for mailman id 598357; Sat, 09 Sep 2023 02:19:22 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qenZC-0004WR-0j for xen-devel@lists.xenproject.org; Sat, 09 Sep 2023 02:19:22 +0000 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2061d.outbound.protection.outlook.com [2a01:111:f400:7e8c::61d]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 483775d2-4eb7-11ee-8783-cb3800f73035; Sat, 09 Sep 2023 04:19:20 +0200 (CEST) Received: from SN6PR16CA0038.namprd16.prod.outlook.com (2603:10b6:805:ca::15) by PH7PR12MB5806.namprd12.prod.outlook.com (2603:10b6:510:1d2::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6768.30; Sat, 9 Sep 2023 02:19:16 +0000 Received: from SN1PEPF0002BA50.namprd03.prod.outlook.com (2603:10b6:805:ca:cafe::4f) by SN6PR16CA0038.outlook.office365.com (2603:10b6:805:ca::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6768.31 via Frontend Transport; Sat, 9 Sep 2023 02:19:16 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SN1PEPF0002BA50.mail.protection.outlook.com (10.167.242.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6792.11 via Frontend Transport; Sat, 9 Sep 2023 02:19:15 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 8 Sep 2023 21:19:15 -0500 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Fri, 8 Sep 2023 21:19:13 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 483775d2-4eb7-11ee-8783-cb3800f73035 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QaU/lWH+gBe6XbortBLbrqmomZuDmki6FzuRrkai/JH397wBr2T8BEB+nmNBRn1hkmZLaFmlG/QijBWoQCuylOo3Dx4LU2AvUV4hECAgntnKc3MoN5IyG8fl7LHJCsc/uQPyY6N5BwFivfmAc/jJcGjfaH8cjBCFrs/oNSjfR07S48EyrXLBJ0FJhSHtkodBPwSTmrMvuz+/nWJMQZ7KXRK142wEgol7HXWX6BxEYYVDxL6cu26VQpo5ilh7vk8ULgJSwcQOjIdPsLt6UmqzTsPWhnwSTUa1KBBmlAIQh5a0rx/IBrUIddUQ6lX5GZ6QfnqSgNkrRd5unN6m5+/M+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sMCuF10qBS80uuE3Gw9n2rizrqn0mnEqVqquOunu4kU=; b=hlXJFaBv+CyATBWMUQbtE2cZHeTRKUZSsGg9LcMnTUp4+Fpcm2l7pPkLvRA57Vw03C5IhWD/FqgPE5mnfPTp/80/lG1m9UiGhtn3RdeRl0987fANc+FcJT02ES1KlIej4K/AekBEwK5nrMZsyPPtHTmD3UY+nmUByvXW2TB+b8nx/zWsGXkdWKD05N9HuetCH3ZEqf8zLp0r2Qdp4NcZkh+l+VxkeuNUmtlw+opWkIhgzS0w2NeBOriVOYooiUb63CBPdQZGXArsMZujRfk7XQMg6QjjGf58f3pfapZv8m1FuZJhnEtm72xBj1hHXvC9Pz3xm100cyy7UxwzdKxqvA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sMCuF10qBS80uuE3Gw9n2rizrqn0mnEqVqquOunu4kU=; b=cku6f6+zlQYDO5KscNBpY0E2WJ9yQIRI9TxBJXm10CVuyve2IqPimGlacGXR5fFmyUlSTWRFMf8rUpTjR69JvbGfQEQRuCEmVPTgqmHjr8Ww0RaCXixFmqHaUOR9oXVw7p8z566A37L1BQCMu0cEzZBGX31h39xccJnrr/T5jWE= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Andrew Cooper , George Dunlap , "Jan Beulich" , Julien Grall , "Stefano Stabellini" , Wei Liu Subject: [PATCH v6 3/4] xen/vpci: header: status register handler Date: Fri, 8 Sep 2023 22:16:27 -0400 Message-ID: <20230909021647.558115-4-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230909021647.558115-1-stewart.hildebrand@amd.com> References: <20230909021647.558115-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA50:EE_|PH7PR12MB5806:EE_ X-MS-Office365-Filtering-Correlation-Id: 60fdb78b-cd0d-41f9-53a6-08dbb0db2a5d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JT4aqjCbG2lJiE7LofRiBN9mMRB1S7hW/Z0/bR3GIN1Oa1rTe5JGFwuMzrHtCNVJP4Dmy39c6E3pXavhwrFnWscv68ptA/o5px9N7GoTNYW4/opcOJGe4dp6UG9FwRjBLVz6ISqVzueM3aHTY+VScN6EcbXITe5+y7d1cf6hw4fomt+906x77heLWoitS5UhSELG9n/47xN89096EzTs5L4GjhIBnZG4uGcs7bJH6o2MzoTfD6nZYjckgDTFbhwPqwlNPxL4Nl9ntSNgTaoOqFJ8UHx9l2zv23k3psRoo5CignGGFYfRUO/+n/vTG1ATY+jG+Hss9+o+1MBCwvwBL9zKUICCAKo1vwkIQ1+XL+MWhvIyHuwGqdLHlcXW/tbzKICwUhzh2CAgkwEWo/gZnNCm5XmgJ0Dvdf5tGvTEFPvovNOeAjbT87VhRItLN6nxHEtkS+UFUu+CzV7+VzPhB3yuNqNwffE6mpWKdS6UI1hvKjoYN8gAXiJ20YTXQACchMN+jkYfkxw9GMEynPRqA6Vd9J8HfiEf/2VtMD8XNBrE0wa/qY114Srrqcv+G0eiebTKaNLa4v6MKtwcaZsSdyFNQ1cc7X77kJMvuF6+USgtUx51WU1hrSrP+gmPHsyvIwrOg8BxBxPRoph1j6I/gjCFjhBevJ8q7Iq5LII3icKGira5VPLxqD9ha49UUxn3GVj9xls5Pit4K4kqN+Hmm4ZH0ZN5s2wiTXxtpFlWkM/6oqlOr0TBq1lZ+BS5TbitL2t/YTTQj2Xq7tSc9k1TTVYuinxLI2uQdUur4mqhOi0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(39860400002)(346002)(376002)(396003)(82310400011)(451199024)(1800799009)(186009)(40470700004)(36840700001)(46966006)(6666004)(83380400001)(26005)(478600001)(2616005)(426003)(336012)(1076003)(2906002)(54906003)(6916009)(44832011)(316002)(70206006)(5660300002)(8936002)(4326008)(40460700003)(8676002)(70586007)(41300700001)(36756003)(86362001)(47076005)(40480700001)(36860700001)(82740400003)(81166007)(356005)(66899024)(36900700001)(357404004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2023 02:19:15.7674 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60fdb78b-cd0d-41f9-53a6-08dbb0db2a5d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA50.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5806 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1694225987008100001 Content-Type: text/plain; charset="utf-8" Introduce a handler for the PCI status register, with ability to mask the capabilities bit. The status register contains RsvdZ bits, read-only bits, = and write-1-to-clear bits, so introduce bitmasks to handle these in vPCI. If a = bit in the bitmask is set, then the special meaning applies: rsvdz_mask: read as zero, guest write ignore (write zero to hardware) ro_mask: read normal, guest write ignore (preserve on write to hardware) rw1c_mask: read normal, write 1 to clear The RsvdZ naming was borrowed from the PCI Express Base 4.0 specification. Xen preserves the value of read-only bits on write to hardware, discarding = the guests write value. The mask_cap_list flag will be set in a follow-on patch. Signed-off-by: Stewart Hildebrand --- v5->v6: * remove duplicate PCI_STATUS_CAP_LIST in constant definition * style fixup in constant definitions * s/res_mask/rsvdz_mask/ * combine a new masking operation into single line * preserve r/o bits on write * get rid of status_read. Instead, use rsvdz_mask for conditionally masking PCI_STATUS_CAP_LIST bit * add comment about PCI_STATUS_CAP_LIST and rsvdp behavior * add sanity checks in add_register * move mask_cap_list from struct vpci_header to local variable v4->v5: * add support for res_mask * add support for ro_mask (squash ro_mask patch) * add constants for reserved, read-only, and rw1c masks v3->v4: * move mask_cap_list setting to the capabilities patch * single pci_conf_read16 in status_read * align mask_cap_list bitfield in struct vpci_header * change to rw1c bit mask instead of treating whole register as rw1c * drop subsystem prefix on renamed add_register function v2->v3: * new patch --- xen/drivers/vpci/header.c | 13 +++++++++ xen/drivers/vpci/vpci.c | 55 +++++++++++++++++++++++++++++--------- xen/include/xen/pci_regs.h | 9 +++++++ xen/include/xen/vpci.h | 8 ++++++ 4 files changed, 73 insertions(+), 12 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 767c1ba718d7..99dcf57678a8 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -521,6 +521,7 @@ static int cf_check init_bars(struct pci_dev *pdev) struct vpci_header *header =3D &pdev->vpci->header; struct vpci_bar *bars =3D header->bars; int rc; + bool mask_cap_list =3D false; =20 switch ( pci_conf_read8(pdev->sbdf, PCI_HEADER_TYPE) & 0x7f ) { @@ -544,6 +545,18 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; =20 + /* + * If mask_cap_list is true, PCI_STATUS_CAP_LIST will be set in both + * rsvdz_mask and ro_mask, and thus will effectively behave as rsvdp + * (reserved/RAZ and preserved on write). + */ + rc =3D vpci_add_register_mask(pdev->vpci, vpci_hw_read16, vpci_hw_writ= e16, + PCI_STATUS, 2, header, PCI_STATUS_RSVDZ_MA= SK | + (mask_cap_list ? PCI_STATUS_CAP_LIST : 0), + PCI_STATUS_RO_MASK, PCI_STATUS_RW1C_MASK); + if ( rc ) + return rc; + if ( pdev->ignore_bars ) return 0; =20 diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 3bec9a4153da..586c6057365b 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -29,6 +29,9 @@ struct vpci_register { unsigned int offset; void *private; struct list_head node; + uint32_t rsvdz_mask; + uint32_t ro_mask; + uint32_t rw1c_mask; }; =20 #ifdef __XEN__ @@ -145,9 +148,16 @@ uint32_t cf_check vpci_hw_read32( return pci_conf_read32(pdev->sbdf, reg); } =20 -int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, - vpci_write_t *write_handler, unsigned int offset, - unsigned int size, void *data) +void cf_check vpci_hw_write16( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) +{ + pci_conf_write16(pdev->sbdf, reg, val); +} + +static int add_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data, uint32_t rsvdz_mask, + uint32_t ro_mask, uint32_t rw1c_mask) { struct list_head *prev; struct vpci_register *r; @@ -155,7 +165,8 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t *r= ead_handler, /* Some sanity checks. */ if ( (size !=3D 1 && size !=3D 2 && size !=3D 4) || offset >=3D PCI_CFG_SPACE_EXP_SIZE || (offset & (size - 1)) || - (!read_handler && !write_handler) ) + (!read_handler && !write_handler) || (ro_mask & rw1c_mask) || + (rsvdz_mask & rw1c_mask) ) return -EINVAL; =20 r =3D xmalloc(struct vpci_register); @@ -167,6 +178,9 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t *r= ead_handler, r->size =3D size; r->offset =3D offset; r->private =3D data; + r->rsvdz_mask =3D rsvdz_mask & (0xffffffffU >> (32 - 8 * size)); + r->ro_mask =3D ro_mask & (0xffffffffU >> (32 - 8 * size)); + r->rw1c_mask =3D rw1c_mask & (0xffffffffU >> (32 - 8 * size)); =20 spin_lock(&vpci->lock); =20 @@ -193,6 +207,23 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t *= read_handler, return 0; } =20 +int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data) +{ + return add_register(vpci, read_handler, write_handler, offset, size, d= ata, + 0, 0, 0); +} + +int vpci_add_register_mask(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offse= t, + unsigned int size, void *data, uint32_t rsvdz_m= ask, + uint32_t ro_mask, uint32_t rw1c_mask) +{ + return add_register(vpci, read_handler, write_handler, offset, size, d= ata, + rsvdz_mask, ro_mask, rw1c_mask); +} + int vpci_remove_register(struct vpci *vpci, unsigned int offset, unsigned int size) { @@ -376,6 +407,7 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, u= nsigned int size) } =20 val =3D r->read(pdev, r->offset, r->private); + val &=3D ~r->rsvdz_mask; =20 /* Check if the read is in the middle of a register. */ if ( r->offset < emu.offset ) @@ -407,26 +439,25 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg,= unsigned int size) =20 /* * Perform a maybe partial write to a register. - * - * Note that this will only work for simple registers, if Xen needs to - * trap accesses to rw1c registers (like the status PCI header register) - * the logic in vpci_write will have to be expanded in order to correctly - * deal with them. */ static void vpci_write_helper(const struct pci_dev *pdev, const struct vpci_register *r, unsigned int = size, unsigned int offset, uint32_t data) { + uint32_t val =3D 0; + ASSERT(size <=3D r->size); =20 - if ( size !=3D r->size ) + if ( (size !=3D r->size) || r->ro_mask ) { - uint32_t val; - val =3D r->read(pdev, r->offset, r->private); + val &=3D ~r->rw1c_mask; data =3D merge_result(val, data, size, offset); } =20 + data &=3D ~r->rsvdz_mask & ~r->ro_mask; + data |=3D val & r->ro_mask; + r->write(pdev, r->offset, data & (0xffffffffU >> (32 - 8 * r->size)), r->private); } diff --git a/xen/include/xen/pci_regs.h b/xen/include/xen/pci_regs.h index 84b18736a85d..b72131729db6 100644 --- a/xen/include/xen/pci_regs.h +++ b/xen/include/xen/pci_regs.h @@ -66,6 +66,15 @@ #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ +#define PCI_STATUS_RSVDZ_MASK 0x0006 + +#define PCI_STATUS_RO_MASK (PCI_STATUS_IMM_READY | PCI_STATUS_INTERRUPT |= \ + PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ | PCI_STATUS_UDF | \ + PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) +#define PCI_STATUS_RW1C_MASK (PCI_STATUS_PARITY | \ + PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_REC_TARGET_ABORT | \ + PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_SIG_SYSTEM_ERROR | \ + PCI_STATUS_DETECTED_PARITY) =20 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision = */ #define PCI_REVISION_ID 0x08 /* Revision ID */ diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 0b8a2a3c745b..7a5cca29e54c 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -37,6 +37,12 @@ int __must_check vpci_add_register(struct vpci *vpci, vpci_write_t *write_handler, unsigned int offset, unsigned int size, void *data); +int __must_check vpci_add_register_mask(struct vpci *vpci, + vpci_read_t *read_handler, + vpci_write_t *write_handler, + unsigned int offset, unsigned int = size, + void *data, uint32_t rsvdz_mask, + uint32_t ro_mask, uint32_t rw1c_ma= sk); int __must_check vpci_remove_register(struct vpci *vpci, unsigned int offs= et, unsigned int size); =20 @@ -50,6 +56,8 @@ uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read32( const struct pci_dev *pdev, unsigned int reg, void *data); +void cf_check vpci_hw_write16( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data= ); =20 /* * Check for pending vPCI operations on this vcpu. Returns true if the vcpu --=20 2.42.0 From nobody Sun May 19 07:31:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1694226008; cv=pass; d=zohomail.com; s=zohoarc; b=T3qvypTFsCXCOeKk+x9qnL8drhelsqo16VAS1eKnqkTTl9bxrIwXOgvOqO6zgoERv8aYkhj2EmtGFsTS2MKiqTS2v9AfwCaPvW8Og4oF3v5Cc91DJab/4Xfk7ZhIxZPU9Qst1bNQn4SDgxhR+Fcpm7aCQszU1xZyEkQC1SB5G5g= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694226008; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4zynH6bdtDF71r3QmVXE6saNFjB3y2Dk04pLrBIKZUo=; b=Vp9OxLZIcYud2nO77ar3Z+uv9L/ECZDWf2FjFswdT62cpI45Q4LEwrC/LiYCJ5CaewdpqR/PBZuxD1LDwWMIkbYKy7Kc1CSIz0nuM/ziNHDxyhtou3RRgbZ43yPQhpJE3vx7DMKhLuWK5CHkzE72PVQowYNo4WqwjLOx/Qpay4Q= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1694226008023699.2652746295962; Fri, 8 Sep 2023 19:20:08 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.598359.933104 (Exim 4.92) (envelope-from ) id 1qenZZ-0004xY-4u; Sat, 09 Sep 2023 02:19:45 +0000 Received: by outflank-mailman (output) from mailman id 598359.933104; Sat, 09 Sep 2023 02:19:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qenZZ-0004xR-15; Sat, 09 Sep 2023 02:19:45 +0000 Received: by outflank-mailman (input) for mailman id 598359; Sat, 09 Sep 2023 02:19:43 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qenZX-0003dU-Nm for xen-devel@lists.xenproject.org; Sat, 09 Sep 2023 02:19:43 +0000 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on20611.outbound.protection.outlook.com [2a01:111:f400:7eb2::611]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 55653dd0-4eb7-11ee-9b0d-b553b5be7939; Sat, 09 Sep 2023 04:19:41 +0200 (CEST) Received: from CY8PR10CA0038.namprd10.prod.outlook.com (2603:10b6:930:4b::22) by SN7PR12MB7154.namprd12.prod.outlook.com (2603:10b6:806:2a5::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6745.34; Sat, 9 Sep 2023 02:19:36 +0000 Received: from CY4PEPF0000E9D4.namprd03.prod.outlook.com (2603:10b6:930:4b:cafe::3e) by CY8PR10CA0038.outlook.office365.com (2603:10b6:930:4b::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6768.31 via Frontend Transport; Sat, 9 Sep 2023 02:19:35 +0000 Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D4.mail.protection.outlook.com (10.167.241.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6792.11 via Frontend Transport; Sat, 9 Sep 2023 02:19:35 +0000 Received: from SATLEXMB08.amd.com (10.181.40.132) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 8 Sep 2023 21:19:34 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 8 Sep 2023 19:19:34 -0700 Received: from ubuntu.mshome.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Fri, 8 Sep 2023 21:19:32 -0500 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 55653dd0-4eb7-11ee-9b0d-b553b5be7939 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nL4DFepLL3YE6S8Wk9tHfklVXFEh2uQVmsbkyTj5dzoWR4gz2zPlOTKsR+vlNe5xEo78SrZokWTNg5k8AXn7zNt1UJG3/TSLyNiOR3NxmJ4HkJaZwNUt/YDC3EAKVXrX1KgEI1JQeejiQKHkgRxIHVu2eRIMmj1Xw7t4D1tAo33uXSmuZ69622+Xp//yUJMwumCTAeqG9rZFxON7JBY4PwoqHrQ6O1zrojAqDKRhfBAJYqUtwPblpRZDDTQ7lHiBUlu35kTPzZExbM7tcXvjCD5UzB1a2kalUdFf8EvAJyhorVSRbDFDZtPK4ftL0uHDsklfCjRGojGnBOeE28+naQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4zynH6bdtDF71r3QmVXE6saNFjB3y2Dk04pLrBIKZUo=; b=YphjmFHxkkbw/8JiIALcVSUBJnONs8Qvk/Q73xUrATUeb2hRTJ7cCzd/aJL7RnrOyWvSLZZI2vuUxsRSZWtdY+v4K1WC5SdrPukITgLzigpTAhjHtmXaVtLcf+TsoFEDdLS3lCAEjRV/ZtnSZy/K4KHycYv4JySOp9IPmEsCQn7OE0Iac1OMMoZlbEnqRFE7jtboKcsM4ytq22qVpFq+tXJxm/0QZD3zLSDW77mPM00P7ZispRRnSiSkLgoSEPeM2qG5RrhRTGAfhaA6FnarDpZFcTcGTzNhXHhJTmvteg0OLnH/56eJawRRKt6nYDqHmy5xQONpeXrMoUTnrdqUJg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4zynH6bdtDF71r3QmVXE6saNFjB3y2Dk04pLrBIKZUo=; b=bM59Z4c9KfTluoSEFF1C5Kshj69blI52M9PWFMia4qJ6R333Vw0R2OQSZc9KH28jzuQwguMq5k/Pe7AWHicT6RtMUD/BCkq07X7fNzSjbgv2rN0gj/EwcNXY0DQOrNlUCSYafAkIzSD9ymqiWEG6ZJnsUOg5zbyVCYI4RWaXRNE= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Andrew Cooper , George Dunlap , "Jan Beulich" , Julien Grall , "Stefano Stabellini" , Wei Liu , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v6 4/4] xen/vpci: header: filter PCI capabilities Date: Fri, 8 Sep 2023 22:16:28 -0400 Message-ID: <20230909021647.558115-5-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230909021647.558115-1-stewart.hildebrand@amd.com> References: <20230909021647.558115-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|SN7PR12MB7154:EE_ X-MS-Office365-Filtering-Correlation-Id: f662380b-b764-4ffb-750d-08dbb0db3623 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Fm6Q4N4vJEHipoxwyR9mDAqE7NklxyXjGWFPOUcXEUlKvVSEp+HAh+B4Neo5DmItDrBSZx/9sM4gNnr9ywLetQ85W9yyMvO2dXyY6Z0iTt9lWfI9vybuzZdyMxYrH0zO3TEGXtSeIVtRvDd1LnU7weVGajxGw3QpII8pMmuGFf++qIUBHRAASazWB1Q+lOXXEk/x/OI+qfAy4Gx8V7n71gtJ0R3w2vI0PSoiGdhGTofDorMp8zR0/OrZzDEj+ihM0Hn77CjIxb9bWeNiaWZLNw7YeIDARxL/UirNx1HeF/ek0ilDNK1sBe9iW5oHeOh2oTmVfLLkl0jXGM3HxD+auz7LVeCiecl73TageyOVZ+8AohG9H1wG0Nwn6gdthUPraVA/fsQS7cTCxSxAX3jm9tFhpOPUo0VUnpqFueje75Jgx3jmFS5y9lkqh/FFy8SSVEarrtMQl28sS7iJp/6whx08fVOOQcecvuUmiNAOXBqCLB7WG7xdONkbyyCQKuSmoK6tf1Y0NNJMph7JIYAZ/3ADVa944rww8QqcsDxrLyHu8Wbp81jVC1geoF4GAhgXL5G5nUv/ycD+L/OW2Rtp11XcVPUHZLBsl2n63XFiy1FRdPJ1K+U2SLwiSohiygMU3yBtwR6fQ3qocT2Gowiht8WpGHrf5ZysJQXFXC1hCwps7cJIoB5GowgftxvOvpofOZHCCEX2dkGmJ4jtihQVm6iX6ynayyS9Jwo/8GqJE5hWx0KKoHIuXAfxlk+ZD1jteVgiJMlXzp3JK7XPLTFFpw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(376002)(346002)(39860400002)(82310400011)(186009)(451199024)(1800799009)(46966006)(40470700004)(36840700001)(36756003)(40460700003)(2906002)(47076005)(426003)(83380400001)(336012)(1076003)(54906003)(316002)(2616005)(6916009)(70206006)(36860700001)(4326008)(70586007)(8936002)(478600001)(8676002)(44832011)(5660300002)(81166007)(82740400003)(6666004)(356005)(26005)(86362001)(40480700001)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2023 02:19:35.4583 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f662380b-b764-4ffb-750d-08dbb0db3623 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7154 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1694226008801100001 Content-Type: text/plain; charset="utf-8" Currently, Xen vPCI only supports virtualizing the MSI and MSI-X capabiliti= es. Hide all other PCI capabilities (including extended capabilities) from domU= s for now, even though there may be certain devices/drivers that depend on being = able to discover certain capabilities. We parse the physical PCI capabilities linked list and add vPCI register handlers for the next elements, inserting our own next value, thus presenti= ng a modified linked list to the domU. Introduce helper functions vpci_hw_read8 and vpci_read_val. The vpci_read_v= al helper function returns a fixed value, which may be used for RAZ registers,= or registers whose value doesn't change. Introduce pci_find_next_cap_ttl() helper while adapting the logic from pci_find_next_cap() to suit our needs, and implement the existing pci_find_next_cap() in terms of the new helper. Signed-off-by: Stewart Hildebrand Reviewed-by: Jan Beulich --- v5->v6: * add register handlers before status register handler in init_bars() * s/header->mask_cap_list/mask_cap_list/ v4->v5: * use more appropriate types, continued * get rid of unnecessary hook function * add Jan's R-b v3->v4: * move mask_cap_list setting to this patch * leave pci_find_next_cap signature alone * use more appropriate types v2->v3: * get rid of > 0 in loop condition * implement pci_find_next_cap in terms of new pci_find_next_cap_ttl functio= n so that hypothetical future callers wouldn't be required to pass &ttl. * change NULL to (void *)0 for RAZ value passed to vpci_read_val * change type of ttl to unsigned int * remember to mask off the low 2 bits of next in the initial loop iteration * change return type of pci_find_next_cap and pci_find_next_cap_ttl * avoid wrapping the PCI_STATUS_CAP_LIST condition by using ! instead of = =3D=3D 0 v1->v2: * change type of ttl to int * use switch statement instead of if/else * adapt existing pci_find_next_cap helper instead of rolling our own * pass ttl as in/out * "pass through" the lower 2 bits of the next pointer * squash helper functions into this patch to avoid transient dead code situ= ation * extended capabilities RAZ/WI --- xen/drivers/pci/pci.c | 26 +++++++++----- xen/drivers/vpci/header.c | 76 +++++++++++++++++++++++++++++++++++++++ xen/drivers/vpci/vpci.c | 12 +++++++ xen/include/xen/pci.h | 3 ++ xen/include/xen/vpci.h | 5 +++ 5 files changed, 113 insertions(+), 9 deletions(-) diff --git a/xen/drivers/pci/pci.c b/xen/drivers/pci/pci.c index 3569ccb24e9e..8799d60c2156 100644 --- a/xen/drivers/pci/pci.c +++ b/xen/drivers/pci/pci.c @@ -39,31 +39,39 @@ unsigned int pci_find_cap_offset(pci_sbdf_t sbdf, unsig= ned int cap) return 0; } =20 -unsigned int pci_find_next_cap(pci_sbdf_t sbdf, unsigned int pos, - unsigned int cap) +unsigned int pci_find_next_cap_ttl(pci_sbdf_t sbdf, unsigned int pos, + bool (*is_match)(unsigned int), + unsigned int cap, unsigned int *ttl) { - u8 id; - int ttl =3D 48; + unsigned int id; =20 - while ( ttl-- ) + while ( (*ttl)-- ) { pos =3D pci_conf_read8(sbdf, pos); if ( pos < 0x40 ) break; =20 - pos &=3D ~3; - id =3D pci_conf_read8(sbdf, pos + PCI_CAP_LIST_ID); + id =3D pci_conf_read8(sbdf, (pos & ~3) + PCI_CAP_LIST_ID); =20 if ( id =3D=3D 0xff ) break; - if ( id =3D=3D cap ) + if ( (is_match && is_match(id)) || (!is_match && id =3D=3D cap) ) return pos; =20 - pos +=3D PCI_CAP_LIST_NEXT; + pos =3D (pos & ~3) + PCI_CAP_LIST_NEXT; } + return 0; } =20 +unsigned int pci_find_next_cap(pci_sbdf_t sbdf, unsigned int pos, + unsigned int cap) +{ + unsigned int ttl =3D 48; + + return pci_find_next_cap_ttl(sbdf, pos, NULL, cap, &ttl) & ~3; +} + /** * pci_find_ext_capability - Find an extended capability * @sbdf: PCI device to query diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 99dcf57678a8..118dd5d4535d 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -513,6 +513,18 @@ static void cf_check rom_write( rom->addr =3D val & PCI_ROM_ADDRESS_MASK; } =20 +static bool cf_check vpci_cap_supported(unsigned int id) +{ + switch ( id ) + { + case PCI_CAP_ID_MSI: + case PCI_CAP_ID_MSIX: + return true; + default: + return false; + } +} + static int cf_check init_bars(struct pci_dev *pdev) { uint16_t cmd; @@ -545,6 +557,70 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; =20 + if ( !is_hardware_domain(pdev->domain) ) + { + if ( !(pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LI= ST) ) + { + /* RAZ/WI */ + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, (void *)0); + if ( rc ) + return rc; + } + else + { + /* Only expose capabilities to the guest that vPCI can handle.= */ + unsigned int next, ttl =3D 48; + + next =3D pci_find_next_cap_ttl(pdev->sbdf, PCI_CAPABILITY_LIST, + vpci_cap_supported, 0, &ttl); + + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &=3D ~3; + + if ( !next ) + /* + * If we don't have any supported capabilities to expose t= o the + * guest, mask the PCI_STATUS_CAP_LIST bit in the status + * register. + */ + mask_cap_list =3D true; + + while ( next && ttl ) + { + unsigned int pos =3D next; + + next =3D pci_find_next_cap_ttl(pdev->sbdf, + pos + PCI_CAP_LIST_NEXT, + vpci_cap_supported, 0, &ttl); + + rc =3D vpci_add_register(pdev->vpci, vpci_hw_read8, NULL, + pos + PCI_CAP_LIST_ID, 1, NULL); + if ( rc ) + return rc; + + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + pos + PCI_CAP_LIST_NEXT, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &=3D ~3; + } + } + + /* Extended capabilities RAZ/WI */ + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, 0x100, 4, + (void *)0); + if ( rc ) + return rc; + } + /* * If mask_cap_list is true, PCI_STATUS_CAP_LIST will be set in both * rsvdz_mask and ro_mask, and thus will effectively behave as rsvdp diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 586c6057365b..433b9b3ebbb1 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -136,6 +136,18 @@ static void cf_check vpci_ignored_write( { } =20 +uint32_t cf_check vpci_read_val( + const struct pci_dev *pdev, unsigned int reg, void *data) +{ + return (uintptr_t)data; +} + +uint32_t cf_check vpci_hw_read8( + const struct pci_dev *pdev, unsigned int reg, void *data) +{ + return pci_conf_read8(pdev->sbdf, reg); +} + uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data) { diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index ea6a4c9abf38..cceac8654f07 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -194,6 +194,9 @@ int pci_mmcfg_read(unsigned int seg, unsigned int bus, int pci_mmcfg_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value); unsigned int pci_find_cap_offset(pci_sbdf_t sbdf, unsigned int cap); +unsigned int pci_find_next_cap_ttl(pci_sbdf_t sbdf, unsigned int pos, + bool (*is_match)(unsigned int), + unsigned int cap, unsigned int *ttl); unsigned int pci_find_next_cap(pci_sbdf_t sbdf, unsigned int pos, unsigned int cap); unsigned int pci_find_ext_capability(pci_sbdf_t sbdf, unsigned int cap); diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 7a5cca29e54c..b79efc49bad6 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -51,7 +51,12 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, un= signed int size); void vpci_write(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, uint32_t data); =20 +uint32_t cf_check vpci_read_val( + const struct pci_dev *pdev, unsigned int reg, void *data); + /* Passthrough handlers. */ +uint32_t cf_check vpci_hw_read8( + const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read32( --=20 2.42.0