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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2023 18:00:09.8161 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ddca4f7b-1661-4d2d-1401-08dba7f09eae X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE39.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4457 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1693245643513100001 These were left over after a previous pci_sbdf_t conversion. Fixes: 0c38c61aad21 ("pci: switch pci_conf_write32 to use pci_sbdf_t") Signed-off-by: Stewart Hildebrand Reviewed-by: Jan Beulich --- v3->v4: * new patch: this change was split from ("xen/pci: convert pci_find_*cap* to pci_sbdf_t") Found by building with EXTRA_CFLAGS_XEN_CORE=3D"-Wunused-but-set-variable" arch/x86/msi.c: In function =E2=80=98msi_set_mask_bit=E2=80=99: arch/x86/msi.c:322:19: warning: variable =E2=80=98func=E2=80=99 set but not= used [-Wunused-but-set-variable] 322 | u8 bus, slot, func; | ^~~~ arch/x86/msi.c:322:13: warning: variable =E2=80=98slot=E2=80=99 set but not= used [-Wunused-but-set-variable] 322 | u8 bus, slot, func; | ^~~~ arch/x86/msi.c:322:8: warning: variable =E2=80=98bus=E2=80=99 set but not u= sed [-Wunused-but-set-variable] 322 | u8 bus, slot, func; | ^~~ arch/x86/msi.c:321:9: warning: variable =E2=80=98seg=E2=80=99 set but not u= sed [-Wunused-but-set-variable] 321 | u16 seg, control; | ^~~ --- xen/arch/x86/msi.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c index d0bf63df1def..41b82f3e87cb 100644 --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -318,17 +318,12 @@ static bool msi_set_mask_bit(struct irq_desc *desc, b= ool host, bool guest) { struct msi_desc *entry =3D desc->msi_desc; struct pci_dev *pdev; - u16 seg, control; - u8 bus, slot, func; + uint16_t control; bool flag =3D host || guest, maskall; =20 ASSERT(spin_is_locked(&desc->lock)); BUG_ON(!entry || !entry->dev); pdev =3D entry->dev; - seg =3D pdev->seg; - bus =3D pdev->bus; - slot =3D PCI_SLOT(pdev->devfn); - func =3D PCI_FUNC(pdev->devfn); switch ( entry->msi_attrib.type ) { case PCI_CAP_ID_MSI: --=20 2.42.0 From nobody Sun May 19 15:58:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1693245674; cv=pass; d=zohomail.com; s=zohoarc; b=hWtd2XwLZUs2HUatuYYKowrRCRgiCAIgp03gGYPklDqgM4w877ZmtgBq5IcKy1C8bDM9WdSkE6ngPKxIzGpmBaXgg3ldJ03GZoqzjVgtYnJFOgBD/UdJSJ5sQI5wa95d2DOyEonWjZd1BKTVyfgCrnTxb6+kcEz0SHO5UW4/JbA= ARC-Message-Signature: i=2; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2023 18:00:47.5186 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9aed885-ee32-45f0-6715-08dba7f0b529 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6698 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1693245676566100001 Content-Type: text/plain; charset="utf-8" Convert pci_find_*cap* functions and call sites to pci_sbdf_t, and remove s= ome now unused local variables. Also change to more appropriate types on lines = that are already being modified as a result of the pci_sbdf_t conversion. Signed-off-by: Stewart Hildebrand Reviewed-by: Jan Beulich --- I built with EXTRA_CFLAGS_XEN_CORE=3D"-Wunused-but-set-variable" (and unfortunately -Wno-error=3Dunused-but-set-variable too) to identify locatio= ns of unneeded local variables as a result of the change to pci_sbdf_t. v3->v4: * use more appropriate types on lines that are being modified anyway * remove "no functional change" from commit description v2->v3: * new patch --- xen/arch/x86/msi.c | 40 ++++++---------------- xen/drivers/char/ehci-dbgp.c | 3 +- xen/drivers/passthrough/amd/iommu_detect.c | 2 +- xen/drivers/passthrough/ats.c | 4 +-- xen/drivers/passthrough/ats.h | 6 ++-- xen/drivers/passthrough/msi.c | 6 ++-- xen/drivers/passthrough/pci.c | 21 +++++------- xen/drivers/passthrough/vtd/quirks.c | 10 ++---- xen/drivers/passthrough/vtd/x86/ats.c | 3 +- xen/drivers/pci/pci.c | 32 +++++++++-------- xen/drivers/vpci/msi.c | 4 +-- xen/drivers/vpci/msix.c | 4 +-- xen/include/xen/pci.h | 11 +++--- 13 files changed, 58 insertions(+), 88 deletions(-) diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c index 41b82f3e87cb..8d4fd43b10a6 100644 --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -283,7 +283,7 @@ static void msi_set_enable(struct pci_dev *dev, int ena= ble) u8 slot =3D PCI_SLOT(dev->devfn); u8 func =3D PCI_FUNC(dev->devfn); =20 - pos =3D pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSI); + pos =3D pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSI); if ( pos ) __msi_set_enable(seg, bus, slot, func, pos, enable); } @@ -291,12 +291,9 @@ static void msi_set_enable(struct pci_dev *dev, int en= able) static void msix_set_enable(struct pci_dev *dev, int enable) { int pos; - u16 control, seg =3D dev->seg; - u8 bus =3D dev->bus; - u8 slot =3D PCI_SLOT(dev->devfn); - u8 func =3D PCI_FUNC(dev->devfn); + uint16_t control; =20 - pos =3D pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSIX); + pos =3D pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSIX); if ( pos ) { control =3D pci_conf_read16(dev->sbdf, msix_control_reg(pos)); @@ -603,13 +600,10 @@ static int msi_capability_init(struct pci_dev *dev, struct msi_desc *entry; int pos; unsigned int i, mpos; - u16 control, seg =3D dev->seg; - u8 bus =3D dev->bus; - u8 slot =3D PCI_SLOT(dev->devfn); - u8 func =3D PCI_FUNC(dev->devfn); + uint16_t control; =20 ASSERT(pcidevs_locked()); - pos =3D pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSI); + pos =3D pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSI); if ( !pos ) return -ENODEV; control =3D pci_conf_read16(dev->sbdf, msi_control_reg(pos)); @@ -680,8 +674,8 @@ static u64 read_pci_mem_bar(u16 seg, u8 bus, u8 slot, u= 8 func, u8 bir, int vf) { struct pci_dev *pdev =3D pci_get_pdev(NULL, PCI_SBDF(seg, bus, slot, func)= ); - unsigned int pos =3D pci_find_ext_capability(seg, bus, - PCI_DEVFN(slot, func), + unsigned int pos =3D pci_find_ext_capability(PCI_SBDF(seg, bus, sl= ot, + func), PCI_EXT_CAP_ID_SRIOV); uint16_t ctrl =3D pci_conf_read16(PCI_SBDF(seg, bus, slot, func), pos + PCI_SRIOV_CTRL); @@ -772,8 +766,7 @@ static int msix_capability_init(struct pci_dev *dev, u8 slot =3D PCI_SLOT(dev->devfn); u8 func =3D PCI_FUNC(dev->devfn); bool maskall =3D msix->host_maskall, zap_on_error =3D false; - unsigned int pos =3D pci_find_cap_offset(seg, bus, slot, func, - PCI_CAP_ID_MSIX); + unsigned int pos =3D pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSIX); =20 if ( !pos ) return -ENODEV; @@ -1097,12 +1090,7 @@ static void _pci_cleanup_msix(struct arch_msix *msix) static void __pci_disable_msix(struct msi_desc *entry) { struct pci_dev *dev =3D entry->dev; - u16 seg =3D dev->seg; - u8 bus =3D dev->bus; - u8 slot =3D PCI_SLOT(dev->devfn); - u8 func =3D PCI_FUNC(dev->devfn); - unsigned int pos =3D pci_find_cap_offset(seg, bus, slot, func, - PCI_CAP_ID_MSIX); + unsigned int pos =3D pci_find_cap_offset(dev->sbdf, PCI_CAP_ID_MSIX); u16 control =3D pci_conf_read16(dev->sbdf, msix_control_reg(entry->msi_attrib.pos)); bool maskall =3D dev->msix->host_maskall; @@ -1206,8 +1194,7 @@ void pci_cleanup_msi(struct pci_dev *pdev) =20 int pci_reset_msix_state(struct pci_dev *pdev) { - unsigned int pos =3D pci_find_cap_offset(pdev->seg, pdev->bus, pdev->s= bdf.dev, - pdev->sbdf.fn, PCI_CAP_ID_MSIX); + unsigned int pos =3D pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSIX); =20 ASSERT(pos); /* @@ -1229,10 +1216,6 @@ int pci_reset_msix_state(struct pci_dev *pdev) int pci_msi_conf_write_intercept(struct pci_dev *pdev, unsigned int reg, unsigned int size, uint32_t *data) { - u16 seg =3D pdev->seg; - u8 bus =3D pdev->bus; - u8 slot =3D PCI_SLOT(pdev->devfn); - u8 func =3D PCI_FUNC(pdev->devfn); struct msi_desc *entry; unsigned int pos; =20 @@ -1240,8 +1223,7 @@ int pci_msi_conf_write_intercept(struct pci_dev *pdev= , unsigned int reg, { entry =3D find_msi_entry(pdev, -1, PCI_CAP_ID_MSIX); pos =3D entry ? entry->msi_attrib.pos - : pci_find_cap_offset(seg, bus, slot, func, - PCI_CAP_ID_MSIX); + : pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSIX); ASSERT(pos); =20 if ( reg >=3D pos && reg < msix_pba_offset_reg(pos) + 4 ) diff --git a/xen/drivers/char/ehci-dbgp.c b/xen/drivers/char/ehci-dbgp.c index 72be4d9cc970..00cbdd5454dd 100644 --- a/xen/drivers/char/ehci-dbgp.c +++ b/xen/drivers/char/ehci-dbgp.c @@ -687,7 +687,8 @@ static unsigned int __init __find_dbgp(u8 bus, u8 slot,= u8 func) if ( (class >> 8) !=3D PCI_CLASS_SERIAL_USB_EHCI ) return 0; =20 - return pci_find_cap_offset(0, bus, slot, func, PCI_CAP_ID_EHCI_DEBUG); + return pci_find_cap_offset(PCI_SBDF(0, bus, slot, func), + PCI_CAP_ID_EHCI_DEBUG); } =20 static unsigned int __init find_dbgp(struct ehci_dbgp *dbgp, diff --git a/xen/drivers/passthrough/amd/iommu_detect.c b/xen/drivers/passt= hrough/amd/iommu_detect.c index 2317fa6a7d8d..cede44e6518f 100644 --- a/xen/drivers/passthrough/amd/iommu_detect.c +++ b/xen/drivers/passthrough/amd/iommu_detect.c @@ -27,7 +27,7 @@ static int __init get_iommu_msi_capabilities( { int pos; =20 - pos =3D pci_find_cap_offset(seg, bus, dev, func, PCI_CAP_ID_MSI); + pos =3D pci_find_cap_offset(PCI_SBDF(seg, bus, dev, func), PCI_CAP_ID_= MSI); =20 if ( !pos ) return -ENODEV; diff --git a/xen/drivers/passthrough/ats.c b/xen/drivers/passthrough/ats.c index 253f5c2e1042..0da183d057c5 100644 --- a/xen/drivers/passthrough/ats.c +++ b/xen/drivers/passthrough/ats.c @@ -24,11 +24,9 @@ boolean_param("ats", ats_enabled); int enable_ats_device(struct pci_dev *pdev, struct list_head *ats_list) { u32 value; - u16 seg =3D pdev->seg; - u8 bus =3D pdev->bus, devfn =3D pdev->devfn; int pos; =20 - pos =3D pci_find_ext_capability(seg, bus, devfn, PCI_EXT_CAP_ID_ATS); + pos =3D pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_ATS); BUG_ON(!pos); =20 if ( iommu_verbose ) diff --git a/xen/drivers/passthrough/ats.h b/xen/drivers/passthrough/ats.h index baa5f6a6dc04..f5e1d254e0d3 100644 --- a/xen/drivers/passthrough/ats.h +++ b/xen/drivers/passthrough/ats.h @@ -32,7 +32,8 @@ static inline int pci_ats_enabled(int seg, int bus, int d= evfn) u32 value; int pos; =20 - pos =3D pci_find_ext_capability(seg, bus, devfn, PCI_EXT_CAP_ID_ATS); + pos =3D pci_find_ext_capability(PCI_SBDF(seg, bus, devfn), + PCI_EXT_CAP_ID_ATS); BUG_ON(!pos); =20 value =3D pci_conf_read16(PCI_SBDF(seg, bus, devfn), pos + ATS_REG_CTL= ); @@ -45,7 +46,8 @@ static inline int pci_ats_device(int seg, int bus, int de= vfn) if ( !ats_enabled ) return 0; =20 - return pci_find_ext_capability(seg, bus, devfn, PCI_EXT_CAP_ID_ATS); + return pci_find_ext_capability(PCI_SBDF(seg, bus, devfn), + PCI_EXT_CAP_ID_ATS); } =20 #endif /* _ATS_H_ */ diff --git a/xen/drivers/passthrough/msi.c b/xen/drivers/passthrough/msi.c index fb78e2ebe8a4..13d904692ef8 100644 --- a/xen/drivers/passthrough/msi.c +++ b/xen/drivers/passthrough/msi.c @@ -24,8 +24,7 @@ int pdev_msi_init(struct pci_dev *pdev) =20 INIT_LIST_HEAD(&pdev->msi_list); =20 - pos =3D pci_find_cap_offset(pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn= ), - PCI_FUNC(pdev->devfn), PCI_CAP_ID_MSI); + pos =3D pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSI); if ( pos ) { uint16_t ctrl =3D pci_conf_read16(pdev->sbdf, msi_control_reg(pos)= ); @@ -33,8 +32,7 @@ int pdev_msi_init(struct pci_dev *pdev) pdev->msi_maxvec =3D multi_msi_capable(ctrl); } =20 - pos =3D pci_find_cap_offset(pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn= ), - PCI_FUNC(pdev->devfn), PCI_CAP_ID_MSIX); + pos =3D pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSIX); if ( pos ) { struct arch_msix *msix =3D xzalloc(struct arch_msix); diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index ed1f689227fa..04d00c7c37df 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -361,8 +361,7 @@ static struct pci_dev *alloc_pdev(struct pci_seg *pseg,= u8 bus, u8 devfn) break; =20 case DEV_TYPE_PCIe_ENDPOINT: - pos =3D pci_find_cap_offset(pseg->nr, bus, PCI_SLOT(devfn), - PCI_FUNC(devfn), PCI_CAP_ID_EXP); + pos =3D pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_EXP); BUG_ON(!pos); cap =3D pci_conf_read16(pdev->sbdf, pos + PCI_EXP_DEVCAP); if ( cap & PCI_EXP_DEVCAP_PHANTOM ) @@ -565,13 +564,12 @@ struct pci_dev *pci_get_pdev(const struct domain *d, = pci_sbdf_t sbdf) static void pci_enable_acs(struct pci_dev *pdev) { int pos; - u16 cap, ctrl, seg =3D pdev->seg; - u8 bus =3D pdev->bus; + uint16_t cap, ctrl; =20 if ( !is_iommu_enabled(pdev->domain) ) return; =20 - pos =3D pci_find_ext_capability(seg, bus, pdev->devfn, PCI_EXT_CAP_ID_= ACS); + pos =3D pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_ACS); if (!pos) return; =20 @@ -704,7 +702,7 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn, =20 if ( !pdev->info.is_virtfn && !pdev->vf_rlen[0] ) { - unsigned int pos =3D pci_find_ext_capability(seg, bus, devfn, + unsigned int pos =3D pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_SRIOV); uint16_t ctrl =3D pci_conf_read16(pdev->sbdf, pos + PCI_SRIOV_CTRL= ); =20 @@ -916,7 +914,8 @@ enum pdev_type pdev_type(u16 seg, u8 bus, u8 devfn) { u16 class_device, creg; u8 d =3D PCI_SLOT(devfn), f =3D PCI_FUNC(devfn); - int pos =3D pci_find_cap_offset(seg, bus, d, f, PCI_CAP_ID_EXP); + unsigned int pos =3D pci_find_cap_offset(PCI_SBDF(seg, bus, devfn), + PCI_CAP_ID_EXP); =20 class_device =3D pci_conf_read16(PCI_SBDF(seg, bus, d, f), PCI_CLASS_D= EVICE); switch ( class_device ) @@ -1184,10 +1183,7 @@ static int hest_match_pci(const struct acpi_hest_aer= _common *p, static bool hest_match_type(const struct acpi_hest_header *hest_hdr, const struct pci_dev *pdev) { - unsigned int pos =3D pci_find_cap_offset(pdev->seg, pdev->bus, - PCI_SLOT(pdev->devfn), - PCI_FUNC(pdev->devfn), - PCI_CAP_ID_EXP); + unsigned int pos =3D pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_EXP); u8 pcie =3D MASK_EXTR(pci_conf_read16(pdev->sbdf, pos + PCI_EXP_FLAGS), PCI_EXP_FLAGS_TYPE); =20 @@ -1258,8 +1254,7 @@ bool pcie_aer_get_firmware_first(const struct pci_dev= *pdev) { struct aer_hest_parse_info info =3D { .pdev =3D pdev }; =20 - return pci_find_cap_offset(pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn), - PCI_FUNC(pdev->devfn), PCI_CAP_ID_EXP) && + return pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_EXP) && apei_hest_parse(aer_hest_parse, &info) >=3D 0 && info.firmware_first; } diff --git a/xen/drivers/passthrough/vtd/quirks.c b/xen/drivers/passthrough= /vtd/quirks.c index 5d706a539788..5a56565ea883 100644 --- a/xen/drivers/passthrough/vtd/quirks.c +++ b/xen/drivers/passthrough/vtd/quirks.c @@ -495,8 +495,6 @@ int me_wifi_quirk(struct domain *domain, uint8_t bus, u= int8_t devfn, =20 void pci_vtd_quirk(const struct pci_dev *pdev) { - int seg =3D pdev->seg; - int bus =3D pdev->bus; int pos; bool ff; u32 val, val2; @@ -532,12 +530,10 @@ void pci_vtd_quirk(const struct pci_dev *pdev) /* Sandybridge-EP (Romley) */ case 0x3c00: /* host bridge */ case 0x3c01 ... 0x3c0b: /* root ports */ - pos =3D pci_find_ext_capability(seg, bus, pdev->devfn, - PCI_EXT_CAP_ID_ERR); + pos =3D pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_ERR); if ( !pos ) { - pos =3D pci_find_ext_capability(seg, bus, pdev->devfn, - PCI_EXT_CAP_ID_VNDR); + pos =3D pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_VND= R); while ( pos ) { val =3D pci_conf_read32(pdev->sbdf, pos + PCI_VNDR_HEADER); @@ -546,7 +542,7 @@ void pci_vtd_quirk(const struct pci_dev *pdev) pos +=3D PCI_VNDR_HEADER; break; } - pos =3D pci_find_next_ext_capability(seg, bus, pdev->devfn= , pos, + pos =3D pci_find_next_ext_capability(pdev->sbdf, pos, PCI_EXT_CAP_ID_VNDR); } ff =3D 0; diff --git a/xen/drivers/passthrough/vtd/x86/ats.c b/xen/drivers/passthroug= h/vtd/x86/ats.c index 9de419775f90..1f5913bed9d2 100644 --- a/xen/drivers/passthrough/vtd/x86/ats.c +++ b/xen/drivers/passthrough/vtd/x86/ats.c @@ -57,8 +57,7 @@ int ats_device(const struct pci_dev *pdev, const struct a= cpi_drhd_unit *drhd) return 0; =20 ats_drhd =3D find_ats_dev_drhd(drhd->iommu); - pos =3D pci_find_ext_capability(pdev->seg, pdev->bus, pdev->devfn, - PCI_EXT_CAP_ID_ATS); + pos =3D pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_ATS); =20 if ( pos && (ats_drhd =3D=3D NULL) ) { diff --git a/xen/drivers/pci/pci.c b/xen/drivers/pci/pci.c index c73a8c4124af..3569ccb24e9e 100644 --- a/xen/drivers/pci/pci.c +++ b/xen/drivers/pci/pci.c @@ -8,25 +8,25 @@ #include #include =20 -int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 func, u8 cap) +unsigned int pci_find_cap_offset(pci_sbdf_t sbdf, unsigned int cap) { u8 id; int max_cap =3D 48; u8 pos =3D PCI_CAPABILITY_LIST; u16 status; =20 - status =3D pci_conf_read16(PCI_SBDF(seg, bus, dev, func), PCI_STATUS); + status =3D pci_conf_read16(sbdf, PCI_STATUS); if ( (status & PCI_STATUS_CAP_LIST) =3D=3D 0 ) return 0; =20 while ( max_cap-- ) { - pos =3D pci_conf_read8(PCI_SBDF(seg, bus, dev, func), pos); + pos =3D pci_conf_read8(sbdf, pos); if ( pos < 0x40 ) break; =20 pos &=3D ~3; - id =3D pci_conf_read8(PCI_SBDF(seg, bus, dev, func), pos + PCI_CAP= _LIST_ID); + id =3D pci_conf_read8(sbdf, pos + PCI_CAP_LIST_ID); =20 if ( id =3D=3D 0xff ) break; @@ -39,19 +39,20 @@ int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 fun= c, u8 cap) return 0; } =20 -int pci_find_next_cap(u16 seg, u8 bus, unsigned int devfn, u8 pos, int cap) +unsigned int pci_find_next_cap(pci_sbdf_t sbdf, unsigned int pos, + unsigned int cap) { u8 id; int ttl =3D 48; =20 while ( ttl-- ) { - pos =3D pci_conf_read8(PCI_SBDF(seg, bus, devfn), pos); + pos =3D pci_conf_read8(sbdf, pos); if ( pos < 0x40 ) break; =20 pos &=3D ~3; - id =3D pci_conf_read8(PCI_SBDF(seg, bus, devfn), pos + PCI_CAP_LIS= T_ID); + id =3D pci_conf_read8(sbdf, pos + PCI_CAP_LIST_ID); =20 if ( id =3D=3D 0xff ) break; @@ -65,21 +66,21 @@ int pci_find_next_cap(u16 seg, u8 bus, unsigned int dev= fn, u8 pos, int cap) =20 /** * pci_find_ext_capability - Find an extended capability - * @seg/@bus/@devfn: PCI device to query + * @sbdf: PCI device to query * @cap: capability code * * Returns the address of the requested extended capability structure * within the device's PCI configuration space or 0 if the device does * not support it. */ -int pci_find_ext_capability(int seg, int bus, int devfn, int cap) +unsigned int pci_find_ext_capability(pci_sbdf_t sbdf, unsigned int cap) { - return pci_find_next_ext_capability(seg, bus, devfn, 0, cap); + return pci_find_next_ext_capability(sbdf, 0, cap); } =20 /** * pci_find_next_ext_capability - Find another extended capability - * @seg/@bus/@devfn: PCI device to query + * @sbdf: PCI device to query * @start: starting position * @cap: capability code * @@ -87,13 +88,14 @@ int pci_find_ext_capability(int seg, int bus, int devfn= , int cap) * within the device's PCI configuration space or 0 if the device does * not support it. */ -int pci_find_next_ext_capability(int seg, int bus, int devfn, int start, i= nt cap) +unsigned int pci_find_next_ext_capability(pci_sbdf_t sbdf, unsigned int st= art, + unsigned int cap) { u32 header; int ttl =3D 480; /* 3840 bytes, minimum 8 bytes per capability */ - int pos =3D max(start, 0x100); + unsigned int pos =3D max(start, 0x100U); =20 - header =3D pci_conf_read32(PCI_SBDF(seg, bus, devfn), pos); + header =3D pci_conf_read32(sbdf, pos); =20 /* * If we have no capabilities, this is indicated by cap ID, @@ -109,7 +111,7 @@ int pci_find_next_ext_capability(int seg, int bus, int = devfn, int start, int cap pos =3D PCI_EXT_CAP_NEXT(header); if ( pos < 0x100 ) break; - header =3D pci_conf_read32(PCI_SBDF(seg, bus, devfn), pos); + header =3D pci_conf_read32(sbdf, pos); } return 0; } diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c index 2814b63d2be7..a253ccbd7db7 100644 --- a/xen/drivers/vpci/msi.c +++ b/xen/drivers/vpci/msi.c @@ -184,9 +184,7 @@ static void cf_check mask_write( =20 static int cf_check init_msi(struct pci_dev *pdev) { - uint8_t slot =3D PCI_SLOT(pdev->devfn), func =3D PCI_FUNC(pdev->devfn); - unsigned int pos =3D pci_find_cap_offset(pdev->seg, pdev->bus, slot, f= unc, - PCI_CAP_ID_MSI); + unsigned int pos =3D pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSI); uint16_t control; int ret; =20 diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index 1be861343dba..d1126a417da9 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -659,14 +659,12 @@ int vpci_make_msix_hole(const struct pci_dev *pdev) static int cf_check init_msix(struct pci_dev *pdev) { struct domain *d =3D pdev->domain; - uint8_t slot =3D PCI_SLOT(pdev->devfn), func =3D PCI_FUNC(pdev->devfn); unsigned int msix_offset, i, max_entries; uint16_t control; struct vpci_msix *msix; int rc; =20 - msix_offset =3D pci_find_cap_offset(pdev->seg, pdev->bus, slot, func, - PCI_CAP_ID_MSIX); + msix_offset =3D pci_find_cap_offset(pdev->sbdf, PCI_CAP_ID_MSIX); if ( !msix_offset ) return 0; =20 diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index 7d8a7cd21301..ea6a4c9abf38 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -193,11 +193,12 @@ int pci_mmcfg_read(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 *value); int pci_mmcfg_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value); -int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 func, u8 cap); -int pci_find_next_cap(u16 seg, u8 bus, unsigned int devfn, u8 pos, int cap= ); -int pci_find_ext_capability(int seg, int bus, int devfn, int cap); -int pci_find_next_ext_capability(int seg, int bus, int devfn, int start, - int cap); +unsigned int pci_find_cap_offset(pci_sbdf_t sbdf, unsigned int cap); +unsigned int pci_find_next_cap(pci_sbdf_t sbdf, unsigned int pos, + unsigned int cap); +unsigned int pci_find_ext_capability(pci_sbdf_t sbdf, unsigned int cap); +unsigned int pci_find_next_ext_capability(pci_sbdf_t sbdf, unsigned int st= art, + unsigned int cap); const char *parse_pci(const char *, unsigned int *seg, unsigned int *bus, unsigned int *dev, unsigned int *func); const char *parse_pci_seg(const char *, unsigned int *seg, unsigned int *b= us, --=20 2.42.0 From nobody Sun May 19 15:58:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1693245731; cv=pass; d=zohomail.com; s=zohoarc; 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bh=mS9rwZFaRU6LsAH3hSbs0rvFafQqmACIWYiLR7cPWEs=; b=SR0yJoPsVpQ2D1djm7+QaADbSgGxMQQQaSIFLKCbheTsxPXiYp3fhOjwv09cWAWbrHLQD8yUt3Ju6ohcCYwItN0P4KqqLsVnimzx/OjrVhx67NINtBx6lNl9G9Nhi57g0x/K3yCuKQPL194kiWEb9JpF57yLFV7Elqvuv/wHEoI= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH v4 3/6] x86/msi: rearrange read_pci_mem_bar slightly Date: Mon, 28 Aug 2023 13:56:51 -0400 Message-ID: <20230828175858.30780-4-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230828175858.30780-1-stewart.hildebrand@amd.com> References: <20230828175858.30780-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E9:EE_|DM6PR12MB4155:EE_ X-MS-Office365-Filtering-Correlation-Id: 63a8ffa4-c099-48f2-7415-08dba7f0d76a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2023 18:01:44.9562 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63a8ffa4-c099-48f2-7415-08dba7f0d76a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4155 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1693245733586100001 Content-Type: text/plain; charset="utf-8" Use pdev->sbdf instead of the PCI_SBDF macro in calls to pci_* functions where appropriate. Move NULL check earlier. Suggested-by: Jan Beulich Signed-off-by: Stewart Hildebrand Reviewed-by: Jan Beulich Suggested-by tag added based on conversation at [1] --- v3->v4: * new patch Suggested-by tag added based on conversation at [1] [1] https://lists.xenproject.org/archives/html/xen-devel/2023-08/msg01886.h= tml --- xen/arch/x86/msi.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c index 8d4fd43b10a6..a78367d7cf5d 100644 --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -674,19 +674,19 @@ static u64 read_pci_mem_bar(u16 seg, u8 bus, u8 slot,= u8 func, u8 bir, int vf) { struct pci_dev *pdev =3D pci_get_pdev(NULL, PCI_SBDF(seg, bus, slot, func)= ); - unsigned int pos =3D pci_find_ext_capability(PCI_SBDF(seg, bus, sl= ot, - func), - PCI_EXT_CAP_ID_SRIOV); - uint16_t ctrl =3D pci_conf_read16(PCI_SBDF(seg, bus, slot, func), - pos + PCI_SRIOV_CTRL); - uint16_t num_vf =3D pci_conf_read16(PCI_SBDF(seg, bus, slot, func), - pos + PCI_SRIOV_NUM_VF); - uint16_t offset =3D pci_conf_read16(PCI_SBDF(seg, bus, slot, func), - pos + PCI_SRIOV_VF_OFFSET); - uint16_t stride =3D pci_conf_read16(PCI_SBDF(seg, bus, slot, func), - pos + PCI_SRIOV_VF_STRIDE); - - if ( !pdev || !pos || + unsigned int pos; + uint16_t ctrl, num_vf, offset, stride; + + if ( !pdev ) + return 0; + + pos =3D pci_find_ext_capability(pdev->sbdf, PCI_EXT_CAP_ID_SRIOV); + ctrl =3D pci_conf_read16(pdev->sbdf, pos + PCI_SRIOV_CTRL); + num_vf =3D pci_conf_read16(pdev->sbdf, pos + PCI_SRIOV_NUM_VF); + offset =3D pci_conf_read16(pdev->sbdf, pos + PCI_SRIOV_VF_OFFSET); + stride =3D pci_conf_read16(pdev->sbdf, pos + PCI_SRIOV_VF_STRIDE); + + if ( !pos || !(ctrl & PCI_SRIOV_CTRL_VFE) || !(ctrl & PCI_SRIOV_CTRL_MSE) || !num_vf || !offset || (num_vf > 1 && !stride) || --=20 2.42.0 From nobody Sun May 19 15:58:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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bh=MJvej4o/mElq6FjgO0ZWLPfwnQd61fY6nEWCZloj5OE=; b=L0yNnOG6af+pbAIvZOfi9IcD7v6TBMDWETAzoT+LL0Ra2n+kdEnC9ED3AjeVwM7Ax0HgQpymYK4Td/DOnGz87yAMsD5zwsitCuJKwDQBFC7XkRXpOigaQ4eQ8AAcA5umcGBqj+2K7ejcvPXrCLYDusZoSMiLtxOt2k9OsMavzz0= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v4 4/6] xen/vpci: header: status register handler Date: Mon, 28 Aug 2023 13:56:52 -0400 Message-ID: <20230828175858.30780-5-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230828175858.30780-1-stewart.hildebrand@amd.com> References: <20230828175858.30780-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3B:EE_|SJ2PR12MB8035:EE_ X-MS-Office365-Filtering-Correlation-Id: 98d8a99c-88b4-4537-af11-08dba7f0e1f6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2023 18:02:02.6993 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98d8a99c-88b4-4537-af11-08dba7f0e1f6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8035 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1693245753325100001 Content-Type: text/plain; charset="utf-8" Introduce a handler for the PCI status register, with ability to mask the capabilities bit. The status register is write-1-to-clear, so introduce han= dling for this type of register in vPCI. The mask_cap_list flag will be set in a follow-on patch. Signed-off-by: Stewart Hildebrand --- v3->v4: * move mask_cap_list setting to the capabilities patch * single pci_conf_read16 in status_read * align mask_cap_list bitfield in struct vpci_header * change to rw1c bit mask instead of treating whole register as rw1c * drop subsystem prefix on renamed add_register function v2->v3: * new patch --- xen/drivers/vpci/header.c | 17 +++++++++++++++++ xen/drivers/vpci/vpci.c | 36 ++++++++++++++++++++++++++++-------- xen/include/xen/vpci.h | 9 +++++++++ 3 files changed, 54 insertions(+), 8 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 767c1ba718d7..dc8c6a66770b 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -413,6 +413,18 @@ static void cf_check cmd_write( pci_conf_write16(pdev->sbdf, reg, cmd); } =20 +static uint32_t cf_check status_read(const struct pci_dev *pdev, + unsigned int reg, void *data) +{ + struct vpci_header *header =3D data; + uint32_t status =3D pci_conf_read16(pdev->sbdf, reg); + + if ( header->mask_cap_list ) + status &=3D ~PCI_STATUS_CAP_LIST; + + return status; +} + static void cf_check bar_write( const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) { @@ -544,6 +556,11 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; =20 + rc =3D vpci_add_rw1c_register(pdev->vpci, status_read, vpci_hw_write16, + PCI_STATUS, 2, header, 0xF900); + if ( rc ) + return rc; + if ( pdev->ignore_bars ) return 0; =20 diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 3bec9a4153da..8b26870a8a2b 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -29,6 +29,7 @@ struct vpci_register { unsigned int offset; void *private; struct list_head node; + uint32_t rw1c_mask; }; =20 #ifdef __XEN__ @@ -145,9 +146,15 @@ uint32_t cf_check vpci_hw_read32( return pci_conf_read32(pdev->sbdf, reg); } =20 -int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, - vpci_write_t *write_handler, unsigned int offset, - unsigned int size, void *data) +void cf_check vpci_hw_write16( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data) +{ + pci_conf_write16(pdev->sbdf, reg, val); +} + +static int add_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data, uint32_t rw1c_mask) { struct list_head *prev; struct vpci_register *r; @@ -167,6 +174,7 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t *r= ead_handler, r->size =3D size; r->offset =3D offset; r->private =3D data; + r->rw1c_mask =3D rw1c_mask; =20 spin_lock(&vpci->lock); =20 @@ -193,6 +201,22 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t *= read_handler, return 0; } =20 +int vpci_add_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offset, + unsigned int size, void *data) +{ + return add_register(vpci, read_handler, write_handler, offset, size, d= ata, + 0); +} + +int vpci_add_rw1c_register(struct vpci *vpci, vpci_read_t *read_handler, + vpci_write_t *write_handler, unsigned int offse= t, + unsigned int size, void *data, uint32_t rw1c_ma= sk) +{ + return add_register(vpci, read_handler, write_handler, offset, size, d= ata, + rw1c_mask); +} + int vpci_remove_register(struct vpci *vpci, unsigned int offset, unsigned int size) { @@ -407,11 +431,6 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, = unsigned int size) =20 /* * Perform a maybe partial write to a register. - * - * Note that this will only work for simple registers, if Xen needs to - * trap accesses to rw1c registers (like the status PCI header register) - * the logic in vpci_write will have to be expanded in order to correctly - * deal with them. */ static void vpci_write_helper(const struct pci_dev *pdev, const struct vpci_register *r, unsigned int = size, @@ -424,6 +443,7 @@ static void vpci_write_helper(const struct pci_dev *pde= v, uint32_t val; =20 val =3D r->read(pdev, r->offset, r->private); + val &=3D ~r->rw1c_mask; data =3D merge_result(val, data, size, offset); } =20 diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 0b8a2a3c745b..51b1b06c2c71 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -37,6 +37,11 @@ int __must_check vpci_add_register(struct vpci *vpci, vpci_write_t *write_handler, unsigned int offset, unsigned int size, void *data); +int __must_check vpci_add_rw1c_register(struct vpci *vpci, + vpci_read_t *read_handler, + vpci_write_t *write_handler, + unsigned int offset, unsigned int = size, + void *data, uint32_t rw1c_mask); int __must_check vpci_remove_register(struct vpci *vpci, unsigned int offs= et, unsigned int size); =20 @@ -50,6 +55,8 @@ uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read32( const struct pci_dev *pdev, unsigned int reg, void *data); +void cf_check vpci_hw_write16( + const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *data= ); =20 /* * Check for pending vPCI operations on this vcpu. Returns true if the vcpu @@ -94,6 +101,8 @@ struct vpci { * upon to know whether BARs are mapped into the guest p2m. */ bool bars_mapped : 1; + /* Store whether to hide all capabilities from the guest. */ + bool mask_cap_list : 1; /* FIXME: currently there's no support for SR-IOV. */ } header; =20 --=20 2.42.0 From nobody Sun May 19 15:58:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1693245794; cv=pass; d=zohomail.com; s=zohoarc; b=doYTdS32mwvBmOHnYq9FsqRzxm2EPTJHqtMoQCiLPI4K6z+43d6rU3ch7gvpz2cLDfKo8DDEZy9hijs3yNN3cZlOLuX4K4OHUQzRiPvQ3cLbuk/rLcVBTzVLGQnFQ0o8gUbSyKxxShbpAFb0UYoX6cambnhYRA0IXoGRTrnEgdA= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; 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bh=dU/f6BYM+t+yAh1uQ1Cq9rU23TlKf83Tj/wjom6+IVU=; b=zCaLUy0h85pU+40YoySWVLeXUBQfRmqoN09nGL7KBFTFTwdE6UY/vWBiE5Tlwysjm1D1FTHK5gS2TJyUzzQy9xcJBnqjHOqbBTXgJDN8rjF1xeP8a6QmQ4cQTNPTvMoA3+OPBkfi7U+ZtzdrTR3d3jkRtTYJl4HLJ0g9Cqy47cg= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [RFC PATCH v4 5/6] xen/vpci: support ro mask Date: Mon, 28 Aug 2023 13:56:53 -0400 Message-ID: <20230828175858.30780-6-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230828175858.30780-1-stewart.hildebrand@amd.com> References: <20230828175858.30780-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3D:EE_|SJ0PR12MB6927:EE_ X-MS-Office365-Filtering-Correlation-Id: 96754622-b765-4e00-c8a8-08dba7f0fb8b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2023 18:02:45.6038 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96754622-b765-4e00-c8a8-08dba7f0fb8b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6927 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1693245795746100001 Content-Type: text/plain; charset="utf-8" Add support for a read-only bit mask for vPCI register handlers. Signed-off-by: Stewart Hildebrand --- v3->v4: * new patch RFC: It seemed like a low-hanging fruit to add support for ro mask. Let me = know what you think, and I could squash it into the status handler patch fo= r the next version of the series. --- xen/drivers/vpci/header.c | 4 ++-- xen/drivers/vpci/vpci.c | 15 ++++++++++----- xen/include/xen/vpci.h | 5 +++-- 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index dc8c6a66770b..4a4dbb69ab1c 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -556,8 +556,8 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; =20 - rc =3D vpci_add_rw1c_register(pdev->vpci, status_read, vpci_hw_write16, - PCI_STATUS, 2, header, 0xF900); + rc =3D vpci_add_register_mask(pdev->vpci, status_read, vpci_hw_write16, + PCI_STATUS, 2, header, 0x06F8, 0xF900); if ( rc ) return rc; =20 diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 8b26870a8a2b..2a67cc516626 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -29,6 +29,7 @@ struct vpci_register { unsigned int offset; void *private; struct list_head node; + uint32_t ro_mask; uint32_t rw1c_mask; }; =20 @@ -154,7 +155,8 @@ void cf_check vpci_hw_write16( =20 static int add_register(struct vpci *vpci, vpci_read_t *read_handler, vpci_write_t *write_handler, unsigned int offset, - unsigned int size, void *data, uint32_t rw1c_mask) + unsigned int size, void *data, uint32_t ro_mask, + uint32_t rw1c_mask) { struct list_head *prev; struct vpci_register *r; @@ -174,6 +176,7 @@ static int add_register(struct vpci *vpci, vpci_read_t = *read_handler, r->size =3D size; r->offset =3D offset; r->private =3D data; + r->ro_mask =3D ro_mask; r->rw1c_mask =3D rw1c_mask; =20 spin_lock(&vpci->lock); @@ -206,15 +209,16 @@ int vpci_add_register(struct vpci *vpci, vpci_read_t = *read_handler, unsigned int size, void *data) { return add_register(vpci, read_handler, write_handler, offset, size, d= ata, - 0); + 0, 0); } =20 -int vpci_add_rw1c_register(struct vpci *vpci, vpci_read_t *read_handler, +int vpci_add_register_mask(struct vpci *vpci, vpci_read_t *read_handler, vpci_write_t *write_handler, unsigned int offse= t, - unsigned int size, void *data, uint32_t rw1c_ma= sk) + unsigned int size, void *data, uint32_t ro_mask, + uint32_t rw1c_mask) { return add_register(vpci, read_handler, write_handler, offset, size, d= ata, - rw1c_mask); + ro_mask, rw1c_mask); } =20 int vpci_remove_register(struct vpci *vpci, unsigned int offset, @@ -447,6 +451,7 @@ static void vpci_write_helper(const struct pci_dev *pde= v, data =3D merge_result(val, data, size, offset); } =20 + data &=3D ~r->ro_mask; r->write(pdev, r->offset, data & (0xffffffffU >> (32 - 8 * r->size)), r->private); } diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 51b1b06c2c71..b0636182d91e 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -37,11 +37,12 @@ int __must_check vpci_add_register(struct vpci *vpci, vpci_write_t *write_handler, unsigned int offset, unsigned int size, void *data); -int __must_check vpci_add_rw1c_register(struct vpci *vpci, +int __must_check vpci_add_register_mask(struct vpci *vpci, vpci_read_t *read_handler, vpci_write_t *write_handler, unsigned int offset, unsigned int = size, - void *data, uint32_t rw1c_mask); + void *data, uint32_t ro_mask, + uint32_t rw1c_mask); int __must_check vpci_remove_register(struct vpci *vpci, unsigned int offs= et, unsigned int size); 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bh=fnedCK7tAR44q7lO/DURZyKyOiN3g7ouC9lxG2A93XY=; b=R7oS/llCM9SDdqAtvA26ZbveqDiGLmdsLHhfJ7nAvbob31JEOxv4ptBxZ7kEpDmDGlwSQ2h0zawaQTG+Jfg2I1Ugxf2Bl4OExQyk2UTz19nbLcnYIAFyhQpnXXA1iFLtqAadDdYsEUTVBZCaD3ihB9L/q7cY72GSI6cCBbsHj2Q= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Andrew Cooper , George Dunlap , "Jan Beulich" , Julien Grall , "Stefano Stabellini" , Wei Liu , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v4 6/6] xen/vpci: header: filter PCI capabilities Date: Mon, 28 Aug 2023 13:56:54 -0400 Message-ID: <20230828175858.30780-7-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230828175858.30780-1-stewart.hildebrand@amd.com> References: <20230828175858.30780-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9DC:EE_|CH2PR12MB4150:EE_ X-MS-Office365-Filtering-Correlation-Id: df6e9dd2-e2e0-4344-4a0c-08dba7f10835 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2023 18:03:06.8630 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df6e9dd2-e2e0-4344-4a0c-08dba7f10835 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4150 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1693245811608100001 Content-Type: text/plain; charset="utf-8" Currently, Xen vPCI only supports virtualizing the MSI and MSI-X capabiliti= es. Hide all other PCI capabilities (including extended capabilities) from domU= s for now, even though there may be certain devices/drivers that depend on being = able to discover certain capabilities. We parse the physical PCI capabilities linked list and add vPCI register handlers for the next elements, inserting our own next value, thus presenti= ng a modified linked list to the domU. Introduce helper functions vpci_hw_read8 and vpci_read_val. The vpci_read_v= al helper function returns a fixed value, which may be used for RAZ registers,= or registers whose value doesn't change. Introduce pci_find_next_cap_ttl() helper while adapting the logic from pci_find_next_cap() to suit our needs, and implement the existing pci_find_next_cap() in terms of the new helper. Signed-off-by: Stewart Hildebrand Reviewed-by: Jan Beulich --- v3->v4: * move mask_cap_list setting to this patch * leave pci_find_next_cap signature alone * use more appropriate types v2->v3: * get rid of > 0 in loop condition * implement pci_find_next_cap in terms of new pci_find_next_cap_ttl functio= n so that hypothetical future callers wouldn't be required to pass &ttl. * change NULL to (void *)0 for RAZ value passed to vpci_read_val * change type of ttl to unsigned int * remember to mask off the low 2 bits of next in the initial loop iteration * change return type of pci_find_next_cap and pci_find_next_cap_ttl * avoid wrapping the PCI_STATUS_CAP_LIST condition by using ! instead of = =3D=3D 0 v1->v2: * change type of ttl to int * use switch statement instead of if/else * adapt existing pci_find_next_cap helper instead of rolling our own * pass ttl as in/out * "pass through" the lower 2 bits of the next pointer * squash helper functions into this patch to avoid transient dead code situ= ation * extended capabilities RAZ/WI --- xen/drivers/pci/pci.c | 31 +++++++++++----- xen/drivers/vpci/header.c | 77 +++++++++++++++++++++++++++++++++++++++ xen/drivers/vpci/vpci.c | 12 ++++++ xen/include/xen/pci.h | 3 ++ xen/include/xen/vpci.h | 5 +++ 5 files changed, 119 insertions(+), 9 deletions(-) diff --git a/xen/drivers/pci/pci.c b/xen/drivers/pci/pci.c index 3569ccb24e9e..733e5e028908 100644 --- a/xen/drivers/pci/pci.c +++ b/xen/drivers/pci/pci.c @@ -39,31 +39,44 @@ unsigned int pci_find_cap_offset(pci_sbdf_t sbdf, unsig= ned int cap) return 0; } =20 -unsigned int pci_find_next_cap(pci_sbdf_t sbdf, unsigned int pos, - unsigned int cap) +unsigned int pci_find_next_cap_ttl(pci_sbdf_t sbdf, unsigned int pos, + bool (*is_match)(unsigned int, unsigned= int), + unsigned int userdata, unsigned int *tt= l) { - u8 id; - int ttl =3D 48; + unsigned int id; =20 - while ( ttl-- ) + while ( (*ttl)-- ) { pos =3D pci_conf_read8(sbdf, pos); if ( pos < 0x40 ) break; =20 - pos &=3D ~3; - id =3D pci_conf_read8(sbdf, pos + PCI_CAP_LIST_ID); + id =3D pci_conf_read8(sbdf, (pos & ~3) + PCI_CAP_LIST_ID); =20 if ( id =3D=3D 0xff ) break; - if ( id =3D=3D cap ) + if ( is_match(id, userdata) ) return pos; =20 - pos +=3D PCI_CAP_LIST_NEXT; + pos =3D (pos & ~3) + PCI_CAP_LIST_NEXT; } + return 0; } =20 +static bool cf_check is_cap_match(unsigned int id1, unsigned int id2) +{ + return id1 =3D=3D id2; +} + +unsigned int pci_find_next_cap(pci_sbdf_t sbdf, unsigned int pos, + unsigned int cap) +{ + unsigned int ttl =3D 48; + + return pci_find_next_cap_ttl(sbdf, pos, is_cap_match, cap, &ttl) & ~3; +} + /** * pci_find_ext_capability - Find an extended capability * @sbdf: PCI device to query diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 4a4dbb69ab1c..919addbfa630 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -525,6 +525,18 @@ static void cf_check rom_write( rom->addr =3D val & PCI_ROM_ADDRESS_MASK; } =20 +static bool cf_check vpci_cap_supported(unsigned int id1, unsigned int id2) +{ + switch ( id1 ) + { + case PCI_CAP_ID_MSI: + case PCI_CAP_ID_MSIX: + return true; + default: + return false; + } +} + static int cf_check init_bars(struct pci_dev *pdev) { uint16_t cmd; @@ -561,6 +573,71 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; =20 + if ( !is_hardware_domain(pdev->domain) ) + { + if ( !(pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LI= ST) ) + { + /* RAZ/WI */ + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, (void *)0); + if ( rc ) + return rc; + } + else + { + /* Only expose capabilities to the guest that vPCI can handle.= */ + uint8_t next; + unsigned int ttl =3D 48; + + next =3D pci_find_next_cap_ttl(pdev->sbdf, PCI_CAPABILITY_LIST, + vpci_cap_supported, 0, &ttl); + + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &=3D ~3; + + if ( !next ) + /* + * If we don't have any supported capabilities to expose t= o the + * guest, mask the PCI_STATUS_CAP_LIST bit in the status + * register. + */ + header->mask_cap_list =3D true; + + while ( next && ttl ) + { + uint8_t pos =3D next; + + next =3D pci_find_next_cap_ttl(pdev->sbdf, + pos + PCI_CAP_LIST_NEXT, + vpci_cap_supported, 0, &ttl); + + rc =3D vpci_add_register(pdev->vpci, vpci_hw_read8, NULL, + pos + PCI_CAP_LIST_ID, 1, NULL); + if ( rc ) + return rc; + + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + pos + PCI_CAP_LIST_NEXT, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &=3D ~3; + } + } + + /* Extended capabilities RAZ/WI */ + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, 0x100, 4, + (void *)0); + if ( rc ) + return rc; + } + if ( pdev->ignore_bars ) return 0; =20 diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 2a67cc516626..25567005d66f 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -135,6 +135,18 @@ static void cf_check vpci_ignored_write( { } =20 +uint32_t cf_check vpci_read_val( + const struct pci_dev *pdev, unsigned int reg, void *data) +{ + return (uintptr_t)data; +} + +uint32_t cf_check vpci_hw_read8( + const struct pci_dev *pdev, unsigned int reg, void *data) +{ + return pci_conf_read8(pdev->sbdf, reg); +} + uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data) { diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index ea6a4c9abf38..50ca2f40acda 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -194,6 +194,9 @@ int pci_mmcfg_read(unsigned int seg, unsigned int bus, int pci_mmcfg_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value); unsigned int pci_find_cap_offset(pci_sbdf_t sbdf, unsigned int cap); +unsigned int pci_find_next_cap_ttl(pci_sbdf_t sbdf, unsigned int pos, + bool (*is_match)(unsigned int, unsigned= int), + unsigned int userdata, unsigned int *tt= l); unsigned int pci_find_next_cap(pci_sbdf_t sbdf, unsigned int pos, unsigned int cap); unsigned int pci_find_ext_capability(pci_sbdf_t sbdf, unsigned int cap); diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index b0636182d91e..a63f2ca8ed56 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -51,7 +51,12 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, un= signed int size); void vpci_write(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, uint32_t data); =20 +uint32_t cf_check vpci_read_val( + const struct pci_dev *pdev, unsigned int reg, void *data); + /* Passthrough handlers. */ +uint32_t cf_check vpci_hw_read8( + const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read32( --=20 2.42.0