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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2023 01:31:50.8806 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 597c7468-e19e-4d5a-3e7e-08dba2af8f4f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5682 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1692667939300100001 Content-Type: text/plain; charset="utf-8" Currently, Xen vPCI only supports virtualizing the MSI and MSI-X capabiliti= es. Hide all other PCI capabilities (including extended capabilities) from domU= s for now, even though there may be certain devices/drivers that depend on being = able to discover certain capabilities. We parse the physical PCI capabilities linked list and add vPCI register handlers for the next elements, inserting our own next value, thus presenti= ng a modified linked list to the domU. Introduce helper functions vpci_hw_read8 and vpci_read_val. The vpci_read_v= al helper function returns a fixed value, which may be used for RAZ registers,= or registers whose value doesn't change. Introduce pci_find_next_cap_ttl() helper while adapting the logic from pci_find_next_cap() to suit our needs, and implement the existing pci_find_next_cap() in terms of the new helper. Signed-off-by: Stewart Hildebrand --- v2->v3: * get rid of > 0 in loop condition * implement pci_find_next_cap in terms of new pci_find_next_cap_ttl functio= n so that hypothetical future callers wouldn't be required to pass &ttl. * change NULL to (void *)0 for RAZ value passed to vpci_read_val * change type of ttl to unsigned int * remember to mask off the low 2 bits of next in the initial loop iteration * change return type of pci_find_next_cap and pci_find_next_cap_ttl * avoid wrapping the PCI_STATUS_CAP_LIST condition by using ! instead of = =3D=3D 0 v1->v2: * change type of ttl to int * use switch statement instead of if/else * adapt existing pci_find_next_cap helper instead of rolling our own * pass ttl as in/out * "pass through" the lower 2 bits of the next pointer * squash helper functions into this patch to avoid transient dead code situ= ation * extended capabilities RAZ/WI --- xen/drivers/pci/pci.c | 24 +++++++++----- xen/drivers/vpci/header.c | 69 +++++++++++++++++++++++++++++++++++++++ xen/drivers/vpci/vpci.c | 12 +++++++ xen/include/xen/pci.h | 5 ++- xen/include/xen/vpci.h | 5 +++ 5 files changed, 106 insertions(+), 9 deletions(-) diff --git a/xen/drivers/pci/pci.c b/xen/drivers/pci/pci.c index 3bcb74040284..f60051694dc5 100644 --- a/xen/drivers/pci/pci.c +++ b/xen/drivers/pci/pci.c @@ -39,30 +39,38 @@ int pci_find_cap_offset(pci_sbdf_t sbdf, u8 cap) return 0; } =20 -int pci_find_next_cap(pci_sbdf_t sbdf, u8 pos, int cap) +uint8_t pci_find_next_cap_ttl(pci_sbdf_t sbdf, uint8_t pos, + bool (*is_match)(uint8_t), unsigned int *ttl) { - u8 id; - int ttl =3D 48; + uint8_t id; =20 - while ( ttl-- ) + while ( (*ttl)-- ) { pos =3D pci_conf_read8(sbdf, pos); if ( pos < 0x40 ) break; =20 - pos &=3D ~3; - id =3D pci_conf_read8(sbdf, pos + PCI_CAP_LIST_ID); + id =3D pci_conf_read8(sbdf, (pos & ~3) + PCI_CAP_LIST_ID); =20 if ( id =3D=3D 0xff ) break; - if ( id =3D=3D cap ) + if ( is_match(id) ) return pos; =20 - pos +=3D PCI_CAP_LIST_NEXT; + pos =3D (pos & ~3) + PCI_CAP_LIST_NEXT; } + return 0; } =20 +uint8_t pci_find_next_cap(pci_sbdf_t sbdf, uint8_t pos, + bool (*is_match)(uint8_t)) +{ + unsigned int ttl =3D 48; + + return pci_find_next_cap_ttl(sbdf, pos, is_match, &ttl) & ~3; +} + /** * pci_find_ext_capability - Find an extended capability * @sbdf: PCI device to query diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 60f7049e3498..b531ab03cec1 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -513,6 +513,18 @@ static void cf_check rom_write( rom->addr =3D val & PCI_ROM_ADDRESS_MASK; } =20 +static bool cf_check vpci_cap_supported(uint8_t id) +{ + switch ( id ) + { + case PCI_CAP_ID_MSI: + case PCI_CAP_ID_MSIX: + return true; + default: + return false; + } +} + static int cf_check init_bars(struct pci_dev *pdev) { uint16_t cmd; @@ -544,6 +556,63 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; =20 + if ( !is_hardware_domain(pdev->domain) ) + { + if ( !(pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LI= ST) ) + { + /* RAZ/WI */ + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, (void *)0); + if ( rc ) + return rc; + } + else + { + /* Only expose capabilities to the guest that vPCI can handle.= */ + uint8_t next; + unsigned int ttl =3D 48; + + next =3D pci_find_next_cap_ttl(pdev->sbdf, PCI_CAPABILITY_LIST, + vpci_cap_supported, &ttl); + + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &=3D ~3; + + while ( next && ttl ) + { + uint8_t pos =3D next; + + next =3D pci_find_next_cap_ttl(pdev->sbdf, + pos + PCI_CAP_LIST_NEXT, + vpci_cap_supported, &ttl); + + rc =3D vpci_add_register(pdev->vpci, vpci_hw_read8, NULL, + pos + PCI_CAP_LIST_ID, 1, NULL); + if ( rc ) + return rc; + + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + pos + PCI_CAP_LIST_NEXT, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &=3D ~3; + } + } + + /* Extended capabilities RAZ/WI */ + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, 0x100, 4, + (void *)0); + if ( rc ) + return rc; + } + if ( pdev->ignore_bars ) return 0; =20 diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index d73fa7630237..4a96aa50494d 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -133,6 +133,18 @@ static void cf_check vpci_ignored_write( { } =20 +uint32_t cf_check vpci_read_val( + const struct pci_dev *pdev, unsigned int reg, void *data) +{ + return (uintptr_t)data; +} + +uint32_t cf_check vpci_hw_read8( + const struct pci_dev *pdev, unsigned int reg, void *data) +{ + return pci_conf_read8(pdev->sbdf, reg); +} + uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data) { diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index 8a482b15745c..b30034ecccba 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -194,7 +194,10 @@ int pci_mmcfg_read(unsigned int seg, unsigned int bus, int pci_mmcfg_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value); int pci_find_cap_offset(pci_sbdf_t sbdf, u8 cap); -int pci_find_next_cap(pci_sbdf_t sbdf, u8 pos, int cap); +uint8_t pci_find_next_cap_ttl(pci_sbdf_t sbdf, uint8_t pos, + bool (*is_match)(uint8_t), unsigned int *ttl= ); +uint8_t pci_find_next_cap(pci_sbdf_t sbdf, uint8_t pos, + bool (*is_match)(uint8_t)); int pci_find_ext_capability(pci_sbdf_t sbdf, int cap); int pci_find_next_ext_capability(pci_sbdf_t sbdf, int start, int cap); const char *parse_pci(const char *, unsigned int *seg, unsigned int *bus, diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 0b8a2a3c745b..17fd252746ec 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -45,7 +45,12 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, un= signed int size); void vpci_write(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, uint32_t data); =20 +uint32_t cf_check vpci_read_val( + const struct pci_dev *pdev, unsigned int reg, void *data); + /* Passthrough handlers. */ +uint32_t cf_check vpci_hw_read8( + const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data); uint32_t cf_check vpci_hw_read32( --=20 2.41.0