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bh=ql0jXnI4Ipxpt1/ru8/r0InDW4bpinHGzCTrC/z1SG0=; b=q4DjQN0KHKbVMExxviZK4YbXiPqO1m1TmJTAmHtuC9DIGdBWYUR2hAL62RwWOjkRzp04UbPeO47l0+1/x4s2Plhc3+Gjet3GOCsa0mHV/kJdhh4hQZzwFE2maZSlZ8nOzHlVBYRRUHGPbDNVz0aeSxuy0FZFzd2ViMz8ZGSKj7c= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Andrew Cooper , George Dunlap , "Jan Beulich" , Julien Grall , "Stefano Stabellini" , Wei Liu , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 1/2] xen/vpci: header: filter PCI capabilities Date: Wed, 16 Aug 2023 14:50:28 -0400 Message-ID: <20230816185035.82994-2-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230816185035.82994-1-stewart.hildebrand@amd.com> References: <20230816185035.82994-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CD:EE_|IA0PR12MB8228:EE_ X-MS-Office365-Filtering-Correlation-Id: e5f36781-430f-4155-16b9-08db9e89cbaf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mI8ir1tV92IwWvqhi3F8PB11XQVcsMhYFtEzMioeqyq++l5b3uwcFM2BhS5LBg+8XhrMkrIGSMTw1MZMedEBGM20pm3jhJP2h9dtHLKpOCwnXVMfE70tBMzRTB58qI8hctw52+bZ8NEuUg2zlXOUjyBGSfVCK3EwaLxy6LqB10P/M26tI+ByKhfA+Wk2Rci1PsG1iPylysxIxMx7BxOCaQodT5GxhB/IxgUorXpedbo+BhILPr3g5oBYmp1MSolEzNnaQ3WxQMG5chhqsbrr2ofRpIUssY9UDFdL1DwZiRc6QBmzerghCaPi30iS8Qi3yxh9xAOUu0tOo4DKyHIUZPB0p7r7QT1GXa0ZRestdN2BpGVvqk7mKfBdiTi00DxV+kPfP6ja62+mYOMeF3SjwkckDrJFDdf6w+PeMpjmaDTxeG07AY+uJHbVvlswh+/sfOUXUGy/XY+PlTPeFU6N23INE8JXgqG2urptHgNEvHPH8YpVLCyvIH6WIQPttXpDQ/dLCSbP/uIu7Jv3KV10qkFH9s405mJVDkdy0Y3vh895lwivI3AjO2IQF0zhkzgcoX++CyXmf2cxlY+NEAseIl+XWeVM9FBxOgVV6PxHWNsez2CJhrj6UuRrGGIeYTwwSkzQ9F1YjBjIuK6dWxoKRLIglSo5Qb8KOmqTphOsZhudjSuY9sJSybDG3pzRq2KkHUhLX9C4cnOjw2jhNbao59mRj0AAwJ5oR67f+UeNr3ESqC3BSDsgmYr/vGo6VfRraeWd2chZetpBKCYEET4aeA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(396003)(346002)(39860400002)(376002)(1800799009)(451199024)(82310400011)(186009)(40470700004)(36840700001)(46966006)(2906002)(40460700003)(83380400001)(86362001)(40480700001)(478600001)(426003)(336012)(36756003)(2616005)(1076003)(26005)(966005)(44832011)(5660300002)(36860700001)(41300700001)(356005)(54906003)(82740400003)(316002)(81166007)(70206006)(70586007)(6916009)(8676002)(8936002)(4326008)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2023 18:51:26.7389 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e5f36781-430f-4155-16b9-08db9e89cbaf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8228 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1692211916012100001 Content-Type: text/plain; charset="utf-8" Currently, Xen vPCI only supports virtualizing the MSI and MSI-X capabiliti= es. Hide all other PCI capabilities (including extended capabilities) from domU= s for now, even though there may be certain devices/drivers that depend on being = able to discover certain capabilities. We parse the physical PCI capabilities linked list and add vPCI register handlers for the next elements, inserting our own next value, thus presenti= ng a modified linked list to the domU. Introduce helper functions vpci_hw_read8 and vpci_read_val. The vpci_read_v= al helper function returns a fixed value, which may be used for RAZ registers,= or registers whose value doesn't change. Adapt pci_find_next_cap() to suit our needs, which has no existing callers. Signed-off-by: Stewart Hildebrand --- If there are no capabilities to be exposed to the guest, a future status register handler likely would want to mask the PCI_STATUS_CAP_LIST bit. See= [1] for a suggestion of how this might be tracked in struct vpci_header. RFC: I'm not a fan of the (void *)(uintptr_t) cast for passing a value to vpci_read_val, but without the cast, the only alternative I could thin= k of would be to introduce a new memory allocation. See the next patch for = an example of what this might look like. v1->v2: * change type of ttl to int * use switch statement instead of if/else * adapt existing pci_find_next_cap helper instead of rolling our own * pass ttl as in/out * "pass through" the lower 2 bits of the next pointer * squash helper functions into this patch to avoid transient dead code situ= ation * extended capabilities RAZ/WI [1] https://lists.xenproject.org/archives/html/xen-devel/2023-08/msg01173.h= tml --- xen/drivers/pci/pci.c | 18 +++++------ xen/drivers/vpci/header.c | 66 +++++++++++++++++++++++++++++++++++++++ xen/drivers/vpci/vpci.c | 12 +++++++ xen/include/xen/pci.h | 3 +- xen/include/xen/vpci.h | 5 +++ 5 files changed, 94 insertions(+), 10 deletions(-) diff --git a/xen/drivers/pci/pci.c b/xen/drivers/pci/pci.c index e411876a1518..fbebbe4a872a 100644 --- a/xen/drivers/pci/pci.c +++ b/xen/drivers/pci/pci.c @@ -39,27 +39,27 @@ int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 fun= c, u8 cap) return 0; } =20 -int pci_find_next_cap(u16 seg, u8 bus, unsigned int devfn, u8 pos, int cap) +int pci_find_next_cap(pci_sbdf_t sbdf, uint8_t pos, bool (*is_match)(uint8= _t), + int *ttl) { - u8 id; - int ttl =3D 48; + uint8_t id; =20 - while ( ttl-- ) + while ( (*ttl)-- > 0 ) { - pos =3D pci_conf_read8(PCI_SBDF(seg, bus, devfn), pos); + pos =3D pci_conf_read8(sbdf, pos); if ( pos < 0x40 ) break; =20 - pos &=3D ~3; - id =3D pci_conf_read8(PCI_SBDF(seg, bus, devfn), pos + PCI_CAP_LIS= T_ID); + id =3D pci_conf_read8(sbdf, (pos & ~3) + PCI_CAP_LIST_ID); =20 if ( id =3D=3D 0xff ) break; - if ( id =3D=3D cap ) + if ( is_match(id) ) return pos; =20 - pos +=3D PCI_CAP_LIST_NEXT; + pos =3D (pos & ~3) + PCI_CAP_LIST_NEXT; } + return 0; } =20 diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 60f7049e3498..ec5947300198 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -513,6 +513,18 @@ static void cf_check rom_write( rom->addr =3D val & PCI_ROM_ADDRESS_MASK; } =20 +static bool cf_check vpci_cap_supported(uint8_t id) +{ + switch ( id ) + { + case PCI_CAP_ID_MSI: + case PCI_CAP_ID_MSIX: + return true; + default: + return false; + } +} + static int cf_check init_bars(struct pci_dev *pdev) { uint16_t cmd; @@ -544,6 +556,60 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; =20 + if ( !is_hardware_domain(pdev->domain) ) + { + if ( (pci_conf_read16(pdev->sbdf, PCI_STATUS) & PCI_STATUS_CAP_LIS= T) + =3D=3D 0 ) + { + /* RAZ/WI */ + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, NULL); + if ( rc ) + return rc; + } + else + { + /* Only expose capabilities to the guest that vPCI can handle.= */ + uint8_t next; + int ttl =3D 48; + + next =3D pci_find_next_cap(pdev->sbdf, PCI_CAPABILITY_LIST, + vpci_cap_supported, &ttl); + + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + PCI_CAPABILITY_LIST, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + while ( next && (ttl > 0) ) + { + uint8_t pos =3D next; + + next =3D pci_find_next_cap(pdev->sbdf, pos + PCI_CAP_LIST_= NEXT, + vpci_cap_supported, &ttl); + + rc =3D vpci_add_register(pdev->vpci, vpci_hw_read8, NULL, + pos + PCI_CAP_LIST_ID, 1, NULL); + if ( rc ) + return rc; + + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, + pos + PCI_CAP_LIST_NEXT, 1, + (void *)(uintptr_t)next); + if ( rc ) + return rc; + + next &=3D ~3; + } + } + + /* Extended capabilities RAZ/WI */ + rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, 0x100, 4= , NULL); + if ( rc ) + return rc; + } + if ( pdev->ignore_bars ) return 0; =20 diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index d73fa7630237..4a96aa50494d 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -133,6 +133,18 @@ static void cf_check vpci_ignored_write( { } =20 +uint32_t cf_check vpci_read_val( + const struct pci_dev *pdev, unsigned int reg, void *data) +{ + return (uintptr_t)data; +} + +uint32_t cf_check vpci_hw_read8( + const struct pci_dev *pdev, unsigned int reg, void *data) +{ + return pci_conf_read8(pdev->sbdf, reg); +} + uint32_t cf_check vpci_hw_read16( const struct pci_dev *pdev, unsigned int reg, void *data) { diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index 5975ca2f3032..57792282108b 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -194,7 +194,8 @@ int pci_mmcfg_read(unsigned int seg, unsigned int bus, int pci_mmcfg_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value); int pci_find_cap_offset(u16 seg, u8 bus, u8 dev, u8 func, u8 cap); -int pci_find_next_cap(u16 seg, u8 bus, unsigned int devfn, u8 pos, int cap= ); +int pci_find_next_cap(pci_sbdf_t sbdf, uint8_t pos, bool (*is_match)(uint8= _t), + int *ttl); int pci_find_ext_capability(int seg, int bus, int devfn, int cap); int pci_find_next_ext_capability(int seg, int bus, int devfn, int pos, int= cap); const char *parse_pci(const char *, unsigned int *seg, unsigned int *bus, diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 0b8a2a3c745b..17fd252746ec 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -45,7 +45,12 @@ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, un= signed int size); void vpci_write(pci_sbdf_t sbdf, unsigned int reg, unsigned int size, uint32_t data); =20 +uint32_t cf_check vpci_read_val( + const struct pci_dev *pdev, unsigned int reg, void *data); + /* Passthrough handlers. */ +uint32_t cf_check vpci_hw_read8( + const struct pci_dev *pdev, unsigned int reg, void *data); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2023 18:51:47.6185 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 47cbac96-559f-497b-346c-08db9e89d828 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9030 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1692211938057100001 Content-Type: text/plain; charset="utf-8" The only purpose of this is to give an idea of what it might look like to introduce a new memory allocation in order to get rid of the casts for the = value passed to vpci_read_val. If this is deemed preferable vs the casts, I will squash it for the next version of the series. Signed-off-by: Stewart Hildebrand --- v1->v2: * new patch --- xen/drivers/vpci/header.c | 13 ++++++++++--- xen/drivers/vpci/vpci.c | 8 +++++++- xen/include/xen/vpci.h | 3 +++ 3 files changed, 20 insertions(+), 4 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index ec5947300198..ae269a0b4bbc 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -571,14 +571,19 @@ static int cf_check init_bars(struct pci_dev *pdev) { /* Only expose capabilities to the guest that vPCI can handle.= */ uint8_t next; - int ttl =3D 48; + int ttl =3D 48, i =3D 0; + + header->caps_list =3D xzalloc_array(uint8_t, ttl); + if ( !header->caps_list ) + return -ENOMEM; =20 next =3D pci_find_next_cap(pdev->sbdf, PCI_CAPABILITY_LIST, vpci_cap_supported, &ttl); =20 + header->caps_list[i] =3D next; rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, PCI_CAPABILITY_LIST, 1, - (void *)(uintptr_t)next); + &header->caps_list[i]); if ( rc ) return rc; =20 @@ -594,9 +599,11 @@ static int cf_check init_bars(struct pci_dev *pdev) if ( rc ) return rc; =20 + i++; + header->caps_list[i] =3D next; rc =3D vpci_add_register(pdev->vpci, vpci_read_val, NULL, pos + PCI_CAP_LIST_NEXT, 1, - (void *)(uintptr_t)next); + &header->caps_list[i]); if ( rc ) return rc; =20 diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 4a96aa50494d..717340b8fbe8 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -61,6 +61,7 @@ void vpci_remove_device(struct pci_dev *pdev) if ( pdev->vpci->msix->table[i] ) iounmap(pdev->vpci->msix->table[i]); } + xfree(pdev->vpci->header.caps_list); xfree(pdev->vpci->msix); xfree(pdev->vpci->msi); xfree(pdev->vpci); @@ -136,7 +137,12 @@ static void cf_check vpci_ignored_write( uint32_t cf_check vpci_read_val( const struct pci_dev *pdev, unsigned int reg, void *data) { - return (uintptr_t)data; + uint8_t *val =3D data; + + if ( val ) + return *val; + + return 0; } =20 uint32_t cf_check vpci_hw_read8( diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 17fd252746ec..7cdee84b5123 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -88,6 +88,9 @@ struct vpci { } bars[PCI_HEADER_NORMAL_NR_BARS + 1]; /* At most 6 BARS + 1 expansion ROM BAR. */ =20 + /* Guest view of capabilities next pointers. */ + uint8_t *caps_list; + /* * Store whether the ROM enable bit is set (doesn't imply ROM BAR * is mapped into guest p2m) if there's a ROM BAR on the device. --=20 2.41.0