From nobody Thu Oct 23 00:40:37 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1687750885254273.4033804827062; Sun, 25 Jun 2023 20:41:25 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.555101.866885 (Exim 4.92) (envelope-from ) id 1qDd5s-0005J1-EM; Mon, 26 Jun 2023 03:40:48 +0000 Received: by outflank-mailman (output) from mailman id 555101.866885; Mon, 26 Jun 2023 03:40:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qDd5r-0005Cr-OS; Mon, 26 Jun 2023 03:40:47 +0000 Received: by outflank-mailman (input) for mailman id 555101; Mon, 26 Jun 2023 03:40:44 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qDd1z-0000HH-Su for xen-devel@lists.xenproject.org; Mon, 26 Jun 2023 03:36:47 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-flk1.inumbo.com (Halon) with ESMTP id acb2b9d8-13d2-11ee-8611-37d641c3527e; Mon, 26 Jun 2023 05:36:45 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5FEB22F4; Sun, 25 Jun 2023 20:37:29 -0700 (PDT) Received: from a011292.shanghai.arm.com (a011292.shanghai.arm.com [10.169.190.94]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B83B73F64C; Sun, 25 Jun 2023 20:36:42 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: acb2b9d8-13d2-11ee-8611-37d641c3527e From: Penny Zheng To: xen-devel@lists.xenproject.org Cc: Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Penny Zheng , Wei Chen Subject: [PATCH v3 31/52] xen/mpu: make early_fdt_map support in MPU systems Date: Mon, 26 Jun 2023 11:34:22 +0800 Message-Id: <20230626033443.2943270-32-Penny.Zheng@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230626033443.2943270-1-Penny.Zheng@arm.com> References: <20230626033443.2943270-1-Penny.Zheng@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1687750886212100001 Content-Type: text/plain; charset="utf-8" In MPU system, MPU memory region is always mapped PAGE_ALIGN, so in order to not access unexpected memory area, dtb section in xen.lds.S should be made page-aligned too. We add . =3D ALIGN(PAGE_SIZE); in the head of dtb section to make it happen. In this commit, we map early FDT with a transient MPU memory region, as it will be relocated into heap and unmapped at the end of boot. Signed-off-by: Penny Zheng Signed-off-by: Wei Chen --- v3: - map the first 2MB. Check the size and then re-map with an extra 2MB if ne= eded --- xen/arch/arm/include/asm/arm64/mpu.h | 3 ++- xen/arch/arm/include/asm/page.h | 5 +++++ xen/arch/arm/mm.c | 26 ++++++++++++++++++++------ xen/arch/arm/mpu/mm.c | 1 + xen/arch/arm/xen.lds.S | 5 ++++- 5 files changed, 32 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/as= m/arm64/mpu.h index a6b07bab02..715ea69884 100644 --- a/xen/arch/arm/include/asm/arm64/mpu.h +++ b/xen/arch/arm/include/asm/arm64/mpu.h @@ -72,7 +72,8 @@ typedef union { unsigned long ns:1; /* Not-Secure */ unsigned long res:1; /* Reserved 0 by hardware */ unsigned long limit:42; /* Limit Address */ - unsigned long pad:16; + unsigned long pad:15; + unsigned long tran:1; /* Transient region */ } reg; uint64_t bits; } prlar_t; diff --git a/xen/arch/arm/include/asm/page.h b/xen/arch/arm/include/asm/pag= e.h index 85ecd5e4de..a434e2205a 100644 --- a/xen/arch/arm/include/asm/page.h +++ b/xen/arch/arm/include/asm/page.h @@ -97,19 +97,24 @@ * [3:4] Execute Never * [5:6] Access Permission * [7] Region Present + * [8] Transient Region, e.g. MPU memory region is temproraily + * mapped for a short time */ #define _PAGE_AI_BIT 0 #define _PAGE_XN_BIT 3 #define _PAGE_AP_BIT 5 #define _PAGE_PRESENT_BIT 7 +#define _PAGE_TRANSIENT_BIT 8 #define _PAGE_AI (7U << _PAGE_AI_BIT) #define _PAGE_XN (2U << _PAGE_XN_BIT) #define _PAGE_RO (2U << _PAGE_AP_BIT) #define _PAGE_PRESENT (1U << _PAGE_PRESENT_BIT) +#define _PAGE_TRANSIENT (1U << _PAGE_TRANSIENT_BIT) #define PAGE_AI_MASK(x) (((x) >> _PAGE_AI_BIT) & 0x7U) #define PAGE_XN_MASK(x) (((x) >> _PAGE_XN_BIT) & 0x3U) #define PAGE_AP_MASK(x) (((x) >> _PAGE_AP_BIT) & 0x3U) #define PAGE_RO_MASK(x) (((x) >> _PAGE_AP_BIT) & 0x2U) +#define PAGE_TRANSIENT_MASK(x) (((x) >> _PAGE_TRANSIENT_BIT) & 0x1U) #endif /* CONFIG_HAS_MPU */ =20 /* diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index d35e7e280f..8625066256 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -61,8 +61,17 @@ void flush_page_to_ram(unsigned long mfn, bool sync_icac= he) =20 void * __init early_fdt_map(paddr_t fdt_paddr) { +#ifndef CONFIG_HAS_MPU /* We are using 2MB superpage for mapping the FDT */ paddr_t base_paddr =3D fdt_paddr & SECOND_MASK; + unsigned int flags =3D PAGE_HYPERVISOR_RO | _PAGE_BLOCK; + unsigned long base_virt =3D BOOT_FDT_VIRT_START; +#else + /* MPU region must be PAGE aligned */ + paddr_t base_paddr =3D fdt_paddr & PAGE_MASK; + unsigned int flags =3D PAGE_HYPERVISOR_RO | _PAGE_TRANSIENT; + unsigned long base_virt =3D ~0UL; +#endif paddr_t offset; void *fdt_virt; uint32_t size; @@ -79,18 +88,24 @@ void * __init early_fdt_map(paddr_t fdt_paddr) if ( !fdt_paddr || fdt_paddr % MIN_FDT_ALIGN ) return NULL; =20 +#ifndef CONFIG_HAS_MPU /* The FDT is mapped using 2MB superpage */ BUILD_BUG_ON(BOOT_FDT_VIRT_START % SZ_2M); +#endif =20 - rc =3D map_pages_to_xen(BOOT_FDT_VIRT_START, maddr_to_mfn(base_paddr), - SZ_2M >> PAGE_SHIFT, - PAGE_HYPERVISOR_RO | _PAGE_BLOCK); + rc =3D map_pages_to_xen(base_virt, maddr_to_mfn(base_paddr), + SZ_2M >> PAGE_SHIFT, flags); if ( rc ) panic("Unable to map the device-tree.\n"); =20 =20 +#ifndef CONFIG_HAS_MPU offset =3D fdt_paddr % SECOND_SIZE; fdt_virt =3D (void *)BOOT_FDT_VIRT_START + offset; +#else + offset =3D fdt_paddr % PAGE_SIZE; + fdt_virt =3D (void *)fdt_paddr; +#endif =20 if ( fdt_magic(fdt_virt) !=3D FDT_MAGIC ) return NULL; @@ -101,10 +116,9 @@ void * __init early_fdt_map(paddr_t fdt_paddr) =20 if ( (offset + size) > SZ_2M ) { - rc =3D map_pages_to_xen(BOOT_FDT_VIRT_START + SZ_2M, + rc =3D map_pages_to_xen(base_virt + SZ_2M, maddr_to_mfn(base_paddr + SZ_2M), - SZ_2M >> PAGE_SHIFT, - PAGE_HYPERVISOR_RO | _PAGE_BLOCK); + SZ_2M >> PAGE_SHIFT, flags); if ( rc ) panic("Unable to map the device-tree\n"); } diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 14a1309ca1..f4ce19d36a 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -448,6 +448,7 @@ static int xen_mpumap_update_entry(paddr_t base, paddr_= t limit, /* Set permission */ xen_mpumap[idx].prbar.reg.ap =3D PAGE_AP_MASK(flags); xen_mpumap[idx].prbar.reg.xn =3D PAGE_XN_MASK(flags); + xen_mpumap[idx].prlar.reg.tran =3D PAGE_TRANSIENT_MASK(flags); =20 write_protection_region((const pr_t*)(&xen_mpumap[idx]), idx); } diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S index 4f7daa7dca..f2715d7cb7 100644 --- a/xen/arch/arm/xen.lds.S +++ b/xen/arch/arm/xen.lds.S @@ -216,7 +216,10 @@ SECTIONS _end =3D . ; =20 /* Section for the device tree blob (if any). */ - .dtb : { *(.dtb) } :text + .dtb : { + . =3D ALIGN(PAGE_SIZE); + *(.dtb) + } :text =20 DWARF2_DEBUG_SECTIONS =20 --=20 2.25.1