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Sat, 24 Jun 2023 10:42:46 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Marcel Apfelbaum , Peter Maydell , Roman Bolshakov , qemu-arm@nongnu.org, Richard Henderson , Alexander Graf , xen-devel@lists.xenproject.org, Sunil Muthuswamy , Anthony Perard , Stefano Stabellini , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Durrant , Reinoud Zandijk , Eduardo Habkost , Cameron Esfahani , Paolo Bonzini Subject: [PATCH v3 11/16] accel: Inline NVMM get_qemu_vcpu() Date: Sat, 24 Jun 2023 19:41:16 +0200 Message-Id: <20230624174121.11508-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230624174121.11508-1-philmd@linaro.org> References: <20230624174121.11508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687628672326100001 No need for this helper to access the CPUState::accel field. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/nvmm/nvmm-all.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index e5ee4af084..72a3a9e3ae 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -49,12 +49,6 @@ struct qemu_machine { static bool nvmm_allowed; static struct qemu_machine qemu_mach; =20 -static AccelCPUState * -get_qemu_vcpu(CPUState *cpu) -{ - return cpu->accel; -} - static struct nvmm_machine * get_nvmm_mach(void) { @@ -86,7 +80,7 @@ nvmm_set_registers(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_x64_state *state =3D vcpu->state; uint64_t bitmap; @@ -223,7 +217,7 @@ nvmm_get_registers(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -347,7 +341,7 @@ static bool nvmm_can_take_int(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_machine *mach =3D get_nvmm_mach(); =20 @@ -372,7 +366,7 @@ nvmm_can_take_int(CPUState *cpu) static bool nvmm_can_take_nmi(CPUState *cpu) { - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; =20 /* * Contrary to INTs, NMIs always schedule an exit when they are @@ -395,7 +389,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -478,7 +472,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) static void nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit) { - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); uint64_t tpr; @@ -565,7 +559,7 @@ static int nvmm_handle_rdmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -610,7 +604,7 @@ static int nvmm_handle_wrmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -686,7 +680,7 @@ nvmm_vcpu_loop(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_vcpu_exit *exit =3D vcpu->exit; @@ -892,7 +886,7 @@ static void nvmm_ipi_signal(int sigcpu) { if (current_cpu) { - AccelCPUState *qcpu =3D get_qemu_vcpu(current_cpu); + AccelCPUState *qcpu =3D current_cpu->accel; #if NVMM_USER_VERSION >=3D 2 struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; nvmm_vcpu_stop(vcpu); @@ -1023,7 +1017,7 @@ void nvmm_destroy_vcpu(CPUState *cpu) { struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; =20 nvmm_vcpu_destroy(mach, &qcpu->vcpu); g_free(cpu->accel); --=20 2.38.1