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(Reorder Taylor's line to keep the section sorted alphabetically). Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 4 ++-- .mailmap | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 7f323cd2eb..1da135b0c8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -497,14 +497,14 @@ F: target/arm/hvf/ =20 X86 HVF CPUs M: Cameron Esfahani -M: Roman Bolshakov +M: Roman Bolshakov W: https://wiki.qemu.org/Features/HVF S: Maintained F: target/i386/hvf/ =20 HVF M: Cameron Esfahani -M: Roman Bolshakov +M: Roman Bolshakov W: https://wiki.qemu.org/Features/HVF S: Maintained F: accel/hvf/ diff --git a/.mailmap b/.mailmap index b57da4827e..64ef9f4de6 100644 --- a/.mailmap +++ b/.mailmap @@ -76,9 +76,10 @@ Paul Burton Philippe Mathieu-Daud=C3=A9 Philippe Mathieu-Daud=C3=A9 Philippe Mathieu-Daud=C3=A9 +Roman Bolshakov Stefan Brankovic -Yongbok Kim Taylor Simpson +Yongbok Kim =20 # Also list preferred name forms where people have changed their # git author config, or had utf8/latin1 encoding issues. --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687450156; cv=none; d=zohomail.com; s=zohoarc; b=mvpDbFTHcGlIdGKc9W+tjoY8YuDbHOyNiAOU1gbrrOkcKjfGLgEaWOiqWpaTAZuPf4XG6mzbEFXSvcswgHakufOxyiZ06+BOKadA/CLT3ok3kGkZR0erwbfpuVtDB3Ybo5C/fgkRb9F4ISq8EgDBI8YkXKtmHXFhCR4sjGRNEas= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687450156; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xHLdIwIywOmneOj5eUp5g6ra2t5DF15QteoMLknkUnc=; b=e5QY7mVR2+MBV8lN1VjWEA3b6s2bRbxBOgCoXAx/BEnIT5obz+lDC0Q1ICzfe5Mag4R1XseUMXIhioxx5cJipGskZZJEnGfR8Gd1pjl6l7We2O0guqJrkuXlElRREMSX0RtxaPxP+DQ66Fd1q+WMGh7Jd2eaKULYYx8ApPzd8kQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 16874501565511000.8550725701618; Thu, 22 Jun 2023 09:09:16 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.553733.864481 (Exim 4.92) (envelope-from ) id 1qCMrd-0001tV-HH; Thu, 22 Jun 2023 16:08:53 +0000 Received: by outflank-mailman (output) from mailman id 553733.864481; Thu, 22 Jun 2023 16:08:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qCMrd-0001tM-Ds; Thu, 22 Jun 2023 16:08:53 +0000 Received: by outflank-mailman (input) for mailman id 553733; Thu, 22 Jun 2023 16:08:51 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qCMrb-0001Gi-J9 for xen-devel@lists.xenproject.org; Thu, 22 Jun 2023 16:08:51 +0000 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [2a00:1450:4864:20::429]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 13c3fd8d-1117-11ee-b237-6b7b168915f2; Thu, 22 Jun 2023 18:08:51 +0200 (CEST) Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3112f256941so5271924f8f.1 for ; Thu, 22 Jun 2023 09:08:51 -0700 (PDT) Received: from localhost.localdomain (230.red-88-28-3.dynamicip.rima-tde.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Richard Henderson --- include/sysemu/hax.h | 2 ++ include/sysemu/kvm.h | 2 ++ include/sysemu/nvmm.h | 2 ++ include/sysemu/tcg.h | 2 ++ include/sysemu/whpx.h | 2 ++ include/sysemu/xen.h | 2 ++ 6 files changed, 12 insertions(+) diff --git a/include/sysemu/hax.h b/include/sysemu/hax.h index bf8f99a824..80fc716f80 100644 --- a/include/sysemu/hax.h +++ b/include/sysemu/hax.h @@ -19,6 +19,8 @@ * */ =20 +/* header to be included in non-HAX-specific code */ + #ifndef QEMU_HAX_H #define QEMU_HAX_H =20 diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 88f5ccfbce..7902acdfd9 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -11,6 +11,8 @@ * */ =20 +/* header to be included in non-KVM-specific code */ + #ifndef QEMU_KVM_H #define QEMU_KVM_H =20 diff --git a/include/sysemu/nvmm.h b/include/sysemu/nvmm.h index 833670fccb..be7bc9a62d 100644 --- a/include/sysemu/nvmm.h +++ b/include/sysemu/nvmm.h @@ -7,6 +7,8 @@ * See the COPYING file in the top-level directory. */ =20 +/* header to be included in non-NVMM-specific code */ + #ifndef QEMU_NVMM_H #define QEMU_NVMM_H =20 diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index 53352450ff..5e2ca9aab3 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -5,6 +5,8 @@ * See the COPYING file in the top-level directory. */ =20 +/* header to be included in non-TCG-specific code */ + #ifndef SYSEMU_TCG_H #define SYSEMU_TCG_H =20 diff --git a/include/sysemu/whpx.h b/include/sysemu/whpx.h index 2889fa2278..781ca5b2b6 100644 --- a/include/sysemu/whpx.h +++ b/include/sysemu/whpx.h @@ -10,6 +10,8 @@ * */ =20 +/* header to be included in non-WHPX-specific code */ + #ifndef QEMU_WHPX_H #define QEMU_WHPX_H =20 diff --git a/include/sysemu/xen.h b/include/sysemu/xen.h index 0ca25697e4..bc13ad5692 100644 --- a/include/sysemu/xen.h +++ b/include/sysemu/xen.h @@ -5,6 +5,8 @@ * See the COPYING file in the top-level directory. */ =20 +/* header to be included in non-Xen-specific code */ + #ifndef SYSEMU_XEN_H #define SYSEMU_XEN_H =20 --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/tcg-accel-ops-mttcg.c | 4 ---- accel/tcg/tcg-accel-ops-rr.c | 3 --- target/i386/whpx/whpx-accel-ops.c | 3 --- 3 files changed, 10 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttc= g.c index b320ff0037..b276262007 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -152,8 +152,4 @@ void mttcg_start_vcpu_thread(CPUState *cpu) =20 qemu_thread_create(cpu->thread, thread_name, mttcg_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); - -#ifdef _WIN32 - cpu->hThread =3D qemu_thread_get_handle(cpu->thread); -#endif } diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 23e4d0f452..2d523289a8 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -329,9 +329,6 @@ void rr_start_vcpu_thread(CPUState *cpu) =20 single_tcg_halt_cond =3D cpu->halt_cond; single_tcg_cpu_thread =3D cpu->thread; -#ifdef _WIN32 - cpu->hThread =3D qemu_thread_get_handle(cpu->thread); -#endif } else { /* we share the thread */ cpu->thread =3D single_tcg_cpu_thread; diff --git a/target/i386/whpx/whpx-accel-ops.c b/target/i386/whpx/whpx-acce= l-ops.c index e8dc4b3a47..67cad86720 100644 --- a/target/i386/whpx/whpx-accel-ops.c +++ b/target/i386/whpx/whpx-accel-ops.c @@ -71,9 +71,6 @@ static void whpx_start_vcpu_thread(CPUState *cpu) cpu->cpu_index); qemu_thread_create(cpu->thread, thread_name, whpx_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); -#ifdef _WIN32 - cpu->hThread =3D qemu_thread_get_handle(cpu->thread); -#endif } =20 static void whpx_kick_vcpu_thread(CPUState *cpu) --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687450176; cv=none; d=zohomail.com; s=zohoarc; b=EncMf9ufYmNVZXEsmoN3R6Of2Zc6Oon3+iY/QXhNbS1ou/SVRA9e37++CGbPOh77bjdb4qicbpraMiMVJr1wDunZ0j/pY08Y0iHG8HKcRwxfpCNjWvnZn/DSSAPU6V/DMiwkF2+4n7W9xKRgLtimXtFmSPJLZ7dJNu9SQPKJBFg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687450176; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KWWds0uHrElgc22pSSxJ50tOp/lAV9kSI84s7Y2g/GM=; b=ghztn1KUOCGS1HOiXS4y7PBwUo7nymOMzlBMdsoZcRxKbApyKVg4AmdlIDsDf4RRU1lcYfFicbJKn3V9hlOC2xBvjFArVHZRZkUmDqFDy9d5Q7yjQ9IJSW3EUZnAUyffB/c4ogcouomiX5xc9iYUS4O86gHeIWbVwDsD5dUh30E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1687450176684675.6094543880716; Thu, 22 Jun 2023 09:09:36 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.553740.864501 (Exim 4.92) (envelope-from ) id 1qCMrx-0002rB-14; Thu, 22 Jun 2023 16:09:13 +0000 Received: by outflank-mailman (output) from mailman id 553740.864501; Thu, 22 Jun 2023 16:09:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qCMrw-0002r4-Tk; Thu, 22 Jun 2023 16:09:12 +0000 Received: by outflank-mailman (input) for mailman id 553740; Thu, 22 Jun 2023 16:09:12 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qCMrw-0001Yq-KL for xen-devel@lists.xenproject.org; Thu, 22 Jun 2023 16:09:12 +0000 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [2a00:1450:4864:20::32a]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 1fb5d7eb-1117-11ee-8611-37d641c3527e; Thu, 22 Jun 2023 18:09:11 +0200 (CEST) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3fa71db41b6so9551795e9.1 for ; Thu, 22 Jun 2023 09:09:11 -0700 (PDT) Received: from localhost.localdomain (230.red-88-28-3.dynamicip.rima-tde.net. [88.28.3.230]) by smtp.gmail.com with ESMTPSA id n6-20020a05600c294600b003f7e4639aabsm19231418wmd.10.2023.06.22.09.09.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Jun 2023 09:09:10 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1fb5d7eb-1117-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687450150; x=1690042150; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KWWds0uHrElgc22pSSxJ50tOp/lAV9kSI84s7Y2g/GM=; b=EbM780AWzavorYGjwE/j3EeJGIDw52NMRbKdS1s1/gZWniGA7sDBRZVP2QyfRqO47I 7X7B7xFYS297uGD3scmvxOmMiYP9OTll3eGFYcIQd4FpE0WW7V3oKBilIjfQT/k+/GPn V5BiCj2bgxxHGiIPvjbPJuQdy4VGi6sUnUZ8JyXtmAJEU6CrcXGXcSuxoa+cZFjfMKPW ZWhlpEG7XgwDT27Y537Y1ehWshHrG0ia2ToE68LsnrY1dFG/RpCqknDRqgAY2g/hC1Kd jf7UQOxMVQuZzQgTtEe05+aD9m+AbSf0u4R9D8Us4q4EE6ZIvJq/tj+t/EKcZaxvsqzH qQfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687450150; x=1690042150; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KWWds0uHrElgc22pSSxJ50tOp/lAV9kSI84s7Y2g/GM=; b=eMPNnfVaa4IGtZ985Sayzdo8hXR0fbgfu00mlIf26yqT+Tre6hDjhx//nSYfM4cPwd IS6v/NnIUkicuQujmYM3qg8012p27O5Umm/j953tfS3EVKxXhhX5S2JabwEyMw+WboNB +Ac4TdafIqmTsKe4qZUWPD1SoKjdpchqbwlGJiySa+VHTdkmjj+3n2Ib1REqL+L9DT8+ bLrv6Hc8BWCyWFoTKrlYWXnw1pn+pbUuiIaiN4w2gB8TPigSUqzvse0i2Eccbqu9s40P 1uaSu530UNrwZTd1ojZcVM1G/9idgjeldNSdf8LNXu1kzPC51Gk4/8KX8/B6hUlFujah KrEg== X-Gm-Message-State: AC+VfDwprUWPgSm+sMjoy0Ub8W1fddfWnAOssIVwx3hIzvGr0Ww0zye1 N24xMp8zTAy4RV68eArBDTe3bg== X-Google-Smtp-Source: ACHHUZ51xfqu7ycVqyxzIHVhQQRD4BRESLxxv3gkwPL1UAb0nB49UkufaCFZkef5SDfT9giEDTGvXg== X-Received: by 2002:a1c:6a0e:0:b0:3fa:78d1:572 with SMTP id f14-20020a1c6a0e000000b003fa78d10572mr642130wmc.0.1687450150672; Thu, 22 Jun 2023 09:09:10 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Reinoud Zandijk , qemu-arm@nongnu.org, kvm@vger.kernel.org, Marcel Apfelbaum , Stefano Stabellini , Anthony Perard , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Roman Bolshakov , Paolo Bonzini , Paul Durrant , Sunil Muthuswamy , Alexander Graf , Richard Henderson , xen-devel@lists.xenproject.org, Eduardo Habkost , Cameron Esfahani Subject: [PATCH v2 04/16] accel: Fix a leak on Windows HAX Date: Thu, 22 Jun 2023 18:08:11 +0200 Message-Id: <20230622160823.71851-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230622160823.71851-1-philmd@linaro.org> References: <20230622160823.71851-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687450177236100001 hThread is only used on the error path in hax_kick_vcpu_thread(). Fixes: b0cb0a66d6 ("Plumb the HAXM-based hardware acceleration support") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/hax/hax-all.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index 3e5992a63b..a2321a1eff 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -205,6 +205,9 @@ int hax_vcpu_destroy(CPUState *cpu) */ hax_close_fd(vcpu->fd); hax_global.vm->vcpus[vcpu->vcpu_id] =3D NULL; +#ifdef _WIN32 + CloseHandle(cpu->hThread); +#endif g_free(vcpu); return 0; } --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687450190; cv=none; d=zohomail.com; s=zohoarc; b=X+IjHoYd7OsOsCQVVbUmXG1K/8/45TPZ6t5kTgIQCF8WHCihAgZtd7r0wNaP8+Svj5z3NuUxBffljvz4ECJy6jNZxWq0bu0yS8RfQUgvGNTsr+npmDe82XMnmK1n51s5lLDsvX5/GuCTipcr8DdD6dPNHHJCs1CKrSjfREm5DDI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687450190; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IGm3E04zIWsYk05zgucyUicl5+3W8OYlCuN37xDTmqU=; b=mfKMYqOdV9miiqPjLvUdvQE8kfxm3VVkKghZvXOobyqpHBmEKfTAmBWtgjG3r+mD42uhQXOlEGiGRk78puKf/fZh4YlL6uC69P5ZrpXo3h08ndFtMOqewGFcAJa3a/TRUECSHf1ZROFI3zayNZ8fbQbLv+oZN0IIExL8fGBUVPU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1687450190649145.44882448439319; Thu, 22 Jun 2023 09:09:50 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.553743.864511 (Exim 4.92) (envelope-from ) id 1qCMs7-0003Kp-BL; Thu, 22 Jun 2023 16:09:23 +0000 Received: by outflank-mailman (output) from mailman id 553743.864511; Thu, 22 Jun 2023 16:09:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qCMs7-0003KZ-5u; Thu, 22 Jun 2023 16:09:23 +0000 Received: by outflank-mailman (input) for mailman id 553743; Thu, 22 Jun 2023 16:09:21 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qCMs5-0001Gi-NO for xen-devel@lists.xenproject.org; Thu, 22 Jun 2023 16:09:21 +0000 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [2a00:1450:4864:20::332]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 25b93591-1117-11ee-b237-6b7b168915f2; Thu, 22 Jun 2023 18:09:21 +0200 (CEST) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3f900cd3f96so63531215e9.2 for ; Thu, 22 Jun 2023 09:09:21 -0700 (PDT) Received: from localhost.localdomain (230.red-88-28-3.dynamicip.rima-tde.net. [88.28.3.230]) by smtp.gmail.com with ESMTPSA id x16-20020a05600c21d000b003f90b58df65sm13346472wmj.29.2023.06.22.09.09.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Jun 2023 09:09:20 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 25b93591-1117-11ee-b237-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687450160; x=1690042160; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IGm3E04zIWsYk05zgucyUicl5+3W8OYlCuN37xDTmqU=; b=oSZmsX3T/bloo+326SGPd5ZsHm46v9IjsSm+mX6+GHNqWc46SWntkTlBPS90redCNR ZUMjqxtJd3cZHvi9zSxHB4xdh1n7b8jsItx4rFl+mHiH+OgAFoaK+J/yb1D8i8vh1g6X Wh9p6+BtcM6BS/8tmV15GdIAi11Ly82V4oPU2YaNVUAxQtA0pzh18AGcDLF12Jbmstq5 FC0EyBMowodStWUPlID3y0Fm2oMAF3cehAD/OcX6fjRY42O0eaZ1AhKvLl08mXhP6Qb/ KU5JoMrq5Jkcz4ttchABNISgzL5QJIvTO362BtWKxVuE531Y/t0qEaegExQ9L9kbFuzp Gf2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687450160; x=1690042160; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IGm3E04zIWsYk05zgucyUicl5+3W8OYlCuN37xDTmqU=; b=brmd/uTKyyNOxq8aIdLP2zTo81L/+ZYQoildiSyworXch68/6Jz/GlY6DzrfBrgEby L3eAFvOs4wCyKMhyMA5eoOXGSvK8e67UykSC0I8up91PoL1JRH/+QIRAfWx7fna2TBFj vqrnBbTukfGW9RmpTRW0j6ipwKF49sov88JPl1dSsU0gZnY39l3yjbSxUXtCbu9suFct MMFmaEboSm8XuEEjes9Q5P1jdWGAHr7SrW+p79Qm/eCJSz6kqwcDaDdE+uAA9hxr3lLg PtCB3AG+DJl46dDQpvPkYnEN/VWjDk01g7in6/Di5hW51Yro2s9Uxkaube/wHx9qpyV/ pOvw== X-Gm-Message-State: AC+VfDyE7C8tGyilIMtWSFijdSK353jd7YtM9tGP5NFh11M29DCtPJy1 1o0b/dIIJ6JyK+zFwWkk/vZs7Q== X-Google-Smtp-Source: ACHHUZ74qZrgBDYUQFFsXIVlBQ+o5CwN3jxcBXCwUZJbgQTonuPJrTO0oSESuEoeaErY25ll4f9Zaw== X-Received: by 2002:a05:600c:2650:b0:3f8:1f52:f3a9 with SMTP id 16-20020a05600c265000b003f81f52f3a9mr13773747wmy.23.1687450160763; Thu, 22 Jun 2023 09:09:20 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Reinoud Zandijk , qemu-arm@nongnu.org, kvm@vger.kernel.org, Marcel Apfelbaum , Stefano Stabellini , Anthony Perard , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Roman Bolshakov , Paolo Bonzini , Paul Durrant , Sunil Muthuswamy , Alexander Graf , Richard Henderson , xen-devel@lists.xenproject.org, Eduardo Habkost , Cameron Esfahani Subject: [PATCH v2 05/16] accel: Destroy HAX vCPU threads once done Date: Thu, 22 Jun 2023 18:08:12 +0200 Message-Id: <20230622160823.71851-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230622160823.71851-1-philmd@linaro.org> References: <20230622160823.71851-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687450193527100005 When the vCPU thread finished its processing, destroy it and signal its destruction to generic vCPU management layer. Add a sanity check for the vCPU accelerator context. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/hax/hax-accel-ops.c | 3 +++ target/i386/hax/hax-all.c | 1 + 2 files changed, 4 insertions(+) diff --git a/target/i386/hax/hax-accel-ops.c b/target/i386/hax/hax-accel-op= s.c index 18114fe34d..0157a628a3 100644 --- a/target/i386/hax/hax-accel-ops.c +++ b/target/i386/hax/hax-accel-ops.c @@ -53,6 +53,8 @@ static void *hax_cpu_thread_fn(void *arg) =20 qemu_wait_io_event(cpu); } while (!cpu->unplug || cpu_can_run(cpu)); + hax_vcpu_destroy(cpu); + cpu_thread_signal_destroyed(cpu); rcu_unregister_thread(); return NULL; } @@ -69,6 +71,7 @@ static void hax_start_vcpu_thread(CPUState *cpu) cpu->cpu_index); qemu_thread_create(cpu->thread, thread_name, hax_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); + assert(cpu->hax_vcpu); #ifdef _WIN32 cpu->hThread =3D qemu_thread_get_handle(cpu->thread); #endif diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index a2321a1eff..38a4323a3c 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -209,6 +209,7 @@ int hax_vcpu_destroy(CPUState *cpu) CloseHandle(cpu->hThread); #endif g_free(vcpu); + cpu->hax_vcpu =3D NULL; return 0; } =20 --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687450192; cv=none; d=zohomail.com; s=zohoarc; b=OIVsIH24lX0IkSo7lcVH5Rx4dp1nVPkDRVdlkkap6A5fXpBRjrjQNB36gJM84Gqs27CN6Cmr1g5pvbIScV5hyO+Ff1Kdjo/uM5TRkrBRkPmaaWRD6LgW9w3CpL8u6H52xe0sTh9B/nFNUIWjfj/hDgLVZ5N7+xs2lX26ePHwtZc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687450192; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UX7A/4NpufAJKKWp2HGkO2gs63RM9WYyIFTo3iDzXaM=; b=LK81yjvjGfPh6VxqcFP9oGNfZpPIsSdf4YQWjHH449yq49VxPzh7fKbOPEJ6i9eMkxA7zMblchcY5OlOEHxq08hzR6oyLgUGt0jdBaCgbDLNSwAoZ+N/osUdU7Kw1eWWEtZTcdaWo+ZlzF+4gfXGjN9Qlp91m0PEZnYjV2wRcXI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687450192616748.7058095839441; Thu, 22 Jun 2023 09:09:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qCMsO-0003mA-0O; Thu, 22 Jun 2023 12:09:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qCMsJ-0003WT-J6 for qemu-devel@nongnu.org; Thu, 22 Jun 2023 12:09:37 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qCMsG-0008Pd-JD for qemu-devel@nongnu.org; Thu, 22 Jun 2023 12:09:34 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-311394406d0so4930690f8f.2 for ; Thu, 22 Jun 2023 09:09:32 -0700 (PDT) Received: from localhost.localdomain (230.red-88-28-3.dynamicip.rima-tde.net. [88.28.3.230]) by smtp.gmail.com with ESMTPSA id w8-20020adfcd08000000b00301a351a8d6sm7484316wrm.84.2023.06.22.09.09.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Jun 2023 09:09:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687450171; x=1690042171; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UX7A/4NpufAJKKWp2HGkO2gs63RM9WYyIFTo3iDzXaM=; b=BtXJKw4brEfZSHejbSp6MCWcQaSz63rU4LVBfRIO2bHD/tGvSckWZTvSLt1jKnsetZ s5eIQiUPBsO64ACxt/KHDmSKmcyN8gtt3DaYZRKyws8Jj6qV642nkeMhbsGDaUoK1zmD hLXWTP2NqMPlhQUEYgrOAatE5ZiiQwRIiHXvqkbIu8aH7U/SmOsg1bjOhdCAQzNqbKUf vtf7eNEDPBDUwpJdu6B6tlO/1xhYYNGvdTt70HCROKSl/+8qSq2Tna2iE8Wg4jxwaerU 496hkQ+qdoLSntgO9lGPsxtxABAvH5SGdC0jrrPiT1JTBW2vBvin2awtuIaxS8CDZWL9 qo3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687450171; x=1690042171; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UX7A/4NpufAJKKWp2HGkO2gs63RM9WYyIFTo3iDzXaM=; b=Mpe55H6eiuF22tG+bK9K0g//FYCt2foX27FAQBHefSoa64e+7X+4JjL5LXQHzcx0d/ qAW1D8crAd67idAuEu5JRQre42WTP7JRNwqGqdq8NQPV2+LfDal0TildhqxPmJsYu4fn IHQ8+gJ7zMJZ8TSyTSeLBh2dvrXWGxOhPwrAowSYdWZuCV5KM5l/FYQ4guJXLHRgH5ru 3DJ4lOgIwJsFUm7oClYonFfQ6cPZ6jmpvf5JIlykHS+MPmPjSD3Hh/hvVgKZNRJ2cCIY 1ahxy8IJHJT+LJboneHGz7sSQZVSzKQ4V3NckjIslKZSJnYvvSaxmtFJEIuUL3tdQb8t 6Dsg== X-Gm-Message-State: AC+VfDwL2F9I2o1Z7hIKPkKp0RugIeLSnbzvIFhkFHbslSTlYcyH6K2q 37pR3KVWhnwKi2zINYqYntRLYIRK6mU7MFTc6RUSoQ== X-Google-Smtp-Source: ACHHUZ6397oLn+9xHpt22BhUSP9QEJUubmRRJRV5VKiXD/mQbPJbeDrcgDPjDy71BF2ku+M1ZHsSsw== X-Received: by 2002:adf:f78a:0:b0:311:1cbd:800a with SMTP id q10-20020adff78a000000b003111cbd800amr13110914wrp.12.1687450170751; Thu, 22 Jun 2023 09:09:30 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Reinoud Zandijk , qemu-arm@nongnu.org, kvm@vger.kernel.org, Marcel Apfelbaum , Stefano Stabellini , Anthony Perard , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Roman Bolshakov , Paolo Bonzini , Paul Durrant , Sunil Muthuswamy , Alexander Graf , Richard Henderson , xen-devel@lists.xenproject.org, Eduardo Habkost , Cameron Esfahani Subject: [PATCH v2 06/16] accel: Rename 'hax_vcpu' as 'accel' in CPUState Date: Thu, 22 Jun 2023 18:08:13 +0200 Message-Id: <20230622160823.71851-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230622160823.71851-1-philmd@linaro.org> References: <20230622160823.71851-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687450193310100003 All accelerators will share a single opaque context in CPUState. Start by renaming 'hax_vcpu' as 'accel'. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 2 +- target/i386/hax/hax-accel-ops.c | 2 +- target/i386/hax/hax-all.c | 18 +++++++++--------- target/i386/nvmm/nvmm-all.c | 6 +++--- target/i386/whpx/whpx-all.c | 6 +++--- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 4871ad85f0..84b5a866e7 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -441,7 +441,7 @@ struct CPUState { /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ bool prctl_unalign_sigbus; =20 - struct hax_vcpu_state *hax_vcpu; + struct hax_vcpu_state *accel; =20 struct hvf_vcpu_state *hvf; =20 diff --git a/target/i386/hax/hax-accel-ops.c b/target/i386/hax/hax-accel-op= s.c index 0157a628a3..a8512efcd5 100644 --- a/target/i386/hax/hax-accel-ops.c +++ b/target/i386/hax/hax-accel-ops.c @@ -71,7 +71,7 @@ static void hax_start_vcpu_thread(CPUState *cpu) cpu->cpu_index); qemu_thread_create(cpu->thread, thread_name, hax_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); - assert(cpu->hax_vcpu); + assert(cpu->accel); #ifdef _WIN32 cpu->hThread =3D qemu_thread_get_handle(cpu->thread); #endif diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index 38a4323a3c..3865ff9419 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -62,7 +62,7 @@ int valid_hax_tunnel_size(uint16_t size) =20 hax_fd hax_vcpu_get_fd(CPUArchState *env) { - struct hax_vcpu_state *vcpu =3D env_cpu(env)->hax_vcpu; + struct hax_vcpu_state *vcpu =3D env_cpu(env)->accel; if (!vcpu) { return HAX_INVALID_FD; } @@ -188,7 +188,7 @@ int hax_vcpu_create(int id) =20 int hax_vcpu_destroy(CPUState *cpu) { - struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; + struct hax_vcpu_state *vcpu =3D cpu->accel; =20 if (!hax_global.vm) { fprintf(stderr, "vcpu %x destroy failed, vm is null\n", vcpu->vcpu= _id); @@ -209,7 +209,7 @@ int hax_vcpu_destroy(CPUState *cpu) CloseHandle(cpu->hThread); #endif g_free(vcpu); - cpu->hax_vcpu =3D NULL; + cpu->accel =3D NULL; return 0; } =20 @@ -223,7 +223,7 @@ int hax_init_vcpu(CPUState *cpu) exit(-1); } =20 - cpu->hax_vcpu =3D hax_global.vm->vcpus[cpu->cpu_index]; + cpu->accel =3D hax_global.vm->vcpus[cpu->cpu_index]; cpu->vcpu_dirty =3D true; qemu_register_reset(hax_reset_vcpu_state, cpu->env_ptr); =20 @@ -415,7 +415,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df= , uint16_t port, static int hax_vcpu_interrupt(CPUArchState *env) { CPUState *cpu =3D env_cpu(env); - struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; + struct hax_vcpu_state *vcpu =3D cpu->accel; struct hax_tunnel *ht =3D vcpu->tunnel; =20 /* @@ -447,7 +447,7 @@ static int hax_vcpu_interrupt(CPUArchState *env) =20 void hax_raise_event(CPUState *cpu) { - struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; + struct hax_vcpu_state *vcpu =3D cpu->accel; =20 if (!vcpu) { return; @@ -468,7 +468,7 @@ static int hax_vcpu_hax_exec(CPUArchState *env) int ret =3D 0; CPUState *cpu =3D env_cpu(env); X86CPU *x86_cpu =3D X86_CPU(cpu); - struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; + struct hax_vcpu_state *vcpu =3D cpu->accel; struct hax_tunnel *ht =3D vcpu->tunnel; =20 if (!hax_enabled()) { @@ -1114,8 +1114,8 @@ void hax_reset_vcpu_state(void *opaque) { CPUState *cpu; for (cpu =3D first_cpu; cpu !=3D NULL; cpu =3D CPU_NEXT(cpu)) { - cpu->hax_vcpu->tunnel->user_event_pending =3D 0; - cpu->hax_vcpu->tunnel->ready_for_interrupt_injection =3D 0; + cpu->accel->tunnel->user_event_pending =3D 0; + cpu->accel->tunnel->ready_for_interrupt_injection =3D 0; } } =20 diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index b75738ee9c..cf4f0af24b 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -52,7 +52,7 @@ static struct qemu_machine qemu_mach; static struct qemu_vcpu * get_qemu_vcpu(CPUState *cpu) { - return (struct qemu_vcpu *)cpu->hax_vcpu; + return (struct qemu_vcpu *)cpu->accel; } =20 static struct nvmm_machine * @@ -995,7 +995,7 @@ nvmm_init_vcpu(CPUState *cpu) } =20 cpu->vcpu_dirty =3D true; - cpu->hax_vcpu =3D (struct hax_vcpu_state *)qcpu; + cpu->accel =3D (struct hax_vcpu_state *)qcpu; =20 return 0; } @@ -1030,7 +1030,7 @@ nvmm_destroy_vcpu(CPUState *cpu) struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); =20 nvmm_vcpu_destroy(mach, &qcpu->vcpu); - g_free(cpu->hax_vcpu); + g_free(cpu->accel); } =20 /* -----------------------------------------------------------------------= --- */ diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 52af81683c..d1ad6f156a 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -262,7 +262,7 @@ static bool whpx_has_xsave(void) =20 static struct whpx_vcpu *get_whpx_vcpu(CPUState *cpu) { - return (struct whpx_vcpu *)cpu->hax_vcpu; + return (struct whpx_vcpu *)cpu->accel; } =20 static WHV_X64_SEGMENT_REGISTER whpx_seg_q2h(const SegmentCache *qs, int v= 86, @@ -2258,7 +2258,7 @@ int whpx_init_vcpu(CPUState *cpu) =20 vcpu->interruptable =3D true; cpu->vcpu_dirty =3D true; - cpu->hax_vcpu =3D (struct hax_vcpu_state *)vcpu; + cpu->accel =3D (struct hax_vcpu_state *)vcpu; max_vcpu_index =3D max(max_vcpu_index, cpu->cpu_index); qemu_add_vm_change_state_handler(whpx_cpu_update_state, cpu->env_ptr); =20 @@ -2300,7 +2300,7 @@ void whpx_destroy_vcpu(CPUState *cpu) =20 whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); - g_free(cpu->hax_vcpu); + g_free(cpu->accel); return; } =20 --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687450212; cv=none; d=zohomail.com; s=zohoarc; b=jfX4rDViYAd/560tiCl74cBZk7OFyiu604GHZ+tP0lpRWWHjnubl/bsrv2fxvJyUGSX9D1VI2dAa1e+Si0ZqYzxa3qTY4tT/fdjC8FLsGxs5htORHQz6VQevRs9TBujwai3rsZYKvwv2zff8DMAkgJw5f7n3RLbhfL0TO5rrkKY= ARC-Message-Signature: i=1; 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[88.28.3.230]) by smtp.gmail.com with ESMTPSA id q6-20020adff506000000b00307c8d6b4a0sm7365203wro.26.2023.06.22.09.09.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Jun 2023 09:09:40 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 31c2a3d8-1117-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687450181; x=1690042181; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CEVQVFEhZHNy/cnG3lPruZJhEG3g4jextiQzVLX54RM=; b=SWMbMjJlyBtm5Bcs5Hgx8xsm/R/SyPlbc+86z/Pib+CFxsxMZCIvBFiDzrAKjzAP6e 5U4spQdTKBGt4dKZJLewiirbAkuHrcXUQBf+sb8f3diBcS9vwPRS4YeFDv/GbfCuCOaj agnq4eSheHgWta4fDymCjlvdWpqGbg31kVD4c/85wg4mGAlNfKktoS6aP5iDcXxBzQ2k 8zugatryBG0h8USQ+05WldDKrbWNpvrPR0xBIawvKUMmo9OoZgGhMxauyxxVnvkftVy2 z0by5PUyeeeVG2B6codhhf2qKQL47MbeaJkQ/rTbEWGzrkZAUfxlMILC4Vo14gYZm80G uPWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687450181; x=1690042181; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CEVQVFEhZHNy/cnG3lPruZJhEG3g4jextiQzVLX54RM=; b=cX1GwLhwoF2VFTJksTC3zuVicH2lF05WQ6xPOhH39Kd8H7KvVDbuhdWB/a7s4mT2PI iZ4YkxoMJVPTsHWTLcMOcuPpKuywtRoHUPanOp4b74rsBAophPIwkiYwyVFj3LJCwZ+M JAXeCeY241Z2CuYPtmDCbj9tYeZgKhaMmQVQMLSrJXk+87n+Ndt7NT+5P/cZISC/r99u b89AP0THRCEnJO44gbaIx7p8QFhS+ZpG2EXATaU71HhF2j3AmCHGf8ZAexnaoDgycCeM 7zQP9liBD+ARu8c5tryODkGyVvSElnwjQcoWckE2r/FetC6BYFvQUfKNEnaLv8LilpT+ NUZQ== X-Gm-Message-State: AC+VfDwD1uYLWzIDfvnXK6t05JzaIGU41pDxCAYTRpiDBeUETueUL3g4 p9+kFeEG9lDFzSt4BKsb4vAytA== X-Google-Smtp-Source: ACHHUZ4nT6po+2alF3S0sJQrN6xHw6556XG/dKFnd67cfUhsDGgYRSSQBeakH0E0LLBXoBk4pMHnVg== X-Received: by 2002:a5d:414e:0:b0:30f:c6cd:e6c7 with SMTP id c14-20020a5d414e000000b0030fc6cde6c7mr12969411wrq.18.1687450180837; Thu, 22 Jun 2023 09:09:40 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Reinoud Zandijk , qemu-arm@nongnu.org, kvm@vger.kernel.org, Marcel Apfelbaum , Stefano Stabellini , Anthony Perard , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Roman Bolshakov , Paolo Bonzini , Paul Durrant , Sunil Muthuswamy , Alexander Graf , Richard Henderson , xen-devel@lists.xenproject.org, Eduardo Habkost , Cameron Esfahani Subject: [PATCH v2 07/16] accel: Rename HAX 'struct hax_vcpu_state' -> AccelCPUState Date: Thu, 22 Jun 2023 18:08:14 +0200 Message-Id: <20230622160823.71851-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230622160823.71851-1-philmd@linaro.org> References: <20230622160823.71851-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687450217270100001 We want all accelerators to share the same opaque pointer in CPUState. Start with the HAX context, renaming its forward declarated structure 'hax_vcpu_state' as 'AccelCPUState'. Directly use the typedef. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 5 ++--- target/i386/hax/hax-i386.h | 11 ++++++----- target/i386/hax/hax-all.c | 16 ++++++++-------- target/i386/hax/hax-posix.c | 4 ++-- target/i386/hax/hax-windows.c | 4 ++-- target/i386/nvmm/nvmm-all.c | 2 +- target/i386/whpx/whpx-all.c | 2 +- 7 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 84b5a866e7..7a0eb5ef32 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -240,7 +240,6 @@ typedef struct SavedIOTLB { struct KVMState; struct kvm_run; =20 -struct hax_vcpu_state; struct hvf_vcpu_state; =20 /* work queue */ @@ -308,6 +307,7 @@ struct qemu_work_item; * @next_cpu: Next CPU sharing TB cache. * @opaque: User data. * @mem_io_pc: Host Program Counter at which the memory was accessed. + * @accel: Pointer to accelerator specific state. * @kvm_fd: vCPU file descriptor for KVM. * @work_mutex: Lock to prevent multiple access to @work_list. * @work_list: List of pending asynchronous work. @@ -422,6 +422,7 @@ struct CPUState { uint32_t can_do_io; int32_t exception_index; =20 + struct AccelvCPUState *accel; /* shared by kvm, hax and hvf */ bool vcpu_dirty; =20 @@ -441,8 +442,6 @@ struct CPUState { /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ bool prctl_unalign_sigbus; =20 - struct hax_vcpu_state *accel; - struct hvf_vcpu_state *hvf; =20 /* track IOMMUs whose translations we've cached in the TCG TLB */ diff --git a/target/i386/hax/hax-i386.h b/target/i386/hax/hax-i386.h index 409ebdb4af..341688a254 100644 --- a/target/i386/hax/hax-i386.h +++ b/target/i386/hax/hax-i386.h @@ -25,12 +25,13 @@ typedef HANDLE hax_fd; #endif =20 extern struct hax_state hax_global; -struct hax_vcpu_state { + +typedef struct AccelCPUState { hax_fd fd; int vcpu_id; struct hax_tunnel *tunnel; unsigned char *iobuf; -}; +} hax_vcpu_state; =20 struct hax_state { hax_fd fd; /* the global hax device interface */ @@ -46,7 +47,7 @@ struct hax_vm { hax_fd fd; int id; int numvcpus; - struct hax_vcpu_state **vcpus; + hax_vcpu_state **vcpus; }; =20 /* Functions exported to host specific mode */ @@ -57,7 +58,7 @@ int valid_hax_tunnel_size(uint16_t size); int hax_mod_version(struct hax_state *hax, struct hax_module_version *vers= ion); int hax_inject_interrupt(CPUArchState *env, int vector); struct hax_vm *hax_vm_create(struct hax_state *hax, int max_cpus); -int hax_vcpu_run(struct hax_vcpu_state *vcpu); +int hax_vcpu_run(hax_vcpu_state *vcpu); int hax_vcpu_create(int id); void hax_kick_vcpu_thread(CPUState *cpu); =20 @@ -76,7 +77,7 @@ int hax_host_create_vm(struct hax_state *hax, int *vm_id); hax_fd hax_host_open_vm(struct hax_state *hax, int vm_id); int hax_host_create_vcpu(hax_fd vm_fd, int vcpuid); hax_fd hax_host_open_vcpu(int vmid, int vcpuid); -int hax_host_setup_vcpu_channel(struct hax_vcpu_state *vcpu); +int hax_host_setup_vcpu_channel(hax_vcpu_state *vcpu); hax_fd hax_mod_open(void); void hax_memory_init(void); =20 diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index 3865ff9419..a55b18f353 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -62,7 +62,7 @@ int valid_hax_tunnel_size(uint16_t size) =20 hax_fd hax_vcpu_get_fd(CPUArchState *env) { - struct hax_vcpu_state *vcpu =3D env_cpu(env)->accel; + hax_vcpu_state *vcpu =3D env_cpu(env)->accel; if (!vcpu) { return HAX_INVALID_FD; } @@ -136,7 +136,7 @@ static int hax_version_support(struct hax_state *hax) =20 int hax_vcpu_create(int id) { - struct hax_vcpu_state *vcpu =3D NULL; + hax_vcpu_state *vcpu =3D NULL; int ret; =20 if (!hax_global.vm) { @@ -149,7 +149,7 @@ int hax_vcpu_create(int id) return 0; } =20 - vcpu =3D g_new0(struct hax_vcpu_state, 1); + vcpu =3D g_new0(hax_vcpu_state, 1); =20 ret =3D hax_host_create_vcpu(hax_global.vm->fd, id); if (ret) { @@ -188,7 +188,7 @@ int hax_vcpu_create(int id) =20 int hax_vcpu_destroy(CPUState *cpu) { - struct hax_vcpu_state *vcpu =3D cpu->accel; + hax_vcpu_state *vcpu =3D cpu->accel; =20 if (!hax_global.vm) { fprintf(stderr, "vcpu %x destroy failed, vm is null\n", vcpu->vcpu= _id); @@ -263,7 +263,7 @@ struct hax_vm *hax_vm_create(struct hax_state *hax, int= max_cpus) } =20 vm->numvcpus =3D max_cpus; - vm->vcpus =3D g_new0(struct hax_vcpu_state *, vm->numvcpus); + vm->vcpus =3D g_new0(hax_vcpu_state *, vm->numvcpus); for (i =3D 0; i < vm->numvcpus; i++) { vm->vcpus[i] =3D NULL; } @@ -415,7 +415,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df= , uint16_t port, static int hax_vcpu_interrupt(CPUArchState *env) { CPUState *cpu =3D env_cpu(env); - struct hax_vcpu_state *vcpu =3D cpu->accel; + hax_vcpu_state *vcpu =3D cpu->accel; struct hax_tunnel *ht =3D vcpu->tunnel; =20 /* @@ -447,7 +447,7 @@ static int hax_vcpu_interrupt(CPUArchState *env) =20 void hax_raise_event(CPUState *cpu) { - struct hax_vcpu_state *vcpu =3D cpu->accel; + hax_vcpu_state *vcpu =3D cpu->accel; =20 if (!vcpu) { return; @@ -468,7 +468,7 @@ static int hax_vcpu_hax_exec(CPUArchState *env) int ret =3D 0; CPUState *cpu =3D env_cpu(env); X86CPU *x86_cpu =3D X86_CPU(cpu); - struct hax_vcpu_state *vcpu =3D cpu->accel; + hax_vcpu_state *vcpu =3D cpu->accel; struct hax_tunnel *ht =3D vcpu->tunnel; =20 if (!hax_enabled()) { diff --git a/target/i386/hax/hax-posix.c b/target/i386/hax/hax-posix.c index ac1a51096e..8ee247845b 100644 --- a/target/i386/hax/hax-posix.c +++ b/target/i386/hax/hax-posix.c @@ -205,7 +205,7 @@ hax_fd hax_host_open_vcpu(int vmid, int vcpuid) return fd; } =20 -int hax_host_setup_vcpu_channel(struct hax_vcpu_state *vcpu) +int hax_host_setup_vcpu_channel(hax_vcpu_state *vcpu) { int ret; struct hax_tunnel_info info; @@ -227,7 +227,7 @@ int hax_host_setup_vcpu_channel(struct hax_vcpu_state *= vcpu) return 0; } =20 -int hax_vcpu_run(struct hax_vcpu_state *vcpu) +int hax_vcpu_run(hax_vcpu_state *vcpu) { return ioctl(vcpu->fd, HAX_VCPU_IOCTL_RUN, NULL); } diff --git a/target/i386/hax/hax-windows.c b/target/i386/hax/hax-windows.c index 59afa213a6..08ec93a256 100644 --- a/target/i386/hax/hax-windows.c +++ b/target/i386/hax/hax-windows.c @@ -301,7 +301,7 @@ hax_fd hax_host_open_vcpu(int vmid, int vcpuid) return hDeviceVCPU; } =20 -int hax_host_setup_vcpu_channel(struct hax_vcpu_state *vcpu) +int hax_host_setup_vcpu_channel(hax_vcpu_state *vcpu) { hax_fd hDeviceVCPU =3D vcpu->fd; int ret; @@ -327,7 +327,7 @@ int hax_host_setup_vcpu_channel(struct hax_vcpu_state *= vcpu) return 0; } =20 -int hax_vcpu_run(struct hax_vcpu_state *vcpu) +int hax_vcpu_run(hax_vcpu_state *vcpu) { int ret; HANDLE hDeviceVCPU =3D vcpu->fd; diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index cf4f0af24b..50b96ced45 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -995,7 +995,7 @@ nvmm_init_vcpu(CPUState *cpu) } =20 cpu->vcpu_dirty =3D true; - cpu->accel =3D (struct hax_vcpu_state *)qcpu; + cpu->accel =3D (struct AccelCPUState *)qcpu; =20 return 0; } diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index d1ad6f156a..340053e6dd 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -2258,7 +2258,7 @@ int whpx_init_vcpu(CPUState *cpu) =20 vcpu->interruptable =3D true; cpu->vcpu_dirty =3D true; - cpu->accel =3D (struct hax_vcpu_state *)vcpu; + cpu->accel =3D (struct AccelCPUState *)vcpu; max_vcpu_index =3D max(max_vcpu_index, cpu->cpu_index); qemu_add_vm_change_state_handler(whpx_cpu_update_state, cpu->env_ptr); =20 --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[88.28.3.230]) by smtp.gmail.com with ESMTPSA id 18-20020a05600c231200b003f9063fc3cbsm15728266wmo.44.2023.06.22.09.09.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Jun 2023 09:09:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687450191; x=1690042191; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JvPaiGifFa4V3EDPR8281c6klb7rmX/1fxpDcHgqe0M=; b=eMI0lYofss2LnSC9zIInA8Ipk7eMxXhs+QiJpeQw9NS9zkZEFQ1lVPz/mbrEgeEiXA Ri7nz3jKh0S6qK5bsBvFyX/ct26k8E5D8eKE417CKn6y2iGv2+rM8N9uwLCMdAKyEI7X MMdOjASfQZS5YzkHqhkSQtobW3/VLtYbGQcltoxMV3nPGbcAESIgwLdZybGqteLBVnBg a5dpQ46mz72Ed6dT4hb+hrjZXYiJyZjkSA9COUibnKtQZC0+hriXiYatbrVRlJqxvbzY lFDuP+sY/SBTHtbuawPlcyqRonlrtNxF9U2xibk40wo1M3U6dJPNYJfm0W1mWDJUNQxk k1+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687450191; x=1690042191; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JvPaiGifFa4V3EDPR8281c6klb7rmX/1fxpDcHgqe0M=; b=SwZHubb8ldcKQdPVPgQ5lYmSAwnY2EDQqRaVlzUH1xl6G4luVneM9DpPAifF6MF+5A +zZrMK3iWEmtWhBRvnq8VAU6hmyjEDapJttPnkO+GbNA58v8SYL9bi1jKvSB5k6h2M1x ENF78BTS3T79Imwcw0e003NjizcilsNMuf/FSroiPYdEVFum1x73du+W5KIjBr8OmDCU gUFJ+bW63pABj3DvxnSHH5V0L/hPhlfZZRySZoyYspeGQc0aYcGHQDUp5d/C7IUlJxk1 R56VYSFPSnse7ppl+B3KkpPPPTPVdqg46XYEYGcAfhsZAklRyhFqHdYdcpsPj4ej/6/6 AsZA== X-Gm-Message-State: AC+VfDx2XMKkteo98lSX55CA+Q6sjMGwLAMnncBfpm1PDZcqeWSQtYQE XnWinycsZzesXx4QX2Q5k/nti9l0/oi2MM0eEo/XJQ== X-Google-Smtp-Source: ACHHUZ6G9OLsvBnleSSkNlcXjvZT2geh5kw9jW1iWf49K3tUM4xM9BzXlYcfgI7DqMTT/RTvu7N/RA== X-Received: by 2002:a7b:cb05:0:b0:3f8:f015:69c9 with SMTP id u5-20020a7bcb05000000b003f8f01569c9mr12695304wmj.11.1687450190857; Thu, 22 Jun 2023 09:09:50 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Reinoud Zandijk , qemu-arm@nongnu.org, kvm@vger.kernel.org, Marcel Apfelbaum , Stefano Stabellini , Anthony Perard , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Roman Bolshakov , Paolo Bonzini , Paul Durrant , Sunil Muthuswamy , Alexander Graf , Richard Henderson , xen-devel@lists.xenproject.org, Eduardo Habkost , Cameron Esfahani Subject: [PATCH v2 08/16] accel: Move HAX hThread to accelerator context Date: Thu, 22 Jun 2023 18:08:15 +0200 Message-Id: <20230622160823.71851-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230622160823.71851-1-philmd@linaro.org> References: <20230622160823.71851-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687450225120100007 hThread variable is only used by the HAX accelerator, so move it to the accelerator specific context. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 1 - target/i386/hax/hax-i386.h | 3 +++ target/i386/hax/hax-accel-ops.c | 2 +- target/i386/hax/hax-all.c | 2 +- target/i386/hax/hax-windows.c | 2 +- 5 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 7a0eb5ef32..01388d5918 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -337,7 +337,6 @@ struct CPUState { =20 struct QemuThread *thread; #ifdef _WIN32 - HANDLE hThread; QemuSemaphore sem; #endif int thread_id; diff --git a/target/i386/hax/hax-i386.h b/target/i386/hax/hax-i386.h index 341688a254..7055f5b53e 100644 --- a/target/i386/hax/hax-i386.h +++ b/target/i386/hax/hax-i386.h @@ -27,6 +27,9 @@ typedef HANDLE hax_fd; extern struct hax_state hax_global; =20 typedef struct AccelCPUState { +#ifdef _WIN32 + HANDLE hThread; +#endif hax_fd fd; int vcpu_id; struct hax_tunnel *tunnel; diff --git a/target/i386/hax/hax-accel-ops.c b/target/i386/hax/hax-accel-op= s.c index a8512efcd5..5031096760 100644 --- a/target/i386/hax/hax-accel-ops.c +++ b/target/i386/hax/hax-accel-ops.c @@ -73,7 +73,7 @@ static void hax_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); assert(cpu->accel); #ifdef _WIN32 - cpu->hThread =3D qemu_thread_get_handle(cpu->thread); + cpu->accel->hThread =3D qemu_thread_get_handle(cpu->thread); #endif } =20 diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index a55b18f353..c9ccc411e9 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -206,7 +206,7 @@ int hax_vcpu_destroy(CPUState *cpu) hax_close_fd(vcpu->fd); hax_global.vm->vcpus[vcpu->vcpu_id] =3D NULL; #ifdef _WIN32 - CloseHandle(cpu->hThread); + CloseHandle(vcpu->hThread); #endif g_free(vcpu); cpu->accel =3D NULL; diff --git a/target/i386/hax/hax-windows.c b/target/i386/hax/hax-windows.c index 08ec93a256..b907953321 100644 --- a/target/i386/hax/hax-windows.c +++ b/target/i386/hax/hax-windows.c @@ -476,7 +476,7 @@ void hax_kick_vcpu_thread(CPUState *cpu) */ cpu->exit_request =3D 1; if (!qemu_cpu_is_self(cpu)) { - if (!QueueUserAPC(dummy_apc_func, cpu->hThread, 0)) { + if (!QueueUserAPC(dummy_apc_func, cpu->accel->hThread, 0)) { fprintf(stderr, "%s: QueueUserAPC failed with error %lu\n", __func__, GetLastError()); exit(1); --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687450249; cv=none; d=zohomail.com; s=zohoarc; b=Y78dwQEfoKTJCe9rBJTACogxAONhDwRuK+ni+0PLy0oqLun9fGWtDvN+ZfRSQSRnPkXhvE1gYKAt7J5HpoC2qtQaatmvtUiasFfCTN4zazdn5e9HjZlObvNyabpqX4DrLwn8AZn+nGiLmj9ieL9T5zHRgN0k8GYxdhCSOWk9DNY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687450249; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0HtP5OMiHV1uHyCREuOsPgXLNdWuwc5y+seBeAIuir0=; b=D5lzBfm6gjY/hidd/PDSqOrP5TYjSM3J6mQ8pKE7W//FFSKsCnqrM5WihZN8Tr0JoP8WA4fksWLFwZO1n59foAlW+YaNDA2+fOdMhmm54lQsI5skFC4lD6evsZAabwwfQzzrmI4yHTPvlPJyBg+4gClhO2VBT856gv7nKYnxrcA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687450249578116.61548727866489; Thu, 22 Jun 2023 09:10:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qCMss-0006E2-4h; Thu, 22 Jun 2023 12:10:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qCMsm-00068O-M1 for qemu-devel@nongnu.org; Thu, 22 Jun 2023 12:10:04 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qCMsk-00010n-Th for qemu-devel@nongnu.org; Thu, 22 Jun 2023 12:10:04 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-3094910b150so7581997f8f.0 for ; Thu, 22 Jun 2023 09:10:02 -0700 (PDT) Received: from localhost.localdomain (230.red-88-28-3.dynamicip.rima-tde.net. [88.28.3.230]) by smtp.gmail.com with ESMTPSA id 18-20020a05600c231200b003f9063fc3cbsm15728619wmo.44.2023.06.22.09.09.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Jun 2023 09:10:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687450201; x=1690042201; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0HtP5OMiHV1uHyCREuOsPgXLNdWuwc5y+seBeAIuir0=; b=fD2yFKYVUSbELRWkgGW0danFEJd49UvIoHVUaoL+iV8IqYQvNfiml31iLxtBJeKK+2 BhYPg4qUhHRzjckRgaA9Y7ICZhNcCZMhqc202pVq8XOrpxWtk6WoH7hxA67ck5XYCSA2 a1mUXkxpR3fQsnOmFzfz0iq4qYue5q1tdAT5/kH9rAuDXlR9gqshBZLvQbP2e7xh87Rz 116ue4dKX7z8nRG43aPZMWOGjKu3Mtzz5LGCpfwr8CqoismIj/q6QyBXeNO1kiC0U6lz /+jW94I7TghlhujpjnaWLHWAqKt+jU29K9hKNOv+XTxyLGAUr4jy4FnAEonFW8sot8W/ zLTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687450201; x=1690042201; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0HtP5OMiHV1uHyCREuOsPgXLNdWuwc5y+seBeAIuir0=; b=bUD5J9/23eMSbYAqpt3133bVUQZ54f5BINQMCq0/EvFul6JhGHHaqPstxc2ujYGUPq EdRO2vsBEqa4NPOi7SgZwSExM2YGlktF0oXg3ezkoohbAO7xZ4QiPiwnBt9iWp6aQ4mT CRNKy6hD/d0kvIYa1oWlEtDYN0wwM8LACE1LXEB1XBvVl6RJ+4axlQt0fAL/9oFI06a/ uCAEjgZ2ocBJvVOvhSh8ratmzfY8Rg6FgxWyn1a4FnRqwJnECmuWGVAvq5Zvq92lVZzB W0Ijz/dGwdVDvAYn3XvQAIDScD8aNMkNGP9CEhu08EIwg4Z5Zv/jg2oqzuAf1NPhEBT9 BsXA== X-Gm-Message-State: AC+VfDxpjkDwkRAN1DZI6x8+CLkTwkvb5g+BBo0h9BcVSCSwvgTLbx5T Nwak8dllXuRRdgLK9PGJ7lKMwYXbMctcB++fYu7jrA== X-Google-Smtp-Source: ACHHUZ63Fuzhm8d41+KEQTBgPUOc0gqnijkCpCOihqOKQVjSB4IS+fg+O0ZMGvIAchJ0HLw7tqsoww== X-Received: by 2002:adf:e611:0:b0:309:fcbe:748a with SMTP id p17-20020adfe611000000b00309fcbe748amr17046247wrm.11.1687450201085; Thu, 22 Jun 2023 09:10:01 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Reinoud Zandijk , qemu-arm@nongnu.org, kvm@vger.kernel.org, Marcel Apfelbaum , Stefano Stabellini , Anthony Perard , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Roman Bolshakov , Paolo Bonzini , Paul Durrant , Sunil Muthuswamy , Alexander Graf , Richard Henderson , xen-devel@lists.xenproject.org, Eduardo Habkost , Cameron Esfahani Subject: [PATCH v2 09/16] accel: Remove NVMM unreachable error path Date: Thu, 22 Jun 2023 18:08:16 +0200 Message-Id: <20230622160823.71851-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230622160823.71851-1-philmd@linaro.org> References: <20230622160823.71851-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687450250438100001 g_malloc0() can not fail. Remove the unreachable error path. https://developer-old.gnome.org/glib/stable/glib-Memory-Allocation.html#gli= b-Memory-Allocation.description Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/nvmm/nvmm-all.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index 50b96ced45..0588a328ae 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -943,10 +943,6 @@ nvmm_init_vcpu(CPUState *cpu) } =20 qcpu =3D g_malloc0(sizeof(*qcpu)); - if (qcpu =3D=3D NULL) { - error_report("NVMM: Failed to allocate VCPU context."); - return -ENOMEM; - } =20 ret =3D nvmm_vcpu_create(mach, cpu->cpu_index, &qcpu->vcpu); if (ret =3D=3D -1) { --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687450242; cv=none; d=zohomail.com; s=zohoarc; b=bzdFUgrs95l32e6N8MENOUMJ97pj29rEasOJDDGepgxlNqgi9eDMyltGG6DrZOiwYwlV8DlRoXiri96pE4990nNbZrzxSvL0FSKsvsrPGWF/JH9rUIzOyzRj7CWfwETxm3gF+sZQHgMyS7foayBfi2NFHztwRJPQ2MeNSsGrF6I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687450242; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DKJxOwJmFtwOPAoIICT6M4A+Kzh99mIVYxe/d/9G77Y=; b=Bkl+VfsybeObUNMxk5/pRDYoTl35CQcaAzG0jFP2lSA17qy3PsKWkLCJpwSDGR6m6GQxlCrI9Y30k9wQJJw7si9mYJEIvzkd1ptJcN2ikJXUWP8LEDRZC6Tr11wtF+wKRt+dFWzy3Kn6s5doIHiJTxhrWLzkKwvzsArSjECvOKk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687450242128715.5429817991475; Thu, 22 Jun 2023 09:10:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qCMtH-0007AI-3U; Thu, 22 Jun 2023 12:10:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qCMsz-0006VU-AF for qemu-devel@nongnu.org; Thu, 22 Jun 2023 12:10:18 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qCMsu-0001T3-Pr for qemu-devel@nongnu.org; Thu, 22 Jun 2023 12:10:15 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-31121494630so8422845f8f.3 for ; Thu, 22 Jun 2023 09:10:12 -0700 (PDT) Received: from localhost.localdomain (230.red-88-28-3.dynamicip.rima-tde.net. [88.28.3.230]) by smtp.gmail.com with ESMTPSA id p1-20020adfcc81000000b0030ada01ca78sm7404978wrj.10.2023.06.22.09.10.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Jun 2023 09:10:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687450211; x=1690042211; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DKJxOwJmFtwOPAoIICT6M4A+Kzh99mIVYxe/d/9G77Y=; b=eg02hjlfgcDaH24aEbjvIFOFqry3t+y3ca6mONxnjQGWPL1Jdtwu4KdzlrO2pncUEm v2uAXFNtaqYiIggOc18WWF8JNx7doFAbVKyL4i5VvjAKuJTrn61jQREqSGuH7wbxPOHB SQl9lpmkdOY2I8TmvPTRmSHTV/xdmaBelLgPfNn9zpSA2OubeWfB677UATrlvOYIbcR5 Xd77M5NfRhzJ8nLGIWLXvPckfbvl62BDfMBhKFdJDV8OUDdGPmWJ81CYWWuuNJVbGqz8 ykGAHRraJs8kr5Nc/YT6E4MagkrdbYLZbwKyQ84h9/BoPe+M9i29JT/WKZ3nt6qAzCaS onVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687450211; x=1690042211; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DKJxOwJmFtwOPAoIICT6M4A+Kzh99mIVYxe/d/9G77Y=; b=fLuH78Lc4lQbBN8zlLUi7c8kC+2Xe31uT3fP3LytFC1vlOxDKJaDRMr9ja6JXIE7IX 6Q5dvAtSfC4Inv7dK6PJ2whFqdKrCBiXn4rL+58nxJfDzUhQbBmrx8I/Cl9I5dM6CVPM RqS+H2mmSKSezNvzDbpHoNh8rndn8doBJrj8+SnVpd5sqvf6Noi4QV7r2O2XXnwm1Gmp b0W40znF7tn5VlB2oYU6UvQv5U9sNcpKYtQr9vqqLB0mVf3BztdnuFbDkcVTTriH6zNd dVvAARdpM/puAq+Kdf4s/38EeiynuxfmHLogdFj5soE0nOvL7a1tVVrhT9vfcGinN/WH 2UsQ== X-Gm-Message-State: AC+VfDx8EmqXjWWqaBXN/N0OwRRkmb8RM4g2lbFpkXnDSG7BaMSDCm6G zc8xxHbiFqrxSHpUBzmLIf900HYrJFgUi2hcvRYj/Q== X-Google-Smtp-Source: ACHHUZ4UJwkfw8UWBY57D2hqCgPl1JN/hvtysVX8WTPHmCC0zEYaJGE4bKrnhQf98VbpMbWrM/7XNw== X-Received: by 2002:a5d:5751:0:b0:30f:c943:f925 with SMTP id q17-20020a5d5751000000b0030fc943f925mr15315373wrw.49.1687450210926; Thu, 22 Jun 2023 09:10:10 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Reinoud Zandijk , qemu-arm@nongnu.org, kvm@vger.kernel.org, Marcel Apfelbaum , Stefano Stabellini , Anthony Perard , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Roman Bolshakov , Paolo Bonzini , Paul Durrant , Sunil Muthuswamy , Alexander Graf , Richard Henderson , xen-devel@lists.xenproject.org, Eduardo Habkost , Cameron Esfahani Subject: [PATCH v2 10/16] accel: Rename NVMM 'struct qemu_vcpu' -> AccelCPUState Date: Thu, 22 Jun 2023 18:08:17 +0200 Message-Id: <20230622160823.71851-11-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230622160823.71851-1-philmd@linaro.org> References: <20230622160823.71851-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687450243369100001 We want all accelerators to share the same opaque pointer in CPUState. Rename NVMM 'qemu_vcpu' as 'AccelCPUState'; directly use the typedef, remove unnecessary casts. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/nvmm/nvmm-all.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index 0588a328ae..e5ee4af084 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -26,7 +26,7 @@ =20 #include =20 -struct qemu_vcpu { +struct AccelCPUState { struct nvmm_vcpu vcpu; uint8_t tpr; bool stop; @@ -49,10 +49,10 @@ struct qemu_machine { static bool nvmm_allowed; static struct qemu_machine qemu_mach; =20 -static struct qemu_vcpu * +static AccelCPUState * get_qemu_vcpu(CPUState *cpu) { - return (struct qemu_vcpu *)cpu->accel; + return cpu->accel; } =20 static struct nvmm_machine * @@ -86,7 +86,7 @@ nvmm_set_registers(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_x64_state *state =3D vcpu->state; uint64_t bitmap; @@ -223,7 +223,7 @@ nvmm_get_registers(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -347,7 +347,7 @@ static bool nvmm_can_take_int(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_machine *mach =3D get_nvmm_mach(); =20 @@ -372,7 +372,7 @@ nvmm_can_take_int(CPUState *cpu) static bool nvmm_can_take_nmi(CPUState *cpu) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); =20 /* * Contrary to INTs, NMIs always schedule an exit when they are @@ -395,7 +395,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -478,7 +478,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) static void nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); uint64_t tpr; @@ -565,7 +565,7 @@ static int nvmm_handle_rdmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -610,7 +610,7 @@ static int nvmm_handle_wrmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -686,7 +686,7 @@ nvmm_vcpu_loop(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_vcpu_exit *exit =3D vcpu->exit; @@ -892,7 +892,7 @@ static void nvmm_ipi_signal(int sigcpu) { if (current_cpu) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(current_cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(current_cpu); #if NVMM_USER_VERSION >=3D 2 struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; nvmm_vcpu_stop(vcpu); @@ -926,7 +926,7 @@ nvmm_init_vcpu(CPUState *cpu) struct nvmm_vcpu_conf_cpuid cpuid; struct nvmm_vcpu_conf_tpr tpr; Error *local_error =3D NULL; - struct qemu_vcpu *qcpu; + AccelCPUState *qcpu; int ret, err; =20 nvmm_init_cpu_signals(); @@ -942,7 +942,7 @@ nvmm_init_vcpu(CPUState *cpu) } } =20 - qcpu =3D g_malloc0(sizeof(*qcpu)); + qcpu =3D g_new0(AccelCPUState, 1); =20 ret =3D nvmm_vcpu_create(mach, cpu->cpu_index, &qcpu->vcpu); if (ret =3D=3D -1) { @@ -991,7 +991,7 @@ nvmm_init_vcpu(CPUState *cpu) } =20 cpu->vcpu_dirty =3D true; - cpu->accel =3D (struct AccelCPUState *)qcpu; + cpu->accel =3D qcpu; =20 return 0; } @@ -1023,7 +1023,7 @@ void nvmm_destroy_vcpu(CPUState *cpu) { struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); =20 nvmm_vcpu_destroy(mach, &qcpu->vcpu); g_free(cpu->accel); --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[88.28.3.230]) by smtp.gmail.com with ESMTPSA id b10-20020adff24a000000b0030ae901bc54sm7431007wrp.62.2023.06.22.09.10.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Jun 2023 09:10:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687450221; x=1690042221; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=op05vfUAX1M3Sv7qs3sw3v39U7zORQkGDmdogVHbS1k=; b=CKQGRKk27eSiIm5F19z7Fw+0UvB8mt1EPZLenc8tuPAa4/0aAJ+SnF0zMdupIesuyt y+b9HW/Tb6ijXTw+tcPYovJXVtzhbfNQAHL/wbbrJCOYMGhNXzWxJNKlFdQs54AipuBV 8cK3z0P30nCRdCrWawQrXVeu9fd8c1dzsrKCESqWXQWBZ2c8S9sJc1GYQT088AZSppGP tM9c3RZPpYecVoQf4egjUEs3Wad7FFK1rNqFHaM5rarNR1UBzBZNnDECVuKlhKTWdy/n Wxo/JJLqZglnWMDLVqm9qi+92fIiIS2+HMnITawdbUIJ6FNynUzzBpy7S6DlXLoEUOiv nYDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687450221; x=1690042221; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=op05vfUAX1M3Sv7qs3sw3v39U7zORQkGDmdogVHbS1k=; b=MAut3Np+6Mstmd+Rw770i5JBFs1rwOphK040sl2Hu3a1PseSaemgAZRG46+8MOSL9K 8oNcn3iVchiuPfFzK5jzerAyHb0kt7oGylWmHo9lYbKL2f5jBVRAC2NJQidyw+uRc//8 DlXLZZ4YZDNxqGlwDyizFULRJVk0fomuy4KdLaErMh9zC/pC99DJV/U/y70Teopo1dGn vO9WYtrpu1YBkBRSQJ+QRcwl8YcjLzrKEb40ahDGx+XVsggp7NuZmWC0ySsfJQnHqjdW Sf6LlptLDlayn6AHSBpa5srX3KgEIICmSlpTOqY4L7o8byaBj47zzMK10PELxWSQPsBq 6xuA== X-Gm-Message-State: AC+VfDzChCCkPXWJvBheAiBdIm4QybHvdZFK7JPbbmAuC6RVgePztPB0 Zw3nDJ0wpwLiED+6XRAaA0xphO4d5HQdqn01WS5FDg== X-Google-Smtp-Source: ACHHUZ4x7GzIKnUKtsG2jddWduLXgCTnpycV5f8sqghKDDH0II0u9Om2EL3+2MK2AM5jv0n4wk3OZg== X-Received: by 2002:a05:600c:228e:b0:3f4:2158:28a0 with SMTP id 14-20020a05600c228e00b003f4215828a0mr17454713wmf.12.1687450221295; Thu, 22 Jun 2023 09:10:21 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Reinoud Zandijk , qemu-arm@nongnu.org, kvm@vger.kernel.org, Marcel Apfelbaum , Stefano Stabellini , Anthony Perard , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Roman Bolshakov , Paolo Bonzini , Paul Durrant , Sunil Muthuswamy , Alexander Graf , Richard Henderson , xen-devel@lists.xenproject.org, Eduardo Habkost , Cameron Esfahani Subject: [PATCH v2 11/16] accel: Inline NVMM get_qemu_vcpu() Date: Thu, 22 Jun 2023 18:08:18 +0200 Message-Id: <20230622160823.71851-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230622160823.71851-1-philmd@linaro.org> References: <20230622160823.71851-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687450261977100001 No need for this helper to access the CPUState::accel field. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/nvmm/nvmm-all.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index e5ee4af084..72a3a9e3ae 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -49,12 +49,6 @@ struct qemu_machine { static bool nvmm_allowed; static struct qemu_machine qemu_mach; =20 -static AccelCPUState * -get_qemu_vcpu(CPUState *cpu) -{ - return cpu->accel; -} - static struct nvmm_machine * get_nvmm_mach(void) { @@ -86,7 +80,7 @@ nvmm_set_registers(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_x64_state *state =3D vcpu->state; uint64_t bitmap; @@ -223,7 +217,7 @@ nvmm_get_registers(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -347,7 +341,7 @@ static bool nvmm_can_take_int(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_machine *mach =3D get_nvmm_mach(); =20 @@ -372,7 +366,7 @@ nvmm_can_take_int(CPUState *cpu) static bool nvmm_can_take_nmi(CPUState *cpu) { - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; =20 /* * Contrary to INTs, NMIs always schedule an exit when they are @@ -395,7 +389,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -478,7 +472,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) static void nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit) { - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); uint64_t tpr; @@ -565,7 +559,7 @@ static int nvmm_handle_rdmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -610,7 +604,7 @@ static int nvmm_handle_wrmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -686,7 +680,7 @@ nvmm_vcpu_loop(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_vcpu_exit *exit =3D vcpu->exit; @@ -892,7 +886,7 @@ static void nvmm_ipi_signal(int sigcpu) { if (current_cpu) { - AccelCPUState *qcpu =3D get_qemu_vcpu(current_cpu); + AccelCPUState *qcpu =3D current_cpu->accel; #if NVMM_USER_VERSION >=3D 2 struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; nvmm_vcpu_stop(vcpu); @@ -1023,7 +1017,7 @@ void nvmm_destroy_vcpu(CPUState *cpu) { struct nvmm_machine *mach =3D get_nvmm_mach(); - AccelCPUState *qcpu =3D get_qemu_vcpu(cpu); + AccelCPUState *qcpu =3D cpu->accel; =20 nvmm_vcpu_destroy(mach, &qcpu->vcpu); g_free(cpu->accel); --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[88.28.3.230]) by smtp.gmail.com with ESMTPSA id 8-20020a05600c028800b003f9c8c6bf53sm3978876wmk.13.2023.06.22.09.10.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Jun 2023 09:10:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687450231; x=1690042231; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xrWBSt50GXK7KCFoWhMRFDVlBR7e4c4Lap7a/Dv/MfQ=; b=uh16dyOE/YngV+vlrCn9FF7LTn5kqMPDeNAZPJp/OXd6o48t2oNQK6+xyZgF0O/Rwg eOGnESuioKTn+49rZFTitvpZbXcCCA2lKI3uKKPWDO6qAJwPVxKRyFjY6tswlOnD5ggQ uglMk0I6MEVmcZiNo50/xLJc3XKZtwUiYzcshho3Z8PHZ77Ff5SeMMqNEPPm+6yamswW 43xD7f+l3wuUlEu0Jk5k14uNzXBhG+/BP5Z2LtMbnA+vN2SOlxaHgl9cD7Y/VNZS7ggW sXiU9m8gF/k7MyaKQbMxBUzf2iKP0B73BEmBKpJN7i3GqROl8rychDyAYceCJlDAbGA3 M6Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687450231; x=1690042231; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xrWBSt50GXK7KCFoWhMRFDVlBR7e4c4Lap7a/Dv/MfQ=; b=OxvnBVIi8WaMI959h6NwzG1h/AGg5FMsc5GnWMTrpoRWI9dAqrwIZCIkrHxA6WDybB 2iwxChyuyZkqGOsIU1lQbwwcU3PUYE6N2rr78v5WJTdPE1/BoW0gd801ptqeD3gq9Yj+ aJ0VwDfpE8W6rSb1RTv2c/31cF/YxOWWAbNnoyPc9DSOWLDMyrBlo4Isacj3ceCdzEwB 7ZqQzi95xFGIMhyobJp7xOHfc6wYddIbOrqxuHZGHyzlOrxJQQwVJWVeqv6RLt8hjEqq JxEjBwSV8TPqR6jFn9La8ka7VU0yvnVPeZ2AxnaKWfB8/q9WymIJiPFSAbHb6+XyLtxi Bb3Q== X-Gm-Message-State: AC+VfDyYbWgb8KuPHx0wohQJN9Dk/Z8VX1SP6kqtJppMlbcDqrwKkHxO U0yu3pwmr3viBJYnHM8zBHxCfS7GRvi3AzW5z9ROJw== X-Google-Smtp-Source: ACHHUZ5cB8aDLTQ/tjJec4fXZP1xWmF+PhC752VaaNKObmwfmqLXBqw27M1/B1ILuvDg4fp61kaDNA== X-Received: by 2002:a1c:7911:0:b0:3f9:b2a9:c546 with SMTP id l17-20020a1c7911000000b003f9b2a9c546mr9068827wme.28.1687450231205; Thu, 22 Jun 2023 09:10:31 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Reinoud Zandijk , qemu-arm@nongnu.org, kvm@vger.kernel.org, Marcel Apfelbaum , Stefano Stabellini , Anthony Perard , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Roman Bolshakov , Paolo Bonzini , Paul Durrant , Sunil Muthuswamy , Alexander Graf , Richard Henderson , xen-devel@lists.xenproject.org, Eduardo Habkost , Cameron Esfahani Subject: [PATCH v2 12/16] accel: Remove WHPX unreachable error path Date: Thu, 22 Jun 2023 18:08:19 +0200 Message-Id: <20230622160823.71851-13-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230622160823.71851-1-philmd@linaro.org> References: <20230622160823.71851-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687450267825100002 g_new0() can not fail. Remove the unreachable error path. https://developer-old.gnome.org/glib/stable/glib-Memory-Allocation.html#gli= b-Memory-Allocation.description Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/whpx/whpx-all.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 340053e6dd..012ba696a9 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -2179,12 +2179,6 @@ int whpx_init_vcpu(CPUState *cpu) =20 vcpu =3D g_new0(struct whpx_vcpu, 1); =20 - if (!vcpu) { - error_report("WHPX: Failed to allocte VCPU context."); - ret =3D -ENOMEM; - goto error; - } - hr =3D whp_dispatch.WHvEmulatorCreateEmulator( &whpx_emu_callbacks, &vcpu->emulator); --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687450269; cv=none; d=zohomail.com; s=zohoarc; b=ND0xGN3QjbxOC5RcQULYwqFhF/dKf3UGTAtMcbKpCYzr7TTnn1qUZw7kRReqGAQK8KzFuiQN3SAYhwsTeTXQl36t2eUsY+nWiqEPdb9oOotwkqURClPjt4/KFVtWHHcBoED6peuSxPTLp5WAAL9GQfUCP872yXL6KKsF1TsTXoE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687450269; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qiGDoiG1y93PPW7mQ2SAaPUCrdr0EnIkEF2xjLc8x+o=; b=ms6t1KlmXTYlah5BL8APQtrspQKjxAUmboMi9+9nAOcBbmyStz4hm91ECOJ1BsVJ7IwgwMiMWKO250B2N4lRf0C3zlkm11GGWhTn+oVE55c47p8e21Z+S3sx5mbDxq2zWmNStEUPgrbMOgfAR6NJyfKwPib/g9aWUxZuuO9oe78= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687450269047579.958737122103; Thu, 22 Jun 2023 09:11:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qCMtj-0008DJ-Ve; Thu, 22 Jun 2023 12:11:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qCMtS-0007w2-Os for qemu-devel@nongnu.org; Thu, 22 Jun 2023 12:10:50 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qCMtO-0002L5-Ua for qemu-devel@nongnu.org; Thu, 22 Jun 2023 12:10:45 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3f9189228bcso48682395e9.3 for ; Thu, 22 Jun 2023 09:10:42 -0700 (PDT) Received: from localhost.localdomain (230.red-88-28-3.dynamicip.rima-tde.net. [88.28.3.230]) by smtp.gmail.com with ESMTPSA id t20-20020a1c7714000000b003f900678815sm8037671wmi.39.2023.06.22.09.10.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Jun 2023 09:10:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687450241; x=1690042241; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qiGDoiG1y93PPW7mQ2SAaPUCrdr0EnIkEF2xjLc8x+o=; b=afjs6vIbGP/1PJJGvwXCmtbKZCbNgsjyiMItVow4+iOx2GIUdmWc+dyuANhlyir8kF 2aYlXh5DgFmociidTOF1UsWRAtyrmcgnlXWGI09EUFdjHUk9Cp5Np1TrftJvCgPWJRKV Cq/etfX6vrPigr5Img+lY9cqze32mMWp1G+ykwR4KoeLQkkExx6kAwT8d+Nm2Mq3b+Ak kEFGWfg0RzXiY6R3b5jbQH46rBTkFIcSsg5dzuY1VAZB/qN2PdND0WyzHOVoX/sDmIlf G1bWhTNMmLufIJFW9cbS0CHCD27DWautHcOj1zDL9J0mWXjnjmK7IY5a1KFAFoSyVrD3 j9Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687450241; x=1690042241; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qiGDoiG1y93PPW7mQ2SAaPUCrdr0EnIkEF2xjLc8x+o=; b=OuYLDzXWMNTWShpj/6Vmd4YJqqtEgs7a/tX5ysjfnq2ppbkuLfKTJCTKpDLDmbS6td fNLYnCCXHKXoWuC6sXNFNKvS3Mo+m2qPauIe2GJOfrGALYYIaYukOBWatthz/sBrpOeK ULycTqCWMHix+TBKSoRh2TK1QeGnnnRQA8CdOvlossOt09pGCxAJEl8gSP1YFQewoT0e 7TKc9SY4BSyaclaFowVfWfhd50bOz70QI3/t0romb5xWvzJyRZddG6CMKCrA2lYVIeAu qFEfW4tzbNi4c6UPgYMyoikqLOGZ/O16KWccy1HuGIvDxudWv4gjhISQh/cT8CdAr+OD IbAw== X-Gm-Message-State: AC+VfDy0Ns2OyYT1jYk1BxjB9gxwHLRCperMGhW3eJ3whNi0DYVFuVbp SrHNLXEinKT/aJGf70izu84c0Ies9dZXVEyEITwUDg== X-Google-Smtp-Source: ACHHUZ5M4RURLV917KnJd3MPK+U1TPYAx4Jil2vHUAphCH9oW8qXZeRccJQsIh2dE0Pzlg9PjXcjAQ== X-Received: by 2002:a05:600c:2119:b0:3fa:776e:8c7a with SMTP id u25-20020a05600c211900b003fa776e8c7amr1300704wml.28.1687450241047; Thu, 22 Jun 2023 09:10:41 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Reinoud Zandijk , qemu-arm@nongnu.org, kvm@vger.kernel.org, Marcel Apfelbaum , Stefano Stabellini , Anthony Perard , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Roman Bolshakov , Paolo Bonzini , Paul Durrant , Sunil Muthuswamy , Alexander Graf , Richard Henderson , xen-devel@lists.xenproject.org, Eduardo Habkost , Cameron Esfahani Subject: [PATCH v2 13/16] accel: Rename WHPX 'struct whpx_vcpu' -> AccelCPUState Date: Thu, 22 Jun 2023 18:08:20 +0200 Message-Id: <20230622160823.71851-14-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230622160823.71851-1-philmd@linaro.org> References: <20230622160823.71851-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687450269801100007 We want all accelerators to share the same opaque pointer in CPUState. Rename WHPX 'whpx_vcpu' as 'AccelCPUState'; use the typedef. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/whpx/whpx-all.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 012ba696a9..107b731d3f 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -229,7 +229,7 @@ typedef enum WhpxStepMode { WHPX_STEP_EXCLUSIVE, } WhpxStepMode; =20 -struct whpx_vcpu { +struct AccelCPUState { WHV_EMULATOR_HANDLE emulator; bool window_registered; bool interruptable; @@ -260,9 +260,9 @@ static bool whpx_has_xsave(void) * VP support */ =20 -static struct whpx_vcpu *get_whpx_vcpu(CPUState *cpu) +static AccelCPUState *get_whpx_vcpu(CPUState *cpu) { - return (struct whpx_vcpu *)cpu->accel; + return (AccelCPUState *)cpu->accel; } =20 static WHV_X64_SEGMENT_REGISTER whpx_seg_q2h(const SegmentCache *qs, int v= 86, @@ -390,7 +390,7 @@ static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8) static void whpx_set_registers(CPUState *cpu, int level) { struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; @@ -609,7 +609,7 @@ static void whpx_get_xcrs(CPUState *cpu) static void whpx_get_registers(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; @@ -892,7 +892,7 @@ static const WHV_EMULATOR_CALLBACKS whpx_emu_callbacks = =3D { static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx) { HRESULT hr; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); WHV_EMULATOR_STATUS emu_status; =20 hr =3D whp_dispatch.WHvEmulatorTryMmioEmulation( @@ -917,7 +917,7 @@ static int whpx_handle_portio(CPUState *cpu, WHV_X64_IO_PORT_ACCESS_CONTEXT *ctx) { HRESULT hr; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); WHV_EMULATOR_STATUS emu_status; =20 hr =3D whp_dispatch.WHvEmulatorTryIoEmulation( @@ -1417,7 +1417,7 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exi= t_context_valid) * of QEMU, nor this port by calling WHvSetVirtualProcessorRegiste= rs(). * This is the most common case. */ - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); return vcpu->exit_ctx.VpContext.Rip; } else { /* @@ -1468,7 +1468,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); int irq; @@ -1590,7 +1590,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) =20 static void whpx_vcpu_post_run(CPUState *cpu) { - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); =20 @@ -1617,7 +1617,7 @@ static void whpx_vcpu_process_async_events(CPUState *= cpu) { CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); =20 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && !(env->hflags & HF_SMM_MASK)) { @@ -1656,7 +1656,7 @@ static int whpx_vcpu_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); struct whpx_breakpoint *stepped_over_bp =3D NULL; WhpxStepMode exclusive_step_mode =3D WHPX_STEP_NONE; int ret; @@ -2154,7 +2154,7 @@ int whpx_init_vcpu(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D NULL; + AccelCPUState *vcpu =3D NULL; Error *local_error =3D NULL; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); @@ -2177,7 +2177,7 @@ int whpx_init_vcpu(CPUState *cpu) } } =20 - vcpu =3D g_new0(struct whpx_vcpu, 1); + vcpu =3D g_new0(AccelCPUState, 1); =20 hr =3D whp_dispatch.WHvEmulatorCreateEmulator( &whpx_emu_callbacks, @@ -2252,7 +2252,7 @@ int whpx_init_vcpu(CPUState *cpu) =20 vcpu->interruptable =3D true; cpu->vcpu_dirty =3D true; - cpu->accel =3D (struct AccelCPUState *)vcpu; + cpu->accel =3D (AccelCPUState *)vcpu; max_vcpu_index =3D max(max_vcpu_index, cpu->cpu_index); qemu_add_vm_change_state_handler(whpx_cpu_update_state, cpu->env_ptr); =20 @@ -2290,7 +2290,7 @@ int whpx_vcpu_exec(CPUState *cpu) void whpx_destroy_vcpu(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); =20 whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[88.28.3.230]) by smtp.gmail.com with ESMTPSA id z17-20020a5d6551000000b00307bc4e39e5sm7314320wrv.117.2023.06.22.09.10.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Jun 2023 09:10:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687450251; x=1690042251; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n1vRGyzu8+XqKaMgtN/nMAkP8vtjVhpBIfkdPMVYyfg=; b=SzgUJ/3O2JDLimh3+Agd51LJmZaiaEI8ZFwaKFU+xUs5N8igbv+HWLrxj9PAtNvt2P tWlCEtAkV4Akr6+YlAN8K0+yYGd8sx7dWoQtnO9KdQzwhhCQld65/SzWP89kgi87B8eh lKMQC9nQ2o/IYRKSQG/yO9HtB3B5uhxSrJ9JhYdyhuNC01KDTA0mRGksU/fOnTci3VcF eTy0N5FdKs+2ao4NC9iyl73k4WTq5YyQZ/JcjaHtorbZwzW7L3xdvwCsUkTmug4AIfdv WLk3g3kHwPWZQJTJwWN7mJvQlvPyRQSzb5+sWK5ic1pU1dfvlbmGNaZyANDyv6I1Adx6 w5kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687450251; x=1690042251; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n1vRGyzu8+XqKaMgtN/nMAkP8vtjVhpBIfkdPMVYyfg=; b=DhCndOd/n/HYVzPZ3PNKYfDuIlCD7Ic9QUFOV5biTSLBqjfzegacgZ7gGbSAe0depe zc0NQRf2tKUcQ7EX++PoPOY4IkIcSr4jo5xh0+TCdhKECIlIvG9MvbjbJBLeutE3rMHU jNnIMG7sFiBzzO0G+zZCDmp6GSbYepxL6lfYSc9+pVqBOSpccH5ret6Kxo7DODdkyx92 H+vJIqN7pnRagpx38FNlMahfWuxfH4D5wteiYTmM90CieTasM3UbVDPlieDlrO+9hQ79 6GdLneF/Lor2Mz/5EkYPxzB461a61p0wBcPMhYCGxIPjfqZy6+3Rxsx6K3768hVJaynk IVhg== X-Gm-Message-State: AC+VfDz6Ku74rW5FRK438zxB4XBSY8mDbidJlNEuRztsgfRt56ybCFCJ 7o5JdcC+pgjKDwKrWhMzsnymbCcWBd4i96Zf5/ROaw== X-Google-Smtp-Source: ACHHUZ6Zvkg+/2pI/zQv1tCUfVDDfB62uZn7snk8J9Qv86AyAfhXfm7jju4fWwybVTRViGAkVekuMA== X-Received: by 2002:a5d:4cc2:0:b0:309:5068:9ebe with SMTP id c2-20020a5d4cc2000000b0030950689ebemr12061202wrt.50.1687450250976; Thu, 22 Jun 2023 09:10:50 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Reinoud Zandijk , qemu-arm@nongnu.org, kvm@vger.kernel.org, Marcel Apfelbaum , Stefano Stabellini , Anthony Perard , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Roman Bolshakov , Paolo Bonzini , Paul Durrant , Sunil Muthuswamy , Alexander Graf , Richard Henderson , xen-devel@lists.xenproject.org, Eduardo Habkost , Cameron Esfahani Subject: [PATCH v2 14/16] accel: Inline WHPX get_whpx_vcpu() Date: Thu, 22 Jun 2023 18:08:21 +0200 Message-Id: <20230622160823.71851-15-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230622160823.71851-1-philmd@linaro.org> References: <20230622160823.71851-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687450303963100001 No need for this helper to access the CPUState::accel field. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/whpx/whpx-all.c | 29 ++++++++++------------------- 1 file changed, 10 insertions(+), 19 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 107b731d3f..fdac13c7c1 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -256,15 +256,6 @@ static bool whpx_has_xsave(void) return whpx_xsave_cap.XsaveSupport; } =20 -/* - * VP support - */ - -static AccelCPUState *get_whpx_vcpu(CPUState *cpu) -{ - return (AccelCPUState *)cpu->accel; -} - static WHV_X64_SEGMENT_REGISTER whpx_seg_q2h(const SegmentCache *qs, int v= 86, int r86) { @@ -390,7 +381,7 @@ static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8) static void whpx_set_registers(CPUState *cpu, int level) { struct whpx_state *whpx =3D &whpx_global; - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; @@ -609,7 +600,7 @@ static void whpx_get_xcrs(CPUState *cpu) static void whpx_get_registers(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; @@ -892,7 +883,7 @@ static const WHV_EMULATOR_CALLBACKS whpx_emu_callbacks = =3D { static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx) { HRESULT hr; - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; WHV_EMULATOR_STATUS emu_status; =20 hr =3D whp_dispatch.WHvEmulatorTryMmioEmulation( @@ -917,7 +908,7 @@ static int whpx_handle_portio(CPUState *cpu, WHV_X64_IO_PORT_ACCESS_CONTEXT *ctx) { HRESULT hr; - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; WHV_EMULATOR_STATUS emu_status; =20 hr =3D whp_dispatch.WHvEmulatorTryIoEmulation( @@ -1417,7 +1408,7 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exi= t_context_valid) * of QEMU, nor this port by calling WHvSetVirtualProcessorRegiste= rs(). * This is the most common case. */ - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; return vcpu->exit_ctx.VpContext.Rip; } else { /* @@ -1468,7 +1459,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); int irq; @@ -1590,7 +1581,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) =20 static void whpx_vcpu_post_run(CPUState *cpu) { - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); =20 @@ -1617,7 +1608,7 @@ static void whpx_vcpu_process_async_events(CPUState *= cpu) { CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; =20 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && !(env->hflags & HF_SMM_MASK)) { @@ -1656,7 +1647,7 @@ static int whpx_vcpu_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; struct whpx_breakpoint *stepped_over_bp =3D NULL; WhpxStepMode exclusive_step_mode =3D WHPX_STEP_NONE; int ret; @@ -2290,7 +2281,7 @@ int whpx_vcpu_exec(CPUState *cpu) void whpx_destroy_vcpu(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; - AccelCPUState *vcpu =3D get_whpx_vcpu(cpu); + AccelCPUState *vcpu =3D cpu->accel; =20 whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687450275; cv=none; d=zohomail.com; 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[88.28.3.230]) by smtp.gmail.com with ESMTPSA id o10-20020a1c750a000000b003f604793989sm5662700wmc.18.2023.06.22.09.10.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Jun 2023 09:11:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687450262; x=1690042262; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RRWIGoCMHA30ya/gVErc/hGu4D1zlFhqqYQ3R4zE/Yc=; b=t745U20cpkP9y09qTnHT58ACbcd3dw2pT0XOALfU1Ir9cOGrJC0tQQGMi14LHQqH5g +xN5iBHjW9n+QXm28fWr9Njb7qWILXh0XWDBRqFfu2YucBT5SwObebrG/GaQlCwELZwt DHOfkhf/41MTmSH3goxTxSbaxIpaNwDsJO/1v7YU2KfXKoTDKU99Aucn6p3FVE5QZabF W5J2Osfq7F7e/jQ8jW11xKumOyh2OAqf2lWvTWFVINll7FW5xTDmmX7gZ3z8/ay9JBbI IYobKh9J0ufzicNgz3Xvyz0Vj59VLsF6FkRFQjVU69hk/lED8ZDxatLaPp3ZFSNJDqds EijQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687450262; x=1690042262; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RRWIGoCMHA30ya/gVErc/hGu4D1zlFhqqYQ3R4zE/Yc=; b=FVBG9JfRmeOJC44rqsgOUAkkQoPh0AaCOLYvQrW1l+rFDGn4IcmwzJy9AFFMwHI4Nk YXFs9asTAKQ7kmoOnGxp3OcMCYTgajn8RDXnSi6mRagZHrD/Tv4roj0X2aJ8XijxRNpc h5PTYFTQpxD3vmWFLJl5rBcexa/CZXZ0L2jmBMlGuiQ4r15PFZjIcQ1I8PcZR6NNmJmb ms19KZD4uOTnKLwPIQwKkjS4IKrhrWc+M0ocTL/qn2dk+3WgBOESwJbKxaLNYx66iUbT cBY8SE0aeNFP+99PdoRIWe2VCwLMlmdFb9Ovuru5khpjd3GUotfDNuWnmIZBpysmuJrf +9QA== X-Gm-Message-State: AC+VfDx04IcEJUAD8Zv9ifU+TmkLFCW76PVNuXQ3/G2WLlxU8uM7Lu8m ImBB+tn2rG+7PgdkWcRuCyhx8+lrhdVV/LrR7djtvQ== X-Google-Smtp-Source: ACHHUZ4IIj48058+XZUHFsrbL5xoZOXXaxhGZj98oO1seM+C5zqlcC7U/H84cpkd7gOVxjdKivvkiw== X-Received: by 2002:a05:600c:22c6:b0:3f9:b17a:cb61 with SMTP id 6-20020a05600c22c600b003f9b17acb61mr9888330wmg.13.1687450262084; Thu, 22 Jun 2023 09:11:02 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Reinoud Zandijk , qemu-arm@nongnu.org, kvm@vger.kernel.org, Marcel Apfelbaum , Stefano Stabellini , Anthony Perard , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Roman Bolshakov , Paolo Bonzini , Paul Durrant , Sunil Muthuswamy , Alexander Graf , Richard Henderson , xen-devel@lists.xenproject.org, Eduardo Habkost , Cameron Esfahani Subject: [PATCH v2 15/16] accel: Rename 'cpu_state' -> 'cpu' Date: Thu, 22 Jun 2023 18:08:22 +0200 Message-Id: <20230622160823.71851-16-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230622160823.71851-1-philmd@linaro.org> References: <20230622160823.71851-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687450275866100001 Most of the codebase uses 'CPUState *cpu' or 'CPUState *cs'. While 'cpu_state' is kind of explicit, it makes the code harder to review. Simply rename as 'cpu' like the rest. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Richard Henderson --- target/i386/hvf/x86hvf.h | 12 +- target/i386/hvf/x86hvf.c | 356 +++++++++++++++++++-------------------- 2 files changed, 184 insertions(+), 184 deletions(-) diff --git a/target/i386/hvf/x86hvf.h b/target/i386/hvf/x86hvf.h index db6003d6bd..6527eb90d4 100644 --- a/target/i386/hvf/x86hvf.h +++ b/target/i386/hvf/x86hvf.h @@ -20,15 +20,15 @@ #include "cpu.h" #include "x86_descr.h" =20 -int hvf_process_events(CPUState *); -bool hvf_inject_interrupts(CPUState *); +int hvf_process_events(CPUState *cpu); +bool hvf_inject_interrupts(CPUState *cpu); void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr); void hvf_get_segment(SegmentCache *qseg, struct vmx_segment *vmx_seg); -void hvf_put_xsave(CPUState *cpu_state); -void hvf_put_msrs(CPUState *cpu_state); -void hvf_get_xsave(CPUState *cpu_state); -void hvf_get_msrs(CPUState *cpu_state); +void hvf_put_xsave(CPUState *cpu); +void hvf_put_msrs(CPUState *cpu); +void hvf_get_xsave(CPUState *cpu); +void hvf_get_msrs(CPUState *cpu); void vmx_clear_int_window_exiting(CPUState *cpu); void vmx_update_tpr(CPUState *cpu); #endif diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index 69d4fb8cf5..dfa500b81d 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -70,255 +70,255 @@ void hvf_get_segment(SegmentCache *qseg, struct vmx_s= egment *vmx_seg) (((vmx_seg->ar >> 15) & 1) << DESC_G_SHIFT); } =20 -void hvf_put_xsave(CPUState *cpu_state) +void hvf_put_xsave(CPUState *cpu) { - void *xsave =3D X86_CPU(cpu_state)->env.xsave_buf; - uint32_t xsave_len =3D X86_CPU(cpu_state)->env.xsave_buf_len; + void *xsave =3D X86_CPU(cpu)->env.xsave_buf; + uint32_t xsave_len =3D X86_CPU(cpu)->env.xsave_buf_len; =20 - x86_cpu_xsave_all_areas(X86_CPU(cpu_state), xsave, xsave_len); + x86_cpu_xsave_all_areas(X86_CPU(cpu), xsave, xsave_len); =20 - if (hv_vcpu_write_fpstate(cpu_state->hvf->fd, xsave, xsave_len)) { + if (hv_vcpu_write_fpstate(cpu->hvf->fd, xsave, xsave_len)) { abort(); } } =20 -static void hvf_put_segments(CPUState *cpu_state) +static void hvf_put_segments(CPUState *cpu) { - CPUX86State *env =3D &X86_CPU(cpu_state)->env; + CPUX86State *env =3D &X86_CPU(cpu)->env; struct vmx_segment seg; =20 - wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); - wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE, env->idt.base); + wvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); + wvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_BASE, env->idt.base); =20 - wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); - wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); + wvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); + wvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); =20 - /* wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR2, env->cr[2]); */ - wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3, env->cr[3]); - vmx_update_tpr(cpu_state); - wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER, env->efer); + /* wvmcs(cpu->hvf->fd, VMCS_GUEST_CR2, env->cr[2]); */ + wvmcs(cpu->hvf->fd, VMCS_GUEST_CR3, env->cr[3]); + vmx_update_tpr(cpu); + wvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER, env->efer); =20 - macvm_set_cr4(cpu_state->hvf->fd, env->cr[4]); - macvm_set_cr0(cpu_state->hvf->fd, env->cr[0]); + macvm_set_cr4(cpu->hvf->fd, env->cr[4]); + macvm_set_cr0(cpu->hvf->fd, env->cr[0]); =20 - hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false); - vmx_write_segment_descriptor(cpu_state, &seg, R_CS); + hvf_set_segment(cpu, &seg, &env->segs[R_CS], false); + vmx_write_segment_descriptor(cpu, &seg, R_CS); =20 - hvf_set_segment(cpu_state, &seg, &env->segs[R_DS], false); - vmx_write_segment_descriptor(cpu_state, &seg, R_DS); + hvf_set_segment(cpu, &seg, &env->segs[R_DS], false); + vmx_write_segment_descriptor(cpu, &seg, R_DS); =20 - hvf_set_segment(cpu_state, &seg, &env->segs[R_ES], false); - vmx_write_segment_descriptor(cpu_state, &seg, R_ES); + hvf_set_segment(cpu, &seg, &env->segs[R_ES], false); + vmx_write_segment_descriptor(cpu, &seg, R_ES); =20 - hvf_set_segment(cpu_state, &seg, &env->segs[R_SS], false); - vmx_write_segment_descriptor(cpu_state, &seg, R_SS); + hvf_set_segment(cpu, &seg, &env->segs[R_SS], false); + vmx_write_segment_descriptor(cpu, &seg, R_SS); =20 - hvf_set_segment(cpu_state, &seg, &env->segs[R_FS], false); - vmx_write_segment_descriptor(cpu_state, &seg, R_FS); + hvf_set_segment(cpu, &seg, &env->segs[R_FS], false); + vmx_write_segment_descriptor(cpu, &seg, R_FS); =20 - hvf_set_segment(cpu_state, &seg, &env->segs[R_GS], false); - vmx_write_segment_descriptor(cpu_state, &seg, R_GS); + hvf_set_segment(cpu, &seg, &env->segs[R_GS], false); + vmx_write_segment_descriptor(cpu, &seg, R_GS); =20 - hvf_set_segment(cpu_state, &seg, &env->tr, true); - vmx_write_segment_descriptor(cpu_state, &seg, R_TR); + hvf_set_segment(cpu, &seg, &env->tr, true); + vmx_write_segment_descriptor(cpu, &seg, R_TR); =20 - hvf_set_segment(cpu_state, &seg, &env->ldt, false); - vmx_write_segment_descriptor(cpu_state, &seg, R_LDTR); + hvf_set_segment(cpu, &seg, &env->ldt, false); + vmx_write_segment_descriptor(cpu, &seg, R_LDTR); } =20 -void hvf_put_msrs(CPUState *cpu_state) +void hvf_put_msrs(CPUState *cpu) { - CPUX86State *env =3D &X86_CPU(cpu_state)->env; + CPUX86State *env =3D &X86_CPU(cpu)->env; =20 - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS, + hv_vcpu_write_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_CS, env->sysenter_cs); - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP, + hv_vcpu_write_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_ESP, env->sysenter_esp); - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP, + hv_vcpu_write_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_EIP, env->sysenter_eip); =20 - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_STAR, env->star); + hv_vcpu_write_msr(cpu->hvf->fd, MSR_STAR, env->star); =20 #ifdef TARGET_X86_64 - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_CSTAR, env->cstar); - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, env->kernelgsb= ase); - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FMASK, env->fmask); - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_LSTAR, env->lstar); + hv_vcpu_write_msr(cpu->hvf->fd, MSR_CSTAR, env->cstar); + hv_vcpu_write_msr(cpu->hvf->fd, MSR_KERNELGSBASE, env->kernelgsbase); + hv_vcpu_write_msr(cpu->hvf->fd, MSR_FMASK, env->fmask); + hv_vcpu_write_msr(cpu->hvf->fd, MSR_LSTAR, env->lstar); #endif =20 - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_GSBASE, env->segs[R_GS].base= ); - hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FSBASE, env->segs[R_FS].base= ); + hv_vcpu_write_msr(cpu->hvf->fd, MSR_GSBASE, env->segs[R_GS].base); + hv_vcpu_write_msr(cpu->hvf->fd, MSR_FSBASE, env->segs[R_FS].base); } =20 =20 -void hvf_get_xsave(CPUState *cpu_state) +void hvf_get_xsave(CPUState *cpu) { - void *xsave =3D X86_CPU(cpu_state)->env.xsave_buf; - uint32_t xsave_len =3D X86_CPU(cpu_state)->env.xsave_buf_len; + void *xsave =3D X86_CPU(cpu)->env.xsave_buf; + uint32_t xsave_len =3D X86_CPU(cpu)->env.xsave_buf_len; =20 - if (hv_vcpu_read_fpstate(cpu_state->hvf->fd, xsave, xsave_len)) { + if (hv_vcpu_read_fpstate(cpu->hvf->fd, xsave, xsave_len)) { abort(); } =20 - x86_cpu_xrstor_all_areas(X86_CPU(cpu_state), xsave, xsave_len); + x86_cpu_xrstor_all_areas(X86_CPU(cpu), xsave, xsave_len); } =20 -static void hvf_get_segments(CPUState *cpu_state) +static void hvf_get_segments(CPUState *cpu) { - CPUX86State *env =3D &X86_CPU(cpu_state)->env; + CPUX86State *env =3D &X86_CPU(cpu)->env; =20 struct vmx_segment seg; =20 env->interrupt_injected =3D -1; =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_CS); + vmx_read_segment_descriptor(cpu, &seg, R_CS); hvf_get_segment(&env->segs[R_CS], &seg); =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_DS); + vmx_read_segment_descriptor(cpu, &seg, R_DS); hvf_get_segment(&env->segs[R_DS], &seg); =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_ES); + vmx_read_segment_descriptor(cpu, &seg, R_ES); hvf_get_segment(&env->segs[R_ES], &seg); =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_FS); + vmx_read_segment_descriptor(cpu, &seg, R_FS); hvf_get_segment(&env->segs[R_FS], &seg); =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_GS); + vmx_read_segment_descriptor(cpu, &seg, R_GS); hvf_get_segment(&env->segs[R_GS], &seg); =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_SS); + vmx_read_segment_descriptor(cpu, &seg, R_SS); hvf_get_segment(&env->segs[R_SS], &seg); =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_TR); + vmx_read_segment_descriptor(cpu, &seg, R_TR); hvf_get_segment(&env->tr, &seg); =20 - vmx_read_segment_descriptor(cpu_state, &seg, R_LDTR); + vmx_read_segment_descriptor(cpu, &seg, R_LDTR); hvf_get_segment(&env->ldt, &seg); =20 - env->idt.limit =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT); - env->idt.base =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE); - env->gdt.limit =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT); - env->gdt.base =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE); + env->idt.limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_LIMIT); + env->idt.base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_BASE); + env->gdt.limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT); + env->gdt.base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE); =20 - env->cr[0] =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR0); + env->cr[0] =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0); env->cr[2] =3D 0; - env->cr[3] =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3); - env->cr[4] =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR4); + env->cr[3] =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR3); + env->cr[4] =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4); =20 - env->efer =3D rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER); + env->efer =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER); } =20 -void hvf_get_msrs(CPUState *cpu_state) +void hvf_get_msrs(CPUState *cpu) { - CPUX86State *env =3D &X86_CPU(cpu_state)->env; + CPUX86State *env =3D &X86_CPU(cpu)->env; uint64_t tmp; =20 - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS, &tmp); + hv_vcpu_read_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_CS, &tmp); env->sysenter_cs =3D tmp; =20 - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP, &tmp); + hv_vcpu_read_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_ESP, &tmp); env->sysenter_esp =3D tmp; =20 - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP, &tmp); + hv_vcpu_read_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_EIP, &tmp); env->sysenter_eip =3D tmp; =20 - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_STAR, &env->star); + hv_vcpu_read_msr(cpu->hvf->fd, MSR_STAR, &env->star); =20 #ifdef TARGET_X86_64 - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_CSTAR, &env->cstar); - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, &env->kernelgsb= ase); - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_FMASK, &env->fmask); - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_LSTAR, &env->lstar); + hv_vcpu_read_msr(cpu->hvf->fd, MSR_CSTAR, &env->cstar); + hv_vcpu_read_msr(cpu->hvf->fd, MSR_KERNELGSBASE, &env->kernelgsbase); + hv_vcpu_read_msr(cpu->hvf->fd, MSR_FMASK, &env->fmask); + hv_vcpu_read_msr(cpu->hvf->fd, MSR_LSTAR, &env->lstar); #endif =20 - hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_APICBASE, &tmp); + hv_vcpu_read_msr(cpu->hvf->fd, MSR_IA32_APICBASE, &tmp); =20 - env->tsc =3D rdtscp() + rvmcs(cpu_state->hvf->fd, VMCS_TSC_OFFSET); + env->tsc =3D rdtscp() + rvmcs(cpu->hvf->fd, VMCS_TSC_OFFSET); } =20 -int hvf_put_registers(CPUState *cpu_state) +int hvf_put_registers(CPUState *cpu) { - X86CPU *x86cpu =3D X86_CPU(cpu_state); + X86CPU *x86cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86cpu->env; =20 - wreg(cpu_state->hvf->fd, HV_X86_RAX, env->regs[R_EAX]); - wreg(cpu_state->hvf->fd, HV_X86_RBX, env->regs[R_EBX]); - wreg(cpu_state->hvf->fd, HV_X86_RCX, env->regs[R_ECX]); - wreg(cpu_state->hvf->fd, HV_X86_RDX, env->regs[R_EDX]); - wreg(cpu_state->hvf->fd, HV_X86_RBP, env->regs[R_EBP]); - wreg(cpu_state->hvf->fd, HV_X86_RSP, env->regs[R_ESP]); - wreg(cpu_state->hvf->fd, HV_X86_RSI, env->regs[R_ESI]); - wreg(cpu_state->hvf->fd, HV_X86_RDI, env->regs[R_EDI]); - wreg(cpu_state->hvf->fd, HV_X86_R8, env->regs[8]); - wreg(cpu_state->hvf->fd, HV_X86_R9, env->regs[9]); - wreg(cpu_state->hvf->fd, HV_X86_R10, env->regs[10]); - wreg(cpu_state->hvf->fd, HV_X86_R11, env->regs[11]); - wreg(cpu_state->hvf->fd, HV_X86_R12, env->regs[12]); - wreg(cpu_state->hvf->fd, HV_X86_R13, env->regs[13]); - wreg(cpu_state->hvf->fd, HV_X86_R14, env->regs[14]); - wreg(cpu_state->hvf->fd, HV_X86_R15, env->regs[15]); - wreg(cpu_state->hvf->fd, HV_X86_RFLAGS, env->eflags); - wreg(cpu_state->hvf->fd, HV_X86_RIP, env->eip); + wreg(cpu->hvf->fd, HV_X86_RAX, env->regs[R_EAX]); + wreg(cpu->hvf->fd, HV_X86_RBX, env->regs[R_EBX]); + wreg(cpu->hvf->fd, HV_X86_RCX, env->regs[R_ECX]); + wreg(cpu->hvf->fd, HV_X86_RDX, env->regs[R_EDX]); + wreg(cpu->hvf->fd, HV_X86_RBP, env->regs[R_EBP]); + wreg(cpu->hvf->fd, HV_X86_RSP, env->regs[R_ESP]); + wreg(cpu->hvf->fd, HV_X86_RSI, env->regs[R_ESI]); + wreg(cpu->hvf->fd, HV_X86_RDI, env->regs[R_EDI]); + wreg(cpu->hvf->fd, HV_X86_R8, env->regs[8]); + wreg(cpu->hvf->fd, HV_X86_R9, env->regs[9]); + wreg(cpu->hvf->fd, HV_X86_R10, env->regs[10]); + wreg(cpu->hvf->fd, HV_X86_R11, env->regs[11]); + wreg(cpu->hvf->fd, HV_X86_R12, env->regs[12]); + wreg(cpu->hvf->fd, HV_X86_R13, env->regs[13]); + wreg(cpu->hvf->fd, HV_X86_R14, env->regs[14]); + wreg(cpu->hvf->fd, HV_X86_R15, env->regs[15]); + wreg(cpu->hvf->fd, HV_X86_RFLAGS, env->eflags); + wreg(cpu->hvf->fd, HV_X86_RIP, env->eip); =20 - wreg(cpu_state->hvf->fd, HV_X86_XCR0, env->xcr0); + wreg(cpu->hvf->fd, HV_X86_XCR0, env->xcr0); =20 - hvf_put_xsave(cpu_state); + hvf_put_xsave(cpu); =20 - hvf_put_segments(cpu_state); + hvf_put_segments(cpu); =20 - hvf_put_msrs(cpu_state); + hvf_put_msrs(cpu); =20 - wreg(cpu_state->hvf->fd, HV_X86_DR0, env->dr[0]); - wreg(cpu_state->hvf->fd, HV_X86_DR1, env->dr[1]); - wreg(cpu_state->hvf->fd, HV_X86_DR2, env->dr[2]); - wreg(cpu_state->hvf->fd, HV_X86_DR3, env->dr[3]); - wreg(cpu_state->hvf->fd, HV_X86_DR4, env->dr[4]); - wreg(cpu_state->hvf->fd, HV_X86_DR5, env->dr[5]); - wreg(cpu_state->hvf->fd, HV_X86_DR6, env->dr[6]); - wreg(cpu_state->hvf->fd, HV_X86_DR7, env->dr[7]); + wreg(cpu->hvf->fd, HV_X86_DR0, env->dr[0]); + wreg(cpu->hvf->fd, HV_X86_DR1, env->dr[1]); + wreg(cpu->hvf->fd, HV_X86_DR2, env->dr[2]); + wreg(cpu->hvf->fd, HV_X86_DR3, env->dr[3]); + wreg(cpu->hvf->fd, HV_X86_DR4, env->dr[4]); + wreg(cpu->hvf->fd, HV_X86_DR5, env->dr[5]); + wreg(cpu->hvf->fd, HV_X86_DR6, env->dr[6]); + wreg(cpu->hvf->fd, HV_X86_DR7, env->dr[7]); =20 return 0; } =20 -int hvf_get_registers(CPUState *cpu_state) +int hvf_get_registers(CPUState *cpu) { - X86CPU *x86cpu =3D X86_CPU(cpu_state); + X86CPU *x86cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86cpu->env; =20 - env->regs[R_EAX] =3D rreg(cpu_state->hvf->fd, HV_X86_RAX); - env->regs[R_EBX] =3D rreg(cpu_state->hvf->fd, HV_X86_RBX); - env->regs[R_ECX] =3D rreg(cpu_state->hvf->fd, HV_X86_RCX); - env->regs[R_EDX] =3D rreg(cpu_state->hvf->fd, HV_X86_RDX); - env->regs[R_EBP] =3D rreg(cpu_state->hvf->fd, HV_X86_RBP); - env->regs[R_ESP] =3D rreg(cpu_state->hvf->fd, HV_X86_RSP); - env->regs[R_ESI] =3D rreg(cpu_state->hvf->fd, HV_X86_RSI); - env->regs[R_EDI] =3D rreg(cpu_state->hvf->fd, HV_X86_RDI); - env->regs[8] =3D rreg(cpu_state->hvf->fd, HV_X86_R8); - env->regs[9] =3D rreg(cpu_state->hvf->fd, HV_X86_R9); - env->regs[10] =3D rreg(cpu_state->hvf->fd, HV_X86_R10); - env->regs[11] =3D rreg(cpu_state->hvf->fd, HV_X86_R11); - env->regs[12] =3D rreg(cpu_state->hvf->fd, HV_X86_R12); - env->regs[13] =3D rreg(cpu_state->hvf->fd, HV_X86_R13); - env->regs[14] =3D rreg(cpu_state->hvf->fd, HV_X86_R14); - env->regs[15] =3D rreg(cpu_state->hvf->fd, HV_X86_R15); + env->regs[R_EAX] =3D rreg(cpu->hvf->fd, HV_X86_RAX); + env->regs[R_EBX] =3D rreg(cpu->hvf->fd, HV_X86_RBX); + env->regs[R_ECX] =3D rreg(cpu->hvf->fd, HV_X86_RCX); + env->regs[R_EDX] =3D rreg(cpu->hvf->fd, HV_X86_RDX); + env->regs[R_EBP] =3D rreg(cpu->hvf->fd, HV_X86_RBP); + env->regs[R_ESP] =3D rreg(cpu->hvf->fd, HV_X86_RSP); + env->regs[R_ESI] =3D rreg(cpu->hvf->fd, HV_X86_RSI); + env->regs[R_EDI] =3D rreg(cpu->hvf->fd, HV_X86_RDI); + env->regs[8] =3D rreg(cpu->hvf->fd, HV_X86_R8); + env->regs[9] =3D rreg(cpu->hvf->fd, HV_X86_R9); + env->regs[10] =3D rreg(cpu->hvf->fd, HV_X86_R10); + env->regs[11] =3D rreg(cpu->hvf->fd, HV_X86_R11); + env->regs[12] =3D rreg(cpu->hvf->fd, HV_X86_R12); + env->regs[13] =3D rreg(cpu->hvf->fd, HV_X86_R13); + env->regs[14] =3D rreg(cpu->hvf->fd, HV_X86_R14); + env->regs[15] =3D rreg(cpu->hvf->fd, HV_X86_R15); =20 - env->eflags =3D rreg(cpu_state->hvf->fd, HV_X86_RFLAGS); - env->eip =3D rreg(cpu_state->hvf->fd, HV_X86_RIP); + env->eflags =3D rreg(cpu->hvf->fd, HV_X86_RFLAGS); + env->eip =3D rreg(cpu->hvf->fd, HV_X86_RIP); =20 - hvf_get_xsave(cpu_state); - env->xcr0 =3D rreg(cpu_state->hvf->fd, HV_X86_XCR0); + hvf_get_xsave(cpu); + env->xcr0 =3D rreg(cpu->hvf->fd, HV_X86_XCR0); =20 - hvf_get_segments(cpu_state); - hvf_get_msrs(cpu_state); + hvf_get_segments(cpu); + hvf_get_msrs(cpu); =20 - env->dr[0] =3D rreg(cpu_state->hvf->fd, HV_X86_DR0); - env->dr[1] =3D rreg(cpu_state->hvf->fd, HV_X86_DR1); - env->dr[2] =3D rreg(cpu_state->hvf->fd, HV_X86_DR2); - env->dr[3] =3D rreg(cpu_state->hvf->fd, HV_X86_DR3); - env->dr[4] =3D rreg(cpu_state->hvf->fd, HV_X86_DR4); - env->dr[5] =3D rreg(cpu_state->hvf->fd, HV_X86_DR5); - env->dr[6] =3D rreg(cpu_state->hvf->fd, HV_X86_DR6); - env->dr[7] =3D rreg(cpu_state->hvf->fd, HV_X86_DR7); + env->dr[0] =3D rreg(cpu->hvf->fd, HV_X86_DR0); + env->dr[1] =3D rreg(cpu->hvf->fd, HV_X86_DR1); + env->dr[2] =3D rreg(cpu->hvf->fd, HV_X86_DR2); + env->dr[3] =3D rreg(cpu->hvf->fd, HV_X86_DR3); + env->dr[4] =3D rreg(cpu->hvf->fd, HV_X86_DR4); + env->dr[5] =3D rreg(cpu->hvf->fd, HV_X86_DR5); + env->dr[6] =3D rreg(cpu->hvf->fd, HV_X86_DR6); + env->dr[7] =3D rreg(cpu->hvf->fd, HV_X86_DR7); =20 x86_update_hflags(env); return 0; @@ -340,9 +340,9 @@ void vmx_clear_int_window_exiting(CPUState *cpu) ~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); } =20 -bool hvf_inject_interrupts(CPUState *cpu_state) +bool hvf_inject_interrupts(CPUState *cpu) { - X86CPU *x86cpu =3D X86_CPU(cpu_state); + X86CPU *x86cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86cpu->env; =20 uint8_t vector; @@ -372,89 +372,89 @@ bool hvf_inject_interrupts(CPUState *cpu_state) uint64_t info =3D 0; if (have_event) { info =3D vector | intr_type | VMCS_INTR_VALID; - uint64_t reason =3D rvmcs(cpu_state->hvf->fd, VMCS_EXIT_REASON); + uint64_t reason =3D rvmcs(cpu->hvf->fd, VMCS_EXIT_REASON); if (env->nmi_injected && reason !=3D EXIT_REASON_TASK_SWITCH) { - vmx_clear_nmi_blocking(cpu_state); + vmx_clear_nmi_blocking(cpu); } =20 if (!(env->hflags2 & HF2_NMI_MASK) || intr_type !=3D VMCS_INTR_T_N= MI) { info &=3D ~(1 << 12); /* clear undefined bit */ if (intr_type =3D=3D VMCS_INTR_T_SWINTR || intr_type =3D=3D VMCS_INTR_T_SWEXCEPTION) { - wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INST_LENGTH, env->ins= _len); + wvmcs(cpu->hvf->fd, VMCS_ENTRY_INST_LENGTH, env->ins_len); } =20 if (env->has_error_code) { - wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_EXCEPTION_ERROR, + wvmcs(cpu->hvf->fd, VMCS_ENTRY_EXCEPTION_ERROR, env->error_code); /* Indicate that VMCS_ENTRY_EXCEPTION_ERROR is valid */ info |=3D VMCS_INTR_DEL_ERRCODE; } /*printf("reinject %lx err %d\n", info, err);*/ - wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info); + wvmcs(cpu->hvf->fd, VMCS_ENTRY_INTR_INFO, info); }; } =20 - if (cpu_state->interrupt_request & CPU_INTERRUPT_NMI) { + if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) { - cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_NMI; + cpu->interrupt_request &=3D ~CPU_INTERRUPT_NMI; info =3D VMCS_INTR_VALID | VMCS_INTR_T_NMI | EXCP02_NMI; - wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info); + wvmcs(cpu->hvf->fd, VMCS_ENTRY_INTR_INFO, info); } else { - vmx_set_nmi_window_exiting(cpu_state); + vmx_set_nmi_window_exiting(cpu); } } =20 if (!(env->hflags & HF_INHIBIT_IRQ_MASK) && - (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) && + (cpu->interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK) && !(info & VMCS_INTR_VALID)) { int line =3D cpu_get_pic_interrupt(&x86cpu->env); - cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_HARD; + cpu->interrupt_request &=3D ~CPU_INTERRUPT_HARD; if (line >=3D 0) { - wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, line | + wvmcs(cpu->hvf->fd, VMCS_ENTRY_INTR_INFO, line | VMCS_INTR_VALID | VMCS_INTR_T_HWINTR); } } - if (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) { - vmx_set_int_window_exiting(cpu_state); + if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { + vmx_set_int_window_exiting(cpu); } - return (cpu_state->interrupt_request + return (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)); } =20 -int hvf_process_events(CPUState *cpu_state) +int hvf_process_events(CPUState *cpu) { - X86CPU *cpu =3D X86_CPU(cpu_state); + X86CPU *cpu =3D X86_CPU(cpu); CPUX86State *env =3D &cpu->env; =20 - if (!cpu_state->vcpu_dirty) { + if (!cpu->vcpu_dirty) { /* light weight sync for CPU_INTERRUPT_HARD and IF_MASK */ - env->eflags =3D rreg(cpu_state->hvf->fd, HV_X86_RFLAGS); + env->eflags =3D rreg(cpu->hvf->fd, HV_X86_RFLAGS); } =20 - if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) { - cpu_synchronize_state(cpu_state); + if (cpu->interrupt_request & CPU_INTERRUPT_INIT) { + cpu_synchronize_state(cpu); do_cpu_init(cpu); } =20 - if (cpu_state->interrupt_request & CPU_INTERRUPT_POLL) { - cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_POLL; + if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { + cpu->interrupt_request &=3D ~CPU_INTERRUPT_POLL; apic_poll_irq(cpu->apic_state); } - if (((cpu_state->interrupt_request & CPU_INTERRUPT_HARD) && + if (((cpu->interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) || - (cpu_state->interrupt_request & CPU_INTERRUPT_NMI)) { - cpu_state->halted =3D 0; + (cpu->interrupt_request & CPU_INTERRUPT_NMI)) { + cpu->halted =3D 0; } - if (cpu_state->interrupt_request & CPU_INTERRUPT_SIPI) { - cpu_synchronize_state(cpu_state); + if (cpu->interrupt_request & CPU_INTERRUPT_SIPI) { + cpu_synchronize_state(cpu); do_cpu_sipi(cpu); } - if (cpu_state->interrupt_request & CPU_INTERRUPT_TPR) { - cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_TPR; - cpu_synchronize_state(cpu_state); + if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { + cpu->interrupt_request &=3D ~CPU_INTERRUPT_TPR; + cpu_synchronize_state(cpu); apic_handle_tpr_access_report(cpu->apic_state, env->eip, env->tpr_access_type); } - return cpu_state->halted; + return cpu->halted; } --=20 2.38.1 From nobody Sat May 11 19:14:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[88.28.3.230]) by smtp.gmail.com with ESMTPSA id b8-20020adff248000000b003063772a55bsm7391445wrp.61.2023.06.22.09.11.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 22 Jun 2023 09:11:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687450274; x=1690042274; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g0kqJburgdu472vwwAFuv1VsrJpQeVQ9WWi/MNQJgyg=; b=mma7h9gmmY4GnoSRRCSQvU9Qy10jjwmCi2iZ7fOsclvwbpwegoScbrs9EXfutkFf1e wYnXGFwEXGwinPc1Vg/+zjLHTfo+wjDik3vGn35DoKJAKKdZCaYazdYyqdSsFa3K5gb7 HEjE/6QTe9WEqnWBc+pRXoA2Ie84xeSnCVs7bbIvaCjtpFjsYXJWABaAyC9robQektco FjoaDzRfTjGFD+9hQyISHIQzXkm75l/GHcWQMzlinvAiUMw1NMTqKwm+6S0WgF9Ef0qD KtPmdDZ/HrQzhPSpAFtIcc4xB0LYx5S1T/ki95mOXMVGeBBxDNInLMe5QHAxzflXHVGH aiOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687450274; x=1690042274; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g0kqJburgdu472vwwAFuv1VsrJpQeVQ9WWi/MNQJgyg=; b=PirQofuZ67GxjJYhuu9U6ZXjqH4pTsnF567oEsO0n9MpDKBAahFoA8PpvLda1tebRe vm3efdBdZMXsJbOG3UqA9VJWJ+C9rQVqWOdOkh5VgYHrhniJmatOM2e84Jh8yObXft9a jgJ4JXR0fIL/XHJ/M0MK4ISZW4SxcCWtKHC7CENozAJM1b7A25Z3vTZ4AAt/GkDCpeJj VQ3SuErFXZnhSkpO6R0T6kY5UVSAH50uGV/JrOE0QjxgCsOBdb/8GOiVrh5x4Is3XRoh Npd2ZYELo64jO/7G7hdddIAk0wc+8V1pFy2nOXGgF/XAixU0+JS+VryG/xpx1a4yb2z7 20pg== X-Gm-Message-State: AC+VfDyGLsIlDTzcrlQT13XFcour2pfkMa40PS0FQv2GmpDQXF5rWs9H D0z1RO9bXizBM+lKEFBkhpXnVx+QNqi0A8g4XxNhgQ== X-Google-Smtp-Source: ACHHUZ4vOPPOLo7QmgVClajvoGsLDBUccKzS2E8fCJ2AC82Z4T83Vnb7AaojHy9ATpjMS6WULzLkyg== X-Received: by 2002:a05:6000:12c8:b0:311:2888:9f95 with SMTP id l8-20020a05600012c800b0031128889f95mr16140447wrx.23.1687450272301; Thu, 22 Jun 2023 09:11:12 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Reinoud Zandijk , qemu-arm@nongnu.org, kvm@vger.kernel.org, Marcel Apfelbaum , Stefano Stabellini , Anthony Perard , Yanan Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Roman Bolshakov , Paolo Bonzini , Paul Durrant , Sunil Muthuswamy , Alexander Graf , Richard Henderson , xen-devel@lists.xenproject.org, Eduardo Habkost , Cameron Esfahani Subject: [PATCH v2 16/16] accel: Rename HVF 'struct hvf_vcpu_state' -> AccelCPUState Date: Thu, 22 Jun 2023 18:08:23 +0200 Message-Id: <20230622160823.71851-17-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230622160823.71851-1-philmd@linaro.org> References: <20230622160823.71851-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687450307167100002 We want all accelerators to share the same opaque pointer in CPUState. Rename the 'hvf_vcpu_state' structure as 'AccelCPUState'. Use the generic 'accel' field of CPUState instead of 'hvf'. Replace g_malloc0() by g_new0() for readability. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- Not even built on x86! --- include/hw/core/cpu.h | 4 - include/sysemu/hvf_int.h | 2 +- target/i386/hvf/vmx.h | 22 ++-- accel/hvf/hvf-accel-ops.c | 18 ++-- target/arm/hvf/hvf.c | 108 +++++++++---------- target/i386/hvf/hvf.c | 104 +++++++++--------- target/i386/hvf/x86.c | 28 ++--- target/i386/hvf/x86_descr.c | 26 ++--- target/i386/hvf/x86_emu.c | 62 +++++------ target/i386/hvf/x86_mmu.c | 4 +- target/i386/hvf/x86_task.c | 10 +- target/i386/hvf/x86hvf.c | 208 ++++++++++++++++++------------------ 12 files changed, 296 insertions(+), 300 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 01388d5918..afde06e054 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -240,8 +240,6 @@ typedef struct SavedIOTLB { struct KVMState; struct kvm_run; =20 -struct hvf_vcpu_state; - /* work queue */ =20 /* The union type allows passing of 64 bit target pointers on 32 bit @@ -441,8 +439,6 @@ struct CPUState { /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ bool prctl_unalign_sigbus; =20 - struct hvf_vcpu_state *hvf; - /* track IOMMUs whose translations we've cached in the TCG TLB */ GArray *iommu_notifiers; }; diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index 6ab119e49f..5237943952 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -49,7 +49,7 @@ struct HVFState { }; extern HVFState *hvf_state; =20 -struct hvf_vcpu_state { +struct AccelvCPUState { uint64_t fd; void *exit; bool vtimer_masked; diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h index fcd9a95e5b..0fffcfa46c 100644 --- a/target/i386/hvf/vmx.h +++ b/target/i386/hvf/vmx.h @@ -180,15 +180,15 @@ static inline void macvm_set_rip(CPUState *cpu, uint6= 4_t rip) uint64_t val; =20 /* BUG, should take considering overlap.. */ - wreg(cpu->hvf->fd, HV_X86_RIP, rip); + wreg(cpu->accel->fd, HV_X86_RIP, rip); env->eip =3D rip; =20 /* after moving forward in rip, we need to clean INTERRUPTABILITY */ - val =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY); + val =3D rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY); if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { env->hflags &=3D ~HF_INHIBIT_IRQ_MASK; - wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, + wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)); } @@ -200,9 +200,9 @@ static inline void vmx_clear_nmi_blocking(CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; =20 env->hflags2 &=3D ~HF2_NMI_MASK; - uint32_t gi =3D (uint32_t) rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBI= LITY); + uint32_t gi =3D (uint32_t) rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTI= BILITY); gi &=3D ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING; - wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); + wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); } =20 static inline void vmx_set_nmi_blocking(CPUState *cpu) @@ -211,16 +211,16 @@ static inline void vmx_set_nmi_blocking(CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; =20 env->hflags2 |=3D HF2_NMI_MASK; - uint32_t gi =3D (uint32_t)rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBIL= ITY); + uint32_t gi =3D (uint32_t)rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIB= ILITY); gi |=3D VMCS_INTERRUPTIBILITY_NMI_BLOCKING; - wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); + wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); } =20 static inline void vmx_set_nmi_window_exiting(CPUState *cpu) { uint64_t val; - val =3D rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val | + val =3D rvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING); =20 } @@ -229,8 +229,8 @@ static inline void vmx_clear_nmi_window_exiting(CPUStat= e *cpu) { =20 uint64_t val; - val =3D rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val & + val =3D rvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING); } =20 diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 9c3da03c94..6b95933264 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -372,19 +372,19 @@ type_init(hvf_type_init); =20 static void hvf_vcpu_destroy(CPUState *cpu) { - hv_return_t ret =3D hv_vcpu_destroy(cpu->hvf->fd); + hv_return_t ret =3D hv_vcpu_destroy(cpu->accel->fd); assert_hvf_ok(ret); =20 hvf_arch_vcpu_destroy(cpu); - g_free(cpu->hvf); - cpu->hvf =3D NULL; + g_free(cpu->accel); + cpu->accel =3D NULL; } =20 static int hvf_init_vcpu(CPUState *cpu) { int r; =20 - cpu->hvf =3D g_malloc0(sizeof(*cpu->hvf)); + cpu->accel =3D g_new0(struct AccelvCPUState, 1); =20 /* init cpu signals */ struct sigaction sigact; @@ -393,18 +393,18 @@ static int hvf_init_vcpu(CPUState *cpu) sigact.sa_handler =3D dummy_signal; sigaction(SIG_IPI, &sigact, NULL); =20 - pthread_sigmask(SIG_BLOCK, NULL, &cpu->hvf->unblock_ipi_mask); - sigdelset(&cpu->hvf->unblock_ipi_mask, SIG_IPI); + pthread_sigmask(SIG_BLOCK, NULL, &cpu->accel->unblock_ipi_mask); + sigdelset(&cpu->accel->unblock_ipi_mask, SIG_IPI); =20 #ifdef __aarch64__ - r =3D hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit= , NULL); + r =3D hv_vcpu_create(&cpu->accel->fd, (hv_vcpu_exit_t **)&cpu->accel->= exit, NULL); #else - r =3D hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT); + r =3D hv_vcpu_create((hv_vcpuid_t *)&cpu->accel->fd, HV_VCPU_DEFAULT); #endif cpu->vcpu_dirty =3D 1; assert_hvf_ok(r); =20 - cpu->hvf->guest_debug_enabled =3D false; + cpu->accel->guest_debug_enabled =3D false; =20 return hvf_arch_init_vcpu(cpu); } diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 8f72624586..8fce64bbf6 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -544,29 +544,29 @@ int hvf_get_registers(CPUState *cpu) int i; =20 for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { - ret =3D hv_vcpu_get_reg(cpu->hvf->fd, hvf_reg_match[i].reg, &val); + ret =3D hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val= ); *(uint64_t *)((void *)env + hvf_reg_match[i].offset) =3D val; assert_hvf_ok(ret); } =20 for (i =3D 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { - ret =3D hv_vcpu_get_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].r= eg, + ret =3D hv_vcpu_get_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i]= .reg, &fpval); memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpv= al)); assert_hvf_ok(ret); } =20 val =3D 0; - ret =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPCR, &val); + ret =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPCR, &val); assert_hvf_ok(ret); vfp_set_fpcr(env, val); =20 val =3D 0; - ret =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPSR, &val); + ret =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPSR, &val); assert_hvf_ok(ret); vfp_set_fpsr(env, val); =20 - ret =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_CPSR, &val); + ret =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_CPSR, &val); assert_hvf_ok(ret); pstate_write(env, val); =20 @@ -575,7 +575,7 @@ int hvf_get_registers(CPUState *cpu) continue; } =20 - if (cpu->hvf->guest_debug_enabled) { + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_sreg_match[i].reg) { case HV_SYS_REG_DBGBVR0_EL1: @@ -661,7 +661,7 @@ int hvf_get_registers(CPUState *cpu) } } =20 - ret =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &= val); + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg,= &val); assert_hvf_ok(ret); =20 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] =3D val; @@ -684,24 +684,24 @@ int hvf_put_registers(CPUState *cpu) =20 for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { val =3D *(uint64_t *)((void *)env + hvf_reg_match[i].offset); - ret =3D hv_vcpu_set_reg(cpu->hvf->fd, hvf_reg_match[i].reg, val); + ret =3D hv_vcpu_set_reg(cpu->accel->fd, hvf_reg_match[i].reg, val); assert_hvf_ok(ret); } =20 for (i =3D 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpv= al)); - ret =3D hv_vcpu_set_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].r= eg, + ret =3D hv_vcpu_set_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i]= .reg, fpval); assert_hvf_ok(ret); } =20 - ret =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPCR, vfp_get_fpcr(env)); + ret =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPCR, vfp_get_fpcr(env)= ); assert_hvf_ok(ret); =20 - ret =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPSR, vfp_get_fpsr(env)); + ret =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPSR, vfp_get_fpsr(env)= ); assert_hvf_ok(ret); =20 - ret =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_CPSR, pstate_read(env)); + ret =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_CPSR, pstate_read(env)); assert_hvf_ok(ret); =20 aarch64_save_sp(env, arm_current_el(env)); @@ -712,7 +712,7 @@ int hvf_put_registers(CPUState *cpu) continue; } =20 - if (cpu->hvf->guest_debug_enabled) { + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_sreg_match[i].reg) { case HV_SYS_REG_DBGBVR0_EL1: @@ -789,11 +789,11 @@ int hvf_put_registers(CPUState *cpu) } =20 val =3D arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; - ret =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, v= al); + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg,= val); assert_hvf_ok(ret); } =20 - ret =3D hv_vcpu_set_vtimer_offset(cpu->hvf->fd, hvf_state->vtimer_offs= et); + ret =3D hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_of= fset); assert_hvf_ok(ret); =20 return 0; @@ -814,7 +814,7 @@ static void hvf_set_reg(CPUState *cpu, int rt, uint64_t= val) flush_cpu_state(cpu); =20 if (rt < 31) { - r =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_X0 + rt, val); + r =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_X0 + rt, val); assert_hvf_ok(r); } } @@ -827,7 +827,7 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) flush_cpu_state(cpu); =20 if (rt < 31) { - r =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_X0 + rt, &val); + r =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_X0 + rt, &val); assert_hvf_ok(r); } =20 @@ -969,22 +969,22 @@ int hvf_arch_init_vcpu(CPUState *cpu) assert(write_cpustate_to_list(arm_cpu, false)); =20 /* Set CP_NO_RAW system registers on init */ - ret =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1, + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MIDR_EL1, arm_cpu->midr); assert_hvf_ok(ret); =20 - ret =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1, + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MPIDR_EL1, arm_cpu->mp_affinity); assert_hvf_ok(ret); =20 - ret =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, = &pfr); + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1= , &pfr); assert_hvf_ok(ret); pfr |=3D env->gicv3state ? (1 << 24) : 0; - ret =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, = pfr); + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1= , pfr); assert_hvf_ok(ret); =20 /* We're limited to underlying hardware caps, override internal versio= ns */ - ret =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL= 1, &arm_cpu->isar.id_aa64mmfr0); assert_hvf_ok(ret); =20 @@ -994,7 +994,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) void hvf_kick_vcpu_thread(CPUState *cpu) { cpus_kick_thread(cpu); - hv_vcpus_exit(&cpu->hvf->fd, 1); + hv_vcpus_exit(&cpu->accel->fd, 1); } =20 static void hvf_raise_exception(CPUState *cpu, uint32_t excp, @@ -1678,13 +1678,13 @@ static int hvf_inject_interrupts(CPUState *cpu) { if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { trace_hvf_inject_fiq(); - hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_FIQ, + hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_FI= Q, true); } =20 if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { trace_hvf_inject_irq(); - hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_IRQ, + hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_IR= Q, true); } =20 @@ -1718,7 +1718,7 @@ static void hvf_wait_for_ipi(CPUState *cpu, struct ti= mespec *ts) */ qatomic_set_mb(&cpu->thread_kicked, false); qemu_mutex_unlock_iothread(); - pselect(0, 0, 0, 0, ts, &cpu->hvf->unblock_ipi_mask); + pselect(0, 0, 0, 0, ts, &cpu->accel->unblock_ipi_mask); qemu_mutex_lock_iothread(); } =20 @@ -1739,7 +1739,7 @@ static void hvf_wfi(CPUState *cpu) return; } =20 - r =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); + r =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ct= l); assert_hvf_ok(r); =20 if (!(ctl & 1) || (ctl & 2)) { @@ -1748,7 +1748,7 @@ static void hvf_wfi(CPUState *cpu) return; } =20 - r =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cva= l); + r =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, &c= val); assert_hvf_ok(r); =20 ticks_to_sleep =3D cval - hvf_vtimer_val(); @@ -1781,12 +1781,12 @@ static void hvf_sync_vtimer(CPUState *cpu) uint64_t ctl; bool irq_state; =20 - if (!cpu->hvf->vtimer_masked) { + if (!cpu->accel->vtimer_masked) { /* We will get notified on vtimer changes by hvf, nothing to do */ return; } =20 - r =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); + r =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ct= l); assert_hvf_ok(r); =20 irq_state =3D (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS= )) =3D=3D @@ -1795,8 +1795,8 @@ static void hvf_sync_vtimer(CPUState *cpu) =20 if (!irq_state) { /* Timer no longer asserting, we can unmask it */ - hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false); - cpu->hvf->vtimer_masked =3D false; + hv_vcpu_set_vtimer_mask(cpu->accel->fd, false); + cpu->accel->vtimer_masked =3D false; } } =20 @@ -1805,7 +1805,7 @@ int hvf_vcpu_exec(CPUState *cpu) ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; int ret; - hv_vcpu_exit_t *hvf_exit =3D cpu->hvf->exit; + hv_vcpu_exit_t *hvf_exit =3D cpu->accel->exit; hv_return_t r; bool advance_pc =3D false; =20 @@ -1821,7 +1821,7 @@ int hvf_vcpu_exec(CPUState *cpu) flush_cpu_state(cpu); =20 qemu_mutex_unlock_iothread(); - assert_hvf_ok(hv_vcpu_run(cpu->hvf->fd)); + assert_hvf_ok(hv_vcpu_run(cpu->accel->fd)); =20 /* handle VMEXIT */ uint64_t exit_reason =3D hvf_exit->reason; @@ -1836,7 +1836,7 @@ int hvf_vcpu_exec(CPUState *cpu) break; case HV_EXIT_REASON_VTIMER_ACTIVATED: qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); - cpu->hvf->vtimer_masked =3D true; + cpu->accel->vtimer_masked =3D true; return 0; case HV_EXIT_REASON_CANCELED: /* we got kicked, no exit to process */ @@ -1990,10 +1990,10 @@ int hvf_vcpu_exec(CPUState *cpu) =20 flush_cpu_state(cpu); =20 - r =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_PC, &pc); + r =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_PC, &pc); assert_hvf_ok(r); pc +=3D 4; - r =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_PC, pc); + r =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_PC, pc); assert_hvf_ok(r); =20 /* Handle single-stepping over instructions which trigger a VM exi= t */ @@ -2113,29 +2113,29 @@ static void hvf_put_gdbstub_debug_registers(CPUStat= e *cpu) =20 for (i =3D 0; i < cur_hw_bps; i++) { HWBreakpoint *bp =3D get_hw_bp(i); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbcr_regs[i], bp->bcr); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], bp->bcr); assert_hvf_ok(r); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbvr_regs[i], bp->bvr); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], bp->bvr); assert_hvf_ok(r); } for (i =3D cur_hw_bps; i < max_hw_bps; i++) { - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbcr_regs[i], 0); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], 0); assert_hvf_ok(r); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbvr_regs[i], 0); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], 0); assert_hvf_ok(r); } =20 for (i =3D 0; i < cur_hw_wps; i++) { HWWatchpoint *wp =3D get_hw_wp(i); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwcr_regs[i], wp->wcr); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], wp->wcr); assert_hvf_ok(r); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwvr_regs[i], wp->wvr); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], wp->wvr); assert_hvf_ok(r); } for (i =3D cur_hw_wps; i < max_hw_wps; i++) { - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwcr_regs[i], 0); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], 0); assert_hvf_ok(r); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwvr_regs[i], 0); + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], 0); assert_hvf_ok(r); } } @@ -2152,19 +2152,19 @@ static void hvf_put_guest_debug_registers(CPUState = *cpu) int i; =20 for (i =3D 0; i < max_hw_bps; i++) { - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbcr_regs[i], + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], env->cp15.dbgbcr[i]); assert_hvf_ok(r); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbvr_regs[i], + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], env->cp15.dbgbvr[i]); assert_hvf_ok(r); } =20 for (i =3D 0; i < max_hw_wps; i++) { - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwcr_regs[i], + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], env->cp15.dbgwcr[i]); assert_hvf_ok(r); - r =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwvr_regs[i], + r =3D hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], env->cp15.dbgwvr[i]); assert_hvf_ok(r); } @@ -2184,16 +2184,16 @@ static void hvf_arch_set_traps(void) /* Check whether guest debugging is enabled for at least one vCPU; if = it * is, enable exiting the guest on all vCPUs */ CPU_FOREACH(cpu) { - should_enable_traps |=3D cpu->hvf->guest_debug_enabled; + should_enable_traps |=3D cpu->accel->guest_debug_enabled; } CPU_FOREACH(cpu) { /* Set whether debug exceptions exit the guest */ - r =3D hv_vcpu_set_trap_debug_exceptions(cpu->hvf->fd, + r =3D hv_vcpu_set_trap_debug_exceptions(cpu->accel->fd, should_enable_traps); assert_hvf_ok(r); =20 /* Set whether accesses to debug registers exit the guest */ - r =3D hv_vcpu_set_trap_debug_reg_accesses(cpu->hvf->fd, + r =3D hv_vcpu_set_trap_debug_reg_accesses(cpu->accel->fd, should_enable_traps); assert_hvf_ok(r); } @@ -2205,12 +2205,12 @@ void hvf_arch_update_guest_debug(CPUState *cpu) CPUARMState *env =3D &arm_cpu->env; =20 /* Check whether guest debugging is enabled */ - cpu->hvf->guest_debug_enabled =3D cpu->singlestep_enabled || + cpu->accel->guest_debug_enabled =3D cpu->singlestep_enabled || hvf_sw_breakpoints_active(cpu) || hvf_arm_hw_debug_active(cpu); =20 /* Update debug registers */ - if (cpu->hvf->guest_debug_enabled) { + if (cpu->accel->guest_debug_enabled) { hvf_put_gdbstub_debug_registers(cpu); } else { hvf_put_guest_debug_registers(cpu); diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index f6775c942a..06ea5033c2 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -81,11 +81,11 @@ void vmx_update_tpr(CPUState *cpu) int tpr =3D cpu_get_apic_tpr(x86_cpu->apic_state) << 4; int irr =3D apic_get_highest_priority_irr(x86_cpu->apic_state); =20 - wreg(cpu->hvf->fd, HV_X86_TPR, tpr); + wreg(cpu->accel->fd, HV_X86_TPR, tpr); if (irr =3D=3D -1) { - wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0); + wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0); } else { - wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : + wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : irr >> 4); } } @@ -93,7 +93,7 @@ void vmx_update_tpr(CPUState *cpu) static void update_apic_tpr(CPUState *cpu) { X86CPU *x86_cpu =3D X86_CPU(cpu); - int tpr =3D rreg(cpu->hvf->fd, HV_X86_TPR) >> 4; + int tpr =3D rreg(cpu->accel->fd, HV_X86_TPR) >> 4; cpu_set_apic_tpr(x86_cpu->apic_state, tpr); } =20 @@ -256,12 +256,12 @@ int hvf_arch_init_vcpu(CPUState *cpu) } =20 /* set VMCS control fields */ - wvmcs(cpu->hvf->fd, VMCS_PIN_BASED_CTLS, + wvmcs(cpu->accel->fd, VMCS_PIN_BASED_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased, VMCS_PIN_BASED_CTLS_EXTINT | VMCS_PIN_BASED_CTLS_NMI | VMCS_PIN_BASED_CTLS_VNMI)); - wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, + wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased, VMCS_PRI_PROC_BASED_CTLS_HLT | VMCS_PRI_PROC_BASED_CTLS_MWAIT | @@ -276,14 +276,14 @@ int hvf_arch_init_vcpu(CPUState *cpu) reqCap |=3D VMCS_PRI_PROC_BASED2_CTLS_RDTSCP; } =20 - wvmcs(cpu->hvf->fd, VMCS_SEC_PROC_BASED_CTLS, + wvmcs(cpu->accel->fd, VMCS_SEC_PROC_BASED_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2, reqCap)); =20 - wvmcs(cpu->hvf->fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx= _cap_entry, + wvmcs(cpu->accel->fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->v= mx_cap_entry, 0)); - wvmcs(cpu->hvf->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ + wvmcs(cpu->accel->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ =20 - wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0); + wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0); =20 x86cpu =3D X86_CPU(cpu); x86cpu->env.xsave_buf_len =3D 4096; @@ -295,18 +295,18 @@ int hvf_arch_init_vcpu(CPUState *cpu) */ assert(hvf_get_supported_cpuid(0xd, 0, R_ECX) <=3D x86cpu->env.xsave_b= uf_len); =20 - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_STAR, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_LSTAR, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_CSTAR, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FMASK, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FSBASE, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_GSBASE, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_KERNELGSBASE, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_TSC_AUX, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_TSC, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_CS, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_EIP, 1); - hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_ESP, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_STAR, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_LSTAR, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_CSTAR, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_FMASK, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_FSBASE, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_GSBASE, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_KERNELGSBASE, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_TSC_AUX, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_TSC, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_CS, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_EIP, 1); + hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_ESP, 1); =20 return 0; } @@ -347,16 +347,16 @@ static void hvf_store_events(CPUState *cpu, uint32_t = ins_len, uint64_t idtvec_in } if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) { env->has_error_code =3D true; - env->error_code =3D rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_ERR= OR); + env->error_code =3D rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_E= RROR); } } - if ((rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) & + if ((rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY) & VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) { env->hflags2 |=3D HF2_NMI_MASK; } else { env->hflags2 &=3D ~HF2_NMI_MASK; } - if (rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) & + if (rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY) & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { env->hflags |=3D HF_INHIBIT_IRQ_MASK; @@ -435,20 +435,20 @@ int hvf_vcpu_exec(CPUState *cpu) return EXCP_HLT; } =20 - hv_return_t r =3D hv_vcpu_run(cpu->hvf->fd); + hv_return_t r =3D hv_vcpu_run(cpu->accel->fd); assert_hvf_ok(r); =20 /* handle VMEXIT */ - uint64_t exit_reason =3D rvmcs(cpu->hvf->fd, VMCS_EXIT_REASON); - uint64_t exit_qual =3D rvmcs(cpu->hvf->fd, VMCS_EXIT_QUALIFICATION= ); - uint32_t ins_len =3D (uint32_t)rvmcs(cpu->hvf->fd, + uint64_t exit_reason =3D rvmcs(cpu->accel->fd, VMCS_EXIT_REASON); + uint64_t exit_qual =3D rvmcs(cpu->accel->fd, VMCS_EXIT_QUALIFICATI= ON); + uint32_t ins_len =3D (uint32_t)rvmcs(cpu->accel->fd, VMCS_EXIT_INSTRUCTION_LENGTH); =20 - uint64_t idtvec_info =3D rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_IN= FO); + uint64_t idtvec_info =3D rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_= INFO); =20 hvf_store_events(cpu, ins_len, idtvec_info); - rip =3D rreg(cpu->hvf->fd, HV_X86_RIP); - env->eflags =3D rreg(cpu->hvf->fd, HV_X86_RFLAGS); + rip =3D rreg(cpu->accel->fd, HV_X86_RIP); + env->eflags =3D rreg(cpu->accel->fd, HV_X86_RFLAGS); =20 qemu_mutex_lock_iothread(); =20 @@ -478,7 +478,7 @@ int hvf_vcpu_exec(CPUState *cpu) case EXIT_REASON_EPT_FAULT: { hvf_slot *slot; - uint64_t gpa =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_PHYSICAL_ADDRE= SS); + uint64_t gpa =3D rvmcs(cpu->accel->fd, VMCS_GUEST_PHYSICAL_ADD= RESS); =20 if (((idtvec_info & VMCS_IDT_VEC_VALID) =3D=3D 0) && ((exit_qual & EXIT_QUAL_NMIUDTI) !=3D 0)) { @@ -523,7 +523,7 @@ int hvf_vcpu_exec(CPUState *cpu) store_regs(cpu); break; } else if (!string && !in) { - RAX(env) =3D rreg(cpu->hvf->fd, HV_X86_RAX); + RAX(env) =3D rreg(cpu->accel->fd, HV_X86_RAX); hvf_handle_io(env, port, &RAX(env), 1, size, 1); macvm_set_rip(cpu, rip + ins_len); break; @@ -539,21 +539,21 @@ int hvf_vcpu_exec(CPUState *cpu) break; } case EXIT_REASON_CPUID: { - uint32_t rax =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX); - uint32_t rbx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RBX); - uint32_t rcx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX); - uint32_t rdx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX); + uint32_t rax =3D (uint32_t)rreg(cpu->accel->fd, HV_X86_RAX); + uint32_t rbx =3D (uint32_t)rreg(cpu->accel->fd, HV_X86_RBX); + uint32_t rcx =3D (uint32_t)rreg(cpu->accel->fd, HV_X86_RCX); + uint32_t rdx =3D (uint32_t)rreg(cpu->accel->fd, HV_X86_RDX); =20 if (rax =3D=3D 1) { /* CPUID1.ecx.OSXSAVE needs to know CR4 */ - env->cr[4] =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4); + env->cr[4] =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR4); } hvf_cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx); =20 - wreg(cpu->hvf->fd, HV_X86_RAX, rax); - wreg(cpu->hvf->fd, HV_X86_RBX, rbx); - wreg(cpu->hvf->fd, HV_X86_RCX, rcx); - wreg(cpu->hvf->fd, HV_X86_RDX, rdx); + wreg(cpu->accel->fd, HV_X86_RAX, rax); + wreg(cpu->accel->fd, HV_X86_RBX, rbx); + wreg(cpu->accel->fd, HV_X86_RCX, rcx); + wreg(cpu->accel->fd, HV_X86_RDX, rdx); =20 macvm_set_rip(cpu, rip + ins_len); break; @@ -561,16 +561,16 @@ int hvf_vcpu_exec(CPUState *cpu) case EXIT_REASON_XSETBV: { X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; - uint32_t eax =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX); - uint32_t ecx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX); - uint32_t edx =3D (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX); + uint32_t eax =3D (uint32_t)rreg(cpu->accel->fd, HV_X86_RAX); + uint32_t ecx =3D (uint32_t)rreg(cpu->accel->fd, HV_X86_RCX); + uint32_t edx =3D (uint32_t)rreg(cpu->accel->fd, HV_X86_RDX); =20 if (ecx) { macvm_set_rip(cpu, rip + ins_len); break; } env->xcr0 =3D ((uint64_t)edx << 32) | eax; - wreg(cpu->hvf->fd, HV_X86_XCR0, env->xcr0 | 1); + wreg(cpu->accel->fd, HV_X86_XCR0, env->xcr0 | 1); macvm_set_rip(cpu, rip + ins_len); break; } @@ -609,11 +609,11 @@ int hvf_vcpu_exec(CPUState *cpu) =20 switch (cr) { case 0x0: { - macvm_set_cr0(cpu->hvf->fd, RRX(env, reg)); + macvm_set_cr0(cpu->accel->fd, RRX(env, reg)); break; } case 4: { - macvm_set_cr4(cpu->hvf->fd, RRX(env, reg)); + macvm_set_cr4(cpu->accel->fd, RRX(env, reg)); break; } case 8: { @@ -649,7 +649,7 @@ int hvf_vcpu_exec(CPUState *cpu) break; } case EXIT_REASON_TASK_SWITCH: { - uint64_t vinfo =3D rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO= ); + uint64_t vinfo =3D rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_IN= FO); x68_segment_selector sel =3D {.sel =3D exit_qual & 0xffff}; vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3, vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, = vinfo @@ -662,8 +662,8 @@ int hvf_vcpu_exec(CPUState *cpu) break; } case EXIT_REASON_RDPMC: - wreg(cpu->hvf->fd, HV_X86_RAX, 0); - wreg(cpu->hvf->fd, HV_X86_RDX, 0); + wreg(cpu->accel->fd, HV_X86_RAX, 0); + wreg(cpu->accel->fd, HV_X86_RDX, 0); macvm_set_rip(cpu, rip + ins_len); break; case VMX_REASON_VMCALL: diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c index d086584f26..8ceea6398e 100644 --- a/target/i386/hvf/x86.c +++ b/target/i386/hvf/x86.c @@ -61,11 +61,11 @@ bool x86_read_segment_descriptor(struct CPUState *cpu, } =20 if (GDT_SEL =3D=3D sel.ti) { - base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE); - limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT); + base =3D rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_BASE); + limit =3D rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT); } else { - base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_BASE); - limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_LIMIT); + base =3D rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_BASE); + limit =3D rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_LIMIT); } =20 if (sel.index * 8 >=3D limit) { @@ -84,11 +84,11 @@ bool x86_write_segment_descriptor(struct CPUState *cpu, uint32_t limit; =20 if (GDT_SEL =3D=3D sel.ti) { - base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE); - limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT); + base =3D rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_BASE); + limit =3D rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT); } else { - base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_BASE); - limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_LIMIT); + base =3D rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_BASE); + limit =3D rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_LIMIT); } =20 if (sel.index * 8 >=3D limit) { @@ -102,8 +102,8 @@ bool x86_write_segment_descriptor(struct CPUState *cpu, bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_de= sc, int gate) { - target_ulong base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_BASE); - uint32_t limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_LIMIT); + target_ulong base =3D rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_BASE); + uint32_t limit =3D rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_LIMIT); =20 memset(idt_desc, 0, sizeof(*idt_desc)); if (gate * 8 >=3D limit) { @@ -117,7 +117,7 @@ bool x86_read_call_gate(struct CPUState *cpu, struct x8= 6_call_gate *idt_desc, =20 bool x86_is_protected(struct CPUState *cpu) { - uint64_t cr0 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0); + uint64_t cr0 =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR0); return cr0 & CR0_PE_MASK; } =20 @@ -135,7 +135,7 @@ bool x86_is_v8086(struct CPUState *cpu) =20 bool x86_is_long_mode(struct CPUState *cpu) { - return rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA; + return rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA; } =20 bool x86_is_long64_mode(struct CPUState *cpu) @@ -148,13 +148,13 @@ bool x86_is_long64_mode(struct CPUState *cpu) =20 bool x86_is_paging_mode(struct CPUState *cpu) { - uint64_t cr0 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0); + uint64_t cr0 =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR0); return cr0 & CR0_PG_MASK; } =20 bool x86_is_pae_enabled(struct CPUState *cpu) { - uint64_t cr4 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4); + uint64_t cr4 =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR4); return cr4 & CR4_PAE_MASK; } =20 diff --git a/target/i386/hvf/x86_descr.c b/target/i386/hvf/x86_descr.c index a484942cfc..c2d2e9ee84 100644 --- a/target/i386/hvf/x86_descr.c +++ b/target/i386/hvf/x86_descr.c @@ -47,47 +47,47 @@ static const struct vmx_segment_field { =20 uint32_t vmx_read_segment_limit(CPUState *cpu, X86Seg seg) { - return (uint32_t)rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].limit); + return (uint32_t)rvmcs(cpu->accel->fd, vmx_segment_fields[seg].limit); } =20 uint32_t vmx_read_segment_ar(CPUState *cpu, X86Seg seg) { - return (uint32_t)rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].ar_bytes); + return (uint32_t)rvmcs(cpu->accel->fd, vmx_segment_fields[seg].ar_byte= s); } =20 uint64_t vmx_read_segment_base(CPUState *cpu, X86Seg seg) { - return rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].base); + return rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base); } =20 x68_segment_selector vmx_read_segment_selector(CPUState *cpu, X86Seg seg) { x68_segment_selector sel; - sel.sel =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector); + sel.sel =3D rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector); return sel; } =20 void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector= selector, X86Seg seg) { - wvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector, selector.sel); + wvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector, selector.sel); } =20 void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment = *desc, X86Seg seg) { - desc->sel =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector); - desc->base =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].base); - desc->limit =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].limit); - desc->ar =3D rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].ar_bytes); + desc->sel =3D rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector); + desc->base =3D rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base); + desc->limit =3D rvmcs(cpu->accel->fd, vmx_segment_fields[seg].limit); + desc->ar =3D rvmcs(cpu->accel->fd, vmx_segment_fields[seg].ar_bytes); } =20 void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc,= X86Seg seg) { const struct vmx_segment_field *sf =3D &vmx_segment_fields[seg]; =20 - wvmcs(cpu->hvf->fd, sf->base, desc->base); - wvmcs(cpu->hvf->fd, sf->limit, desc->limit); - wvmcs(cpu->hvf->fd, sf->selector, desc->sel); - wvmcs(cpu->hvf->fd, sf->ar_bytes, desc->ar); + wvmcs(cpu->accel->fd, sf->base, desc->base); + wvmcs(cpu->accel->fd, sf->limit, desc->limit); + wvmcs(cpu->accel->fd, sf->selector, desc->sel); + wvmcs(cpu->accel->fd, sf->ar_bytes, desc->ar); } =20 void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selec= tor selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_= desc) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index f5704f63e8..ccda568478 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -673,7 +673,7 @@ void simulate_rdmsr(struct CPUState *cpu) =20 switch (msr) { case MSR_IA32_TSC: - val =3D rdtscp() + rvmcs(cpu->hvf->fd, VMCS_TSC_OFFSET); + val =3D rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET); break; case MSR_IA32_APICBASE: val =3D cpu_get_apic_base(X86_CPU(cpu)->apic_state); @@ -682,16 +682,16 @@ void simulate_rdmsr(struct CPUState *cpu) val =3D x86_cpu->ucode_rev; break; case MSR_EFER: - val =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER); + val =3D rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER); break; case MSR_FSBASE: - val =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE); + val =3D rvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE); break; case MSR_GSBASE: - val =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE); + val =3D rvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE); break; case MSR_KERNELGSBASE: - val =3D rvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE); + val =3D rvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE); break; case MSR_STAR: abort(); @@ -779,13 +779,13 @@ void simulate_wrmsr(struct CPUState *cpu) cpu_set_apic_base(X86_CPU(cpu)->apic_state, data); break; case MSR_FSBASE: - wvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE, data); + wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data); break; case MSR_GSBASE: - wvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE, data); + wvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE, data); break; case MSR_KERNELGSBASE: - wvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE, data); + wvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE, data); break; case MSR_STAR: abort(); @@ -798,9 +798,9 @@ void simulate_wrmsr(struct CPUState *cpu) break; case MSR_EFER: /*printf("new efer %llx\n", EFER(cpu));*/ - wvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER, data); + wvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER, data); if (data & MSR_EFER_NXE) { - hv_vcpu_invalidate_tlb(cpu->hvf->fd); + hv_vcpu_invalidate_tlb(cpu->accel->fd); } break; case MSR_MTRRphysBase(0): @@ -1424,21 +1424,21 @@ void load_regs(struct CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; =20 int i =3D 0; - RRX(env, R_EAX) =3D rreg(cpu->hvf->fd, HV_X86_RAX); - RRX(env, R_EBX) =3D rreg(cpu->hvf->fd, HV_X86_RBX); - RRX(env, R_ECX) =3D rreg(cpu->hvf->fd, HV_X86_RCX); - RRX(env, R_EDX) =3D rreg(cpu->hvf->fd, HV_X86_RDX); - RRX(env, R_ESI) =3D rreg(cpu->hvf->fd, HV_X86_RSI); - RRX(env, R_EDI) =3D rreg(cpu->hvf->fd, HV_X86_RDI); - RRX(env, R_ESP) =3D rreg(cpu->hvf->fd, HV_X86_RSP); - RRX(env, R_EBP) =3D rreg(cpu->hvf->fd, HV_X86_RBP); + RRX(env, R_EAX) =3D rreg(cpu->accel->fd, HV_X86_RAX); + RRX(env, R_EBX) =3D rreg(cpu->accel->fd, HV_X86_RBX); + RRX(env, R_ECX) =3D rreg(cpu->accel->fd, HV_X86_RCX); + RRX(env, R_EDX) =3D rreg(cpu->accel->fd, HV_X86_RDX); + RRX(env, R_ESI) =3D rreg(cpu->accel->fd, HV_X86_RSI); + RRX(env, R_EDI) =3D rreg(cpu->accel->fd, HV_X86_RDI); + RRX(env, R_ESP) =3D rreg(cpu->accel->fd, HV_X86_RSP); + RRX(env, R_EBP) =3D rreg(cpu->accel->fd, HV_X86_RBP); for (i =3D 8; i < 16; i++) { - RRX(env, i) =3D rreg(cpu->hvf->fd, HV_X86_RAX + i); + RRX(env, i) =3D rreg(cpu->accel->fd, HV_X86_RAX + i); } =20 - env->eflags =3D rreg(cpu->hvf->fd, HV_X86_RFLAGS); + env->eflags =3D rreg(cpu->accel->fd, HV_X86_RFLAGS); rflags_to_lflags(env); - env->eip =3D rreg(cpu->hvf->fd, HV_X86_RIP); + env->eip =3D rreg(cpu->accel->fd, HV_X86_RIP); } =20 void store_regs(struct CPUState *cpu) @@ -1447,20 +1447,20 @@ void store_regs(struct CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; =20 int i =3D 0; - wreg(cpu->hvf->fd, HV_X86_RAX, RAX(env)); - wreg(cpu->hvf->fd, HV_X86_RBX, RBX(env)); - wreg(cpu->hvf->fd, HV_X86_RCX, RCX(env)); - wreg(cpu->hvf->fd, HV_X86_RDX, RDX(env)); - wreg(cpu->hvf->fd, HV_X86_RSI, RSI(env)); - wreg(cpu->hvf->fd, HV_X86_RDI, RDI(env)); - wreg(cpu->hvf->fd, HV_X86_RBP, RBP(env)); - wreg(cpu->hvf->fd, HV_X86_RSP, RSP(env)); + wreg(cpu->accel->fd, HV_X86_RAX, RAX(env)); + wreg(cpu->accel->fd, HV_X86_RBX, RBX(env)); + wreg(cpu->accel->fd, HV_X86_RCX, RCX(env)); + wreg(cpu->accel->fd, HV_X86_RDX, RDX(env)); + wreg(cpu->accel->fd, HV_X86_RSI, RSI(env)); + wreg(cpu->accel->fd, HV_X86_RDI, RDI(env)); + wreg(cpu->accel->fd, HV_X86_RBP, RBP(env)); + wreg(cpu->accel->fd, HV_X86_RSP, RSP(env)); for (i =3D 8; i < 16; i++) { - wreg(cpu->hvf->fd, HV_X86_RAX + i, RRX(env, i)); + wreg(cpu->accel->fd, HV_X86_RAX + i, RRX(env, i)); } =20 lflags_to_rflags(env); - wreg(cpu->hvf->fd, HV_X86_RFLAGS, env->eflags); + wreg(cpu->accel->fd, HV_X86_RFLAGS, env->eflags); macvm_set_rip(cpu, env->eip); } =20 diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c index 96d117567e..8cd08622a1 100644 --- a/target/i386/hvf/x86_mmu.c +++ b/target/i386/hvf/x86_mmu.c @@ -126,7 +126,7 @@ static bool test_pt_entry(struct CPUState *cpu, struct = gpt_translation *pt, pt->err_code |=3D MMU_PAGE_PT; } =20 - uint32_t cr0 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0); + uint32_t cr0 =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR0); /* check protection */ if (cr0 & CR0_WP_MASK) { if (pt->write_access && !pte_write_access(pte)) { @@ -171,7 +171,7 @@ static bool walk_gpt(struct CPUState *cpu, target_ulong= addr, int err_code, { int top_level, level; bool is_large =3D false; - target_ulong cr3 =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR3); + target_ulong cr3 =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR3); uint64_t page_mask =3D pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK; =20 memset(pt, 0, sizeof(*pt)); diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c index beaeec0687..f09bfbdda5 100644 --- a/target/i386/hvf/x86_task.c +++ b/target/i386/hvf/x86_task.c @@ -61,7 +61,7 @@ static void load_state_from_tss32(CPUState *cpu, struct x= 86_tss_segment32 *tss) X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; =20 - wvmcs(cpu->hvf->fd, VMCS_GUEST_CR3, tss->cr3); + wvmcs(cpu->accel->fd, VMCS_GUEST_CR3, tss->cr3); =20 env->eip =3D tss->eip; env->eflags =3D tss->eflags | 2; @@ -110,11 +110,11 @@ static int task_switch_32(CPUState *cpu, x68_segment_= selector tss_sel, x68_segme =20 void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, i= nt reason, bool gate_valid, uint8_t gate, uint64_t gate_type) { - uint64_t rip =3D rreg(cpu->hvf->fd, HV_X86_RIP); + uint64_t rip =3D rreg(cpu->accel->fd, HV_X86_RIP); if (!gate_valid || (gate_type !=3D VMCS_INTR_T_HWEXCEPTION && gate_type !=3D VMCS_INTR_T_HWINTR && gate_type !=3D VMCS_INTR_T_NMI)) { - int ins_len =3D rvmcs(cpu->hvf->fd, VMCS_EXIT_INSTRUCTION_LENGTH); + int ins_len =3D rvmcs(cpu->accel->fd, VMCS_EXIT_INSTRUCTION_LENGTH= ); macvm_set_rip(cpu, rip + ins_len); return; } @@ -173,12 +173,12 @@ void vmx_handle_task_switch(CPUState *cpu, x68_segmen= t_selector tss_sel, int rea //ret =3D task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, = &next_tss_desc); VM_PANIC("task_switch_16"); =20 - macvm_set_cr0(cpu->hvf->fd, rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0) | + macvm_set_cr0(cpu->accel->fd, rvmcs(cpu->accel->fd, VMCS_GUEST_CR0) | CR0_TS_MASK); x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg); vmx_write_segment_descriptor(cpu, &vmx_seg, R_TR); =20 store_regs(cpu); =20 - hv_vcpu_invalidate_tlb(cpu->hvf->fd); + hv_vcpu_invalidate_tlb(cpu->accel->fd); } diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index dfa500b81d..852e3bbf71 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -77,7 +77,7 @@ void hvf_put_xsave(CPUState *cpu) =20 x86_cpu_xsave_all_areas(X86_CPU(cpu), xsave, xsave_len); =20 - if (hv_vcpu_write_fpstate(cpu->hvf->fd, xsave, xsave_len)) { + if (hv_vcpu_write_fpstate(cpu->accel->fd, xsave, xsave_len)) { abort(); } } @@ -87,19 +87,19 @@ static void hvf_put_segments(CPUState *cpu) CPUX86State *env =3D &X86_CPU(cpu)->env; struct vmx_segment seg; =20 - wvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); - wvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_BASE, env->idt.base); + wvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); + wvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_BASE, env->idt.base); =20 - wvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); - wvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); + wvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); + wvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); =20 - /* wvmcs(cpu->hvf->fd, VMCS_GUEST_CR2, env->cr[2]); */ - wvmcs(cpu->hvf->fd, VMCS_GUEST_CR3, env->cr[3]); + /* wvmcs(cpu->accel->fd, VMCS_GUEST_CR2, env->cr[2]); */ + wvmcs(cpu->accel->fd, VMCS_GUEST_CR3, env->cr[3]); vmx_update_tpr(cpu); - wvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER, env->efer); + wvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER, env->efer); =20 - macvm_set_cr4(cpu->hvf->fd, env->cr[4]); - macvm_set_cr0(cpu->hvf->fd, env->cr[0]); + macvm_set_cr4(cpu->accel->fd, env->cr[4]); + macvm_set_cr0(cpu->accel->fd, env->cr[0]); =20 hvf_set_segment(cpu, &seg, &env->segs[R_CS], false); vmx_write_segment_descriptor(cpu, &seg, R_CS); @@ -130,24 +130,24 @@ void hvf_put_msrs(CPUState *cpu) { CPUX86State *env =3D &X86_CPU(cpu)->env; =20 - hv_vcpu_write_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_CS, + hv_vcpu_write_msr(cpu->accel->fd, MSR_IA32_SYSENTER_CS, env->sysenter_cs); - hv_vcpu_write_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_ESP, + hv_vcpu_write_msr(cpu->accel->fd, MSR_IA32_SYSENTER_ESP, env->sysenter_esp); - hv_vcpu_write_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_EIP, + hv_vcpu_write_msr(cpu->accel->fd, MSR_IA32_SYSENTER_EIP, env->sysenter_eip); =20 - hv_vcpu_write_msr(cpu->hvf->fd, MSR_STAR, env->star); + hv_vcpu_write_msr(cpu->accel->fd, MSR_STAR, env->star); =20 #ifdef TARGET_X86_64 - hv_vcpu_write_msr(cpu->hvf->fd, MSR_CSTAR, env->cstar); - hv_vcpu_write_msr(cpu->hvf->fd, MSR_KERNELGSBASE, env->kernelgsbase); - hv_vcpu_write_msr(cpu->hvf->fd, MSR_FMASK, env->fmask); - hv_vcpu_write_msr(cpu->hvf->fd, MSR_LSTAR, env->lstar); + hv_vcpu_write_msr(cpu->accel->fd, MSR_CSTAR, env->cstar); + hv_vcpu_write_msr(cpu->accel->fd, MSR_KERNELGSBASE, env->kernelgsbase); + hv_vcpu_write_msr(cpu->accel->fd, MSR_FMASK, env->fmask); + hv_vcpu_write_msr(cpu->accel->fd, MSR_LSTAR, env->lstar); #endif =20 - hv_vcpu_write_msr(cpu->hvf->fd, MSR_GSBASE, env->segs[R_GS].base); - hv_vcpu_write_msr(cpu->hvf->fd, MSR_FSBASE, env->segs[R_FS].base); + hv_vcpu_write_msr(cpu->accel->fd, MSR_GSBASE, env->segs[R_GS].base); + hv_vcpu_write_msr(cpu->accel->fd, MSR_FSBASE, env->segs[R_FS].base); } =20 =20 @@ -156,7 +156,7 @@ void hvf_get_xsave(CPUState *cpu) void *xsave =3D X86_CPU(cpu)->env.xsave_buf; uint32_t xsave_len =3D X86_CPU(cpu)->env.xsave_buf_len; =20 - if (hv_vcpu_read_fpstate(cpu->hvf->fd, xsave, xsave_len)) { + if (hv_vcpu_read_fpstate(cpu->accel->fd, xsave, xsave_len)) { abort(); } =20 @@ -195,17 +195,17 @@ static void hvf_get_segments(CPUState *cpu) vmx_read_segment_descriptor(cpu, &seg, R_LDTR); hvf_get_segment(&env->ldt, &seg); =20 - env->idt.limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_LIMIT); - env->idt.base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_BASE); - env->gdt.limit =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT); - env->gdt.base =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE); + env->idt.limit =3D rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_LIMIT); + env->idt.base =3D rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_BASE); + env->gdt.limit =3D rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT); + env->gdt.base =3D rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_BASE); =20 - env->cr[0] =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0); + env->cr[0] =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR0); env->cr[2] =3D 0; - env->cr[3] =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR3); - env->cr[4] =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4); + env->cr[3] =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR3); + env->cr[4] =3D rvmcs(cpu->accel->fd, VMCS_GUEST_CR4); =20 - env->efer =3D rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER); + env->efer =3D rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER); } =20 void hvf_get_msrs(CPUState *cpu) @@ -213,27 +213,27 @@ void hvf_get_msrs(CPUState *cpu) CPUX86State *env =3D &X86_CPU(cpu)->env; uint64_t tmp; =20 - hv_vcpu_read_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_CS, &tmp); + hv_vcpu_read_msr(cpu->accel->fd, MSR_IA32_SYSENTER_CS, &tmp); env->sysenter_cs =3D tmp; =20 - hv_vcpu_read_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_ESP, &tmp); + hv_vcpu_read_msr(cpu->accel->fd, MSR_IA32_SYSENTER_ESP, &tmp); env->sysenter_esp =3D tmp; =20 - hv_vcpu_read_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_EIP, &tmp); + hv_vcpu_read_msr(cpu->accel->fd, MSR_IA32_SYSENTER_EIP, &tmp); env->sysenter_eip =3D tmp; =20 - hv_vcpu_read_msr(cpu->hvf->fd, MSR_STAR, &env->star); + hv_vcpu_read_msr(cpu->accel->fd, MSR_STAR, &env->star); =20 #ifdef TARGET_X86_64 - hv_vcpu_read_msr(cpu->hvf->fd, MSR_CSTAR, &env->cstar); - hv_vcpu_read_msr(cpu->hvf->fd, MSR_KERNELGSBASE, &env->kernelgsbase); - hv_vcpu_read_msr(cpu->hvf->fd, MSR_FMASK, &env->fmask); - hv_vcpu_read_msr(cpu->hvf->fd, MSR_LSTAR, &env->lstar); + hv_vcpu_read_msr(cpu->accel->fd, MSR_CSTAR, &env->cstar); + hv_vcpu_read_msr(cpu->accel->fd, MSR_KERNELGSBASE, &env->kernelgsbase); + hv_vcpu_read_msr(cpu->accel->fd, MSR_FMASK, &env->fmask); + hv_vcpu_read_msr(cpu->accel->fd, MSR_LSTAR, &env->lstar); #endif =20 - hv_vcpu_read_msr(cpu->hvf->fd, MSR_IA32_APICBASE, &tmp); + hv_vcpu_read_msr(cpu->accel->fd, MSR_IA32_APICBASE, &tmp); =20 - env->tsc =3D rdtscp() + rvmcs(cpu->hvf->fd, VMCS_TSC_OFFSET); + env->tsc =3D rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET); } =20 int hvf_put_registers(CPUState *cpu) @@ -241,26 +241,26 @@ int hvf_put_registers(CPUState *cpu) X86CPU *x86cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86cpu->env; =20 - wreg(cpu->hvf->fd, HV_X86_RAX, env->regs[R_EAX]); - wreg(cpu->hvf->fd, HV_X86_RBX, env->regs[R_EBX]); - wreg(cpu->hvf->fd, HV_X86_RCX, env->regs[R_ECX]); - wreg(cpu->hvf->fd, HV_X86_RDX, env->regs[R_EDX]); - wreg(cpu->hvf->fd, HV_X86_RBP, env->regs[R_EBP]); - wreg(cpu->hvf->fd, HV_X86_RSP, env->regs[R_ESP]); - wreg(cpu->hvf->fd, HV_X86_RSI, env->regs[R_ESI]); - wreg(cpu->hvf->fd, HV_X86_RDI, env->regs[R_EDI]); - wreg(cpu->hvf->fd, HV_X86_R8, env->regs[8]); - wreg(cpu->hvf->fd, HV_X86_R9, env->regs[9]); - wreg(cpu->hvf->fd, HV_X86_R10, env->regs[10]); - wreg(cpu->hvf->fd, HV_X86_R11, env->regs[11]); - wreg(cpu->hvf->fd, HV_X86_R12, env->regs[12]); - wreg(cpu->hvf->fd, HV_X86_R13, env->regs[13]); - wreg(cpu->hvf->fd, HV_X86_R14, env->regs[14]); - wreg(cpu->hvf->fd, HV_X86_R15, env->regs[15]); - wreg(cpu->hvf->fd, HV_X86_RFLAGS, env->eflags); - wreg(cpu->hvf->fd, HV_X86_RIP, env->eip); + wreg(cpu->accel->fd, HV_X86_RAX, env->regs[R_EAX]); + wreg(cpu->accel->fd, HV_X86_RBX, env->regs[R_EBX]); + wreg(cpu->accel->fd, HV_X86_RCX, env->regs[R_ECX]); + wreg(cpu->accel->fd, HV_X86_RDX, env->regs[R_EDX]); + wreg(cpu->accel->fd, HV_X86_RBP, env->regs[R_EBP]); + wreg(cpu->accel->fd, HV_X86_RSP, env->regs[R_ESP]); + wreg(cpu->accel->fd, HV_X86_RSI, env->regs[R_ESI]); + wreg(cpu->accel->fd, HV_X86_RDI, env->regs[R_EDI]); + wreg(cpu->accel->fd, HV_X86_R8, env->regs[8]); + wreg(cpu->accel->fd, HV_X86_R9, env->regs[9]); + wreg(cpu->accel->fd, HV_X86_R10, env->regs[10]); + wreg(cpu->accel->fd, HV_X86_R11, env->regs[11]); + wreg(cpu->accel->fd, HV_X86_R12, env->regs[12]); + wreg(cpu->accel->fd, HV_X86_R13, env->regs[13]); + wreg(cpu->accel->fd, HV_X86_R14, env->regs[14]); + wreg(cpu->accel->fd, HV_X86_R15, env->regs[15]); + wreg(cpu->accel->fd, HV_X86_RFLAGS, env->eflags); + wreg(cpu->accel->fd, HV_X86_RIP, env->eip); =20 - wreg(cpu->hvf->fd, HV_X86_XCR0, env->xcr0); + wreg(cpu->accel->fd, HV_X86_XCR0, env->xcr0); =20 hvf_put_xsave(cpu); =20 @@ -268,14 +268,14 @@ int hvf_put_registers(CPUState *cpu) =20 hvf_put_msrs(cpu); =20 - wreg(cpu->hvf->fd, HV_X86_DR0, env->dr[0]); - wreg(cpu->hvf->fd, HV_X86_DR1, env->dr[1]); - wreg(cpu->hvf->fd, HV_X86_DR2, env->dr[2]); - wreg(cpu->hvf->fd, HV_X86_DR3, env->dr[3]); - wreg(cpu->hvf->fd, HV_X86_DR4, env->dr[4]); - wreg(cpu->hvf->fd, HV_X86_DR5, env->dr[5]); - wreg(cpu->hvf->fd, HV_X86_DR6, env->dr[6]); - wreg(cpu->hvf->fd, HV_X86_DR7, env->dr[7]); + wreg(cpu->accel->fd, HV_X86_DR0, env->dr[0]); + wreg(cpu->accel->fd, HV_X86_DR1, env->dr[1]); + wreg(cpu->accel->fd, HV_X86_DR2, env->dr[2]); + wreg(cpu->accel->fd, HV_X86_DR3, env->dr[3]); + wreg(cpu->accel->fd, HV_X86_DR4, env->dr[4]); + wreg(cpu->accel->fd, HV_X86_DR5, env->dr[5]); + wreg(cpu->accel->fd, HV_X86_DR6, env->dr[6]); + wreg(cpu->accel->fd, HV_X86_DR7, env->dr[7]); =20 return 0; } @@ -285,40 +285,40 @@ int hvf_get_registers(CPUState *cpu) X86CPU *x86cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86cpu->env; =20 - env->regs[R_EAX] =3D rreg(cpu->hvf->fd, HV_X86_RAX); - env->regs[R_EBX] =3D rreg(cpu->hvf->fd, HV_X86_RBX); - env->regs[R_ECX] =3D rreg(cpu->hvf->fd, HV_X86_RCX); - env->regs[R_EDX] =3D rreg(cpu->hvf->fd, HV_X86_RDX); - env->regs[R_EBP] =3D rreg(cpu->hvf->fd, HV_X86_RBP); - env->regs[R_ESP] =3D rreg(cpu->hvf->fd, HV_X86_RSP); - env->regs[R_ESI] =3D rreg(cpu->hvf->fd, HV_X86_RSI); - env->regs[R_EDI] =3D rreg(cpu->hvf->fd, HV_X86_RDI); - env->regs[8] =3D rreg(cpu->hvf->fd, HV_X86_R8); - env->regs[9] =3D rreg(cpu->hvf->fd, HV_X86_R9); - env->regs[10] =3D rreg(cpu->hvf->fd, HV_X86_R10); - env->regs[11] =3D rreg(cpu->hvf->fd, HV_X86_R11); - env->regs[12] =3D rreg(cpu->hvf->fd, HV_X86_R12); - env->regs[13] =3D rreg(cpu->hvf->fd, HV_X86_R13); - env->regs[14] =3D rreg(cpu->hvf->fd, HV_X86_R14); - env->regs[15] =3D rreg(cpu->hvf->fd, HV_X86_R15); + env->regs[R_EAX] =3D rreg(cpu->accel->fd, HV_X86_RAX); + env->regs[R_EBX] =3D rreg(cpu->accel->fd, HV_X86_RBX); + env->regs[R_ECX] =3D rreg(cpu->accel->fd, HV_X86_RCX); + env->regs[R_EDX] =3D rreg(cpu->accel->fd, HV_X86_RDX); + env->regs[R_EBP] =3D rreg(cpu->accel->fd, HV_X86_RBP); + env->regs[R_ESP] =3D rreg(cpu->accel->fd, HV_X86_RSP); + env->regs[R_ESI] =3D rreg(cpu->accel->fd, HV_X86_RSI); + env->regs[R_EDI] =3D rreg(cpu->accel->fd, HV_X86_RDI); + env->regs[8] =3D rreg(cpu->accel->fd, HV_X86_R8); + env->regs[9] =3D rreg(cpu->accel->fd, HV_X86_R9); + env->regs[10] =3D rreg(cpu->accel->fd, HV_X86_R10); + env->regs[11] =3D rreg(cpu->accel->fd, HV_X86_R11); + env->regs[12] =3D rreg(cpu->accel->fd, HV_X86_R12); + env->regs[13] =3D rreg(cpu->accel->fd, HV_X86_R13); + env->regs[14] =3D rreg(cpu->accel->fd, HV_X86_R14); + env->regs[15] =3D rreg(cpu->accel->fd, HV_X86_R15); =20 - env->eflags =3D rreg(cpu->hvf->fd, HV_X86_RFLAGS); - env->eip =3D rreg(cpu->hvf->fd, HV_X86_RIP); + env->eflags =3D rreg(cpu->accel->fd, HV_X86_RFLAGS); + env->eip =3D rreg(cpu->accel->fd, HV_X86_RIP); =20 hvf_get_xsave(cpu); - env->xcr0 =3D rreg(cpu->hvf->fd, HV_X86_XCR0); + env->xcr0 =3D rreg(cpu->accel->fd, HV_X86_XCR0); =20 hvf_get_segments(cpu); hvf_get_msrs(cpu); =20 - env->dr[0] =3D rreg(cpu->hvf->fd, HV_X86_DR0); - env->dr[1] =3D rreg(cpu->hvf->fd, HV_X86_DR1); - env->dr[2] =3D rreg(cpu->hvf->fd, HV_X86_DR2); - env->dr[3] =3D rreg(cpu->hvf->fd, HV_X86_DR3); - env->dr[4] =3D rreg(cpu->hvf->fd, HV_X86_DR4); - env->dr[5] =3D rreg(cpu->hvf->fd, HV_X86_DR5); - env->dr[6] =3D rreg(cpu->hvf->fd, HV_X86_DR6); - env->dr[7] =3D rreg(cpu->hvf->fd, HV_X86_DR7); + env->dr[0] =3D rreg(cpu->accel->fd, HV_X86_DR0); + env->dr[1] =3D rreg(cpu->accel->fd, HV_X86_DR1); + env->dr[2] =3D rreg(cpu->accel->fd, HV_X86_DR2); + env->dr[3] =3D rreg(cpu->accel->fd, HV_X86_DR3); + env->dr[4] =3D rreg(cpu->accel->fd, HV_X86_DR4); + env->dr[5] =3D rreg(cpu->accel->fd, HV_X86_DR5); + env->dr[6] =3D rreg(cpu->accel->fd, HV_X86_DR6); + env->dr[7] =3D rreg(cpu->accel->fd, HV_X86_DR7); =20 x86_update_hflags(env); return 0; @@ -327,16 +327,16 @@ int hvf_get_registers(CPUState *cpu) static void vmx_set_int_window_exiting(CPUState *cpu) { uint64_t val; - val =3D rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val | + val =3D rvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); } =20 void vmx_clear_int_window_exiting(CPUState *cpu) { uint64_t val; - val =3D rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS); - wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val & + val =3D rvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS); + wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING); } =20 @@ -372,7 +372,7 @@ bool hvf_inject_interrupts(CPUState *cpu) uint64_t info =3D 0; if (have_event) { info =3D vector | intr_type | VMCS_INTR_VALID; - uint64_t reason =3D rvmcs(cpu->hvf->fd, VMCS_EXIT_REASON); + uint64_t reason =3D rvmcs(cpu->accel->fd, VMCS_EXIT_REASON); if (env->nmi_injected && reason !=3D EXIT_REASON_TASK_SWITCH) { vmx_clear_nmi_blocking(cpu); } @@ -381,17 +381,17 @@ bool hvf_inject_interrupts(CPUState *cpu) info &=3D ~(1 << 12); /* clear undefined bit */ if (intr_type =3D=3D VMCS_INTR_T_SWINTR || intr_type =3D=3D VMCS_INTR_T_SWEXCEPTION) { - wvmcs(cpu->hvf->fd, VMCS_ENTRY_INST_LENGTH, env->ins_len); + wvmcs(cpu->accel->fd, VMCS_ENTRY_INST_LENGTH, env->ins_len= ); } =20 if (env->has_error_code) { - wvmcs(cpu->hvf->fd, VMCS_ENTRY_EXCEPTION_ERROR, + wvmcs(cpu->accel->fd, VMCS_ENTRY_EXCEPTION_ERROR, env->error_code); /* Indicate that VMCS_ENTRY_EXCEPTION_ERROR is valid */ info |=3D VMCS_INTR_DEL_ERRCODE; } /*printf("reinject %lx err %d\n", info, err);*/ - wvmcs(cpu->hvf->fd, VMCS_ENTRY_INTR_INFO, info); + wvmcs(cpu->accel->fd, VMCS_ENTRY_INTR_INFO, info); }; } =20 @@ -399,7 +399,7 @@ bool hvf_inject_interrupts(CPUState *cpu) if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_NMI; info =3D VMCS_INTR_VALID | VMCS_INTR_T_NMI | EXCP02_NMI; - wvmcs(cpu->hvf->fd, VMCS_ENTRY_INTR_INFO, info); + wvmcs(cpu->accel->fd, VMCS_ENTRY_INTR_INFO, info); } else { vmx_set_nmi_window_exiting(cpu); } @@ -411,7 +411,7 @@ bool hvf_inject_interrupts(CPUState *cpu) int line =3D cpu_get_pic_interrupt(&x86cpu->env); cpu->interrupt_request &=3D ~CPU_INTERRUPT_HARD; if (line >=3D 0) { - wvmcs(cpu->hvf->fd, VMCS_ENTRY_INTR_INFO, line | + wvmcs(cpu->accel->fd, VMCS_ENTRY_INTR_INFO, line | VMCS_INTR_VALID | VMCS_INTR_T_HWINTR); } } @@ -429,7 +429,7 @@ int hvf_process_events(CPUState *cpu) =20 if (!cpu->vcpu_dirty) { /* light weight sync for CPU_INTERRUPT_HARD and IF_MASK */ - env->eflags =3D rreg(cpu->hvf->fd, HV_X86_RFLAGS); + env->eflags =3D rreg(cpu->accel->fd, HV_X86_RFLAGS); } =20 if (cpu->interrupt_request & CPU_INTERRUPT_INIT) { --=20 2.38.1