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bh=SCI9MwarsbRlj2FJ9hBho2GnuBuTU9RG25ioTaHG3ao=; b=HnOMR4yPVJKKaKpTYp8eaUCROER4ZnkkiXd1ElazADmvP6lHUTnIp0S+lwj9ls4pujd6tgemDNxdkU3cbJAgGyvGYJga62wnUJfpYF+dw+XPkPUO6Epi73gqUtmmH8FLqdNrYD530nQmEV/2uNBTtigqwHsLVndXav36zmdS6dM= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 3/4] xen/arm: pl011: Use correct accessors Date: Wed, 7 Jun 2023 11:27:26 +0200 Message-ID: <20230607092727.19654-4-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607092727.19654-1-michal.orzel@amd.com> References: <20230607092727.19654-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT020:EE_|SA1PR12MB8597:EE_ X-MS-Office365-Filtering-Correlation-Id: b9949e3a-1cb8-468d-c34f-08db6739780e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2023 09:27:52.7618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9949e3a-1cb8-468d-c34f-08db6739780e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8597 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1686130107520100001 Content-Type: text/plain; charset="utf-8" At the moment, we use 32-bit only accessors (i.e. readl/writel) to match the SBSA v2.x requirement. This should not be the default case for normal PL011 where accesses shall be 8/16-bit (max register size is 16-bit). There are however implementations of this UART that can only handle 32-bit MMIO. This is advertised by dt property "reg-io-width" set to 4. Introduce new struct pl011 member mmio32 and replace pl011_{read/write} macros with static inline helpers that use 32-bit or 16-bit accessors (largest-common not to end up using different ones depending on the actual register size) according to mmio32 value. By default this property is set to false, unless: - reg-io-width is specified with value 4, - SBSA UART is in use. For now, no changes done for ACPI due to lack of testing possibilities (i.e. current behavior maintained resulting in 32-bit accesses). Signed-off-by: Michal Orzel Reviewed-by: Stefano Stabellini Tested-by: Henry Wang --- xen/drivers/char/pl011.c | 53 +++++++++++++++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 6 deletions(-) diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index 052a6512515c..403b1ac06551 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -41,6 +41,7 @@ static struct pl011 { /* unsigned int timeout_ms; */ /* bool_t probing, intr_works; */ bool sbsa; /* ARM SBSA generic interface */ + bool mmio32; /* 32-bit only MMIO */ } pl011_com =3D {0}; =20 /* These parity settings can be ORed directly into the LCR. */ @@ -50,9 +51,30 @@ static struct pl011 { #define PARITY_MARK (PEN|SPS) #define PARITY_SPACE (PEN|EPS|SPS) =20 -/* SBSA v2.x document requires, all reads/writes must be 32-bit accesses */ -#define pl011_read(uart, off) readl((uart)->regs + (off)) -#define pl011_write(uart, off,val) writel((val), (uart)->regs + (off)) +/* + * By default, PL011 accesses shall be done using 8/16-bit accessors to + * support legacy devices that cannot cope with 32-bit. On the other hand, + * there are implementations of PL011 that can only handle 32-bit MMIO. Al= so, + * SBSA v2.x requires 32-bit accesses. Note that for default case, we use + * largest-common accessors (i.e. 16-bit) not to end up using different on= es + * depending on the actual register size. + */ +static inline void +pl011_write(struct pl011 *uart, unsigned int offset, unsigned int val) +{ + if ( uart->mmio32 ) + writel(val, uart->regs + offset); + else + writew(val, uart->regs + offset); +} + +static inline unsigned int pl011_read(struct pl011 *uart, unsigned int off= set) +{ + if ( uart->mmio32 ) + return readl(uart->regs + offset); + + return readw(uart->regs + offset); +} =20 static unsigned int pl011_intr_status(struct pl011 *uart) { @@ -222,7 +244,8 @@ static struct uart_driver __read_mostly pl011_driver = =3D { .vuart_info =3D pl011_vuart, }; =20 -static int __init pl011_uart_init(int irq, paddr_t addr, paddr_t size, boo= l sbsa) +static int __init +pl011_uart_init(int irq, paddr_t addr, paddr_t size, bool sbsa, bool mmio3= 2) { struct pl011 *uart; =20 @@ -233,6 +256,9 @@ static int __init pl011_uart_init(int irq, paddr_t addr= , paddr_t size, bool sbsa uart->stop_bits =3D 1; uart->sbsa =3D sbsa; =20 + /* Set 32-bit MMIO also for SBSA since v2.x requires it */ + uart->mmio32 =3D (mmio32 || sbsa); + uart->regs =3D ioremap_nocache(addr, size); if ( !uart->regs ) { @@ -259,6 +285,8 @@ static int __init pl011_dt_uart_init(struct dt_device_n= ode *dev, const char *config =3D data; int res; paddr_t addr, size; + uint32_t io_width; + bool mmio32 =3D false; =20 if ( strcmp(config, "") ) { @@ -280,7 +308,19 @@ static int __init pl011_dt_uart_init(struct dt_device_= node *dev, return -EINVAL; } =20 - res =3D pl011_uart_init(res, addr, size, false); + /* See linux Documentation/devicetree/bindings/serial/pl011.yaml */ + if ( dt_property_read_u32(dev, "reg-io-width", &io_width) ) + { + if ( io_width =3D=3D 4 ) + mmio32 =3D true; + else if ( io_width !=3D 1 ) + { + printk("pl011: Unsupported reg-io-width (%"PRIu32")\n", io_wid= th); + return -EINVAL; + } + } + + res =3D pl011_uart_init(res, addr, size, false, mmio32); if ( res < 0 ) { printk("pl011: Unable to initialize\n"); @@ -328,8 +368,9 @@ static int __init pl011_acpi_uart_init(const void *data) /* trigger/polarity information is not available in spcr */ irq_set_type(spcr->interrupt, IRQ_TYPE_LEVEL_HIGH); =20 + /* TODO - mmio32 proper handling (for now set to true) */ res =3D pl011_uart_init(spcr->interrupt, spcr->serial_port.address, - PAGE_SIZE, sbsa); + PAGE_SIZE, sbsa, true); if ( res < 0 ) { printk("pl011: Unable to initialize\n"); --=20 2.25.1