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bh=R98uFfHZVa1myY/azuIH4bMaUuCmPRTnAIKrAgYKBu4=; b=QCTzPS+ZsgDM3eYLpD4EG+LBHsmmVQNCHkFc1axLasf1uVcWolwlPTjufMSVxMXoe/himnjhFMMrVTHgddQSXI8ZebLfIioh9X5CEYaS3hPA0wgG93pdtgKUJyu/VsCcyYifGpc3hppAGdbhEaMuN8QJ0DuCb+bJIrJuc9YM51g= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 1/4] xen/arm: debug-pl011: Use correct accessors Date: Wed, 7 Jun 2023 11:27:24 +0200 Message-ID: <20230607092727.19654-2-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607092727.19654-1-michal.orzel@amd.com> References: <20230607092727.19654-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT022:EE_|SA1PR12MB8095:EE_ X-MS-Office365-Filtering-Correlation-Id: e18bc765-03f6-46c2-c383-08db67397560 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2023 09:27:48.2661 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e18bc765-03f6-46c2-c383-08db67397560 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8095 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1686130100158100003 Content-Type: text/plain; charset="utf-8" Although most PL011 UARTs can cope with 32-bit accesses, some of the old legacy ones might not. PL011 registers are 8/16-bit wide and this shall be perceived as the normal behavior. Modify early printk pl011 code for arm32/arm64 to use the correct accessors depending on the register size (refer ARM DDI 0183G, Table 3.1). Signed-off-by: Michal Orzel Reviewed-by: Stefano Stabellini Tested-by: Henry Wang --- Next patch will override strX,ldrX with macros but I prefer to keep the history clean (+ possibiltity for a backport if needed). --- xen/arch/arm/arm32/debug-pl011.inc | 12 ++++++------ xen/arch/arm/arm64/debug-pl011.inc | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/arm32/debug-pl011.inc b/xen/arch/arm/arm32/debug-= pl011.inc index c527f1d4424d..9fe0c2503831 100644 --- a/xen/arch/arm/arm32/debug-pl011.inc +++ b/xen/arch/arm/arm32/debug-pl011.inc @@ -26,13 +26,13 @@ */ .macro early_uart_init rb, rc, rd mov \rc, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE % 16) - str \rc, [\rb, #FBRD] /* -> UARTFBRD (Baud divisor fraction)= */ + strb \rc, [\rb, #FBRD] /* -> UARTFBRD (Baud divisor fraction)= */ mov \rc, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE / 16) - str \rc, [\rb, #IBRD] /* -> UARTIBRD (Baud divisor integer) = */ + strh \rc, [\rb, #IBRD] /* -> UARTIBRD (Baud divisor integer) = */ mov \rc, #WLEN_8 /* 8n1 */ - str \rc, [\rb, #LCR_H] /* -> UARTLCR_H (Line control) */ + strb \rc, [\rb, #LCR_H] /* -> UARTLCR_H (Line control) */ ldr \rc, =3D(RXE | TXE | UARTEN) /* RXE | TXE | UARTEN */ - str \rc, [\rb, #CR] /* -> UARTCR (Control Register) */ + strh \rc, [\rb, #CR] /* -> UARTCR (Control Register) */ .endm =20 /* @@ -42,7 +42,7 @@ */ .macro early_uart_ready rb, rc 1: - ldr \rc, [\rb, #FR] /* <- UARTFR (Flag register) */ + ldrh \rc, [\rb, #FR] /* <- UARTFR (Flag register) */ tst \rc, #BUSY /* Check BUSY bit */ bne 1b /* Wait for the UART to be ready */ .endm @@ -53,7 +53,7 @@ * rt: register which contains the character to transmit */ .macro early_uart_transmit rb, rt - str \rt, [\rb, #DR] /* -> UARTDR (Data Register) */ + strb \rt, [\rb, #DR] /* -> UARTDR (Data Register) */ .endm =20 /* diff --git a/xen/arch/arm/arm64/debug-pl011.inc b/xen/arch/arm/arm64/debug-= pl011.inc index 6d60e78c8ba3..df713eff4922 100644 --- a/xen/arch/arm/arm64/debug-pl011.inc +++ b/xen/arch/arm/arm64/debug-pl011.inc @@ -25,13 +25,13 @@ */ .macro early_uart_init xb, c mov x\c, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE % 16) - strh w\c, [\xb, #FBRD] /* -> UARTFBRD (Baud divisor fraction= ) */ + strb w\c, [\xb, #FBRD] /* -> UARTFBRD (Baud divisor fraction= ) */ mov x\c, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE / 16) strh w\c, [\xb, #IBRD] /* -> UARTIBRD (Baud divisor integer)= */ mov x\c, #WLEN_8 /* 8n1 */ - str w\c, [\xb, #LCR_H] /* -> UARTLCR_H (Line control) */ + strb w\c, [\xb, #LCR_H] /* -> UARTLCR_H (Line control) */ ldr x\c, =3D(RXE | TXE | UARTEN) - str w\c, [\xb, #CR] /* -> UARTCR (Control Register) */ + strh w\c, [\xb, #CR] /* -> UARTCR (Control Register) */ .endm =20 /* --=20 2.25.1 From nobody Thu Oct 31 23:52:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2023 09:27:49.8441 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43246eb3-bf50-47af-8c8c-08db67397651 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5650 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1686130102165100005 Content-Type: text/plain; charset="utf-8" There are implementations of PL011 that can only handle 32-bit accesses as oppose to the normal behavior where accesses are 8/16-bit wide. This is usually advertised by setting a dt property 'reg-io-width' to 4. Introduce CONFIG_EARLY_UART_PL011_MMIO32 Kconfig option to be able to enable the use of 32-bit only accessors in PL011 early printk code. Define macros PL011_{STRH,STRB,LDRH} to distinguish accessors for normal case from 32-bit MMIO one and use them in arm32/arm64 pl011 early printk code. Update documentation accordingly. Signed-off-by: Michal Orzel Reviewed-by: Stefano Stabellini Tested-by: Henry Wang --- I might want to align the indentation of operands but doing so in this patch is rather no go as it would limit the visibility of the scope of this patch. Something to do in the future. --- docs/misc/arm/early-printk.txt | 3 +++ xen/arch/arm/Kconfig.debug | 7 +++++++ xen/arch/arm/arm32/debug-pl011.inc | 12 ++++++------ xen/arch/arm/arm64/debug-pl011.inc | 12 ++++++------ xen/arch/arm/include/asm/pl011-uart.h | 19 +++++++++++++++++++ 5 files changed, 41 insertions(+), 12 deletions(-) diff --git a/docs/misc/arm/early-printk.txt b/docs/misc/arm/early-printk.txt index aa22826075a4..bc2d65aa2ea3 100644 --- a/docs/misc/arm/early-printk.txt +++ b/docs/misc/arm/early-printk.txt @@ -26,6 +26,9 @@ Other options depends on the driver selected: If CONFIG_EARLY_UART_PL011_BAUD_RATE is set to 0 then the code will not try to initialize the UART, so that bootloader or firmware settings can be used for maximum compatibility. + + - CONFIG_EARLY_UART_PL011_MMIO32 is, optionally, used to enable 32-bit + only accesses to registers. - scif - CONFIG_EARLY_UART_SCIF_VERSION_* is, optionally, the interface versi= on of the UART. Default to version NONE. diff --git a/xen/arch/arm/Kconfig.debug b/xen/arch/arm/Kconfig.debug index 842d768280c4..eec860e88e0b 100644 --- a/xen/arch/arm/Kconfig.debug +++ b/xen/arch/arm/Kconfig.debug @@ -253,6 +253,13 @@ config EARLY_UART_PL011_BAUD_RATE default 115200 if EARLY_PRINTK_FASTMODEL default 0 =20 +config EARLY_UART_PL011_MMIO32 + bool "32-bit only MMIO for PL011 early printk" + depends on EARLY_UART_PL011 + help + If specified, all accesses to PL011 registers made from early printk co= de + will be done using 32-bit only accessors. + config EARLY_UART_INIT depends on EARLY_UART_PL011 && EARLY_UART_PL011_BAUD_RATE !=3D 0 def_bool y diff --git a/xen/arch/arm/arm32/debug-pl011.inc b/xen/arch/arm/arm32/debug-= pl011.inc index 9fe0c2503831..5833da2a235c 100644 --- a/xen/arch/arm/arm32/debug-pl011.inc +++ b/xen/arch/arm/arm32/debug-pl011.inc @@ -26,13 +26,13 @@ */ .macro early_uart_init rb, rc, rd mov \rc, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE % 16) - strb \rc, [\rb, #FBRD] /* -> UARTFBRD (Baud divisor fraction)= */ + PL011_STRB \rc, [\rb, #FBRD] /* -> UARTFBRD (Baud divisor fracti= on) */ mov \rc, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE / 16) - strh \rc, [\rb, #IBRD] /* -> UARTIBRD (Baud divisor integer) = */ + PL011_STRH \rc, [\rb, #IBRD] /* -> UARTIBRD (Baud divisor intege= r) */ mov \rc, #WLEN_8 /* 8n1 */ - strb \rc, [\rb, #LCR_H] /* -> UARTLCR_H (Line control) */ + PL011_STRB \rc, [\rb, #LCR_H] /* -> UARTLCR_H (Line control) */ ldr \rc, =3D(RXE | TXE | UARTEN) /* RXE | TXE | UARTEN */ - strh \rc, [\rb, #CR] /* -> UARTCR (Control Register) */ + PL011_STRH \rc, [\rb, #CR] /* -> UARTCR (Control Register) */ .endm =20 /* @@ -42,7 +42,7 @@ */ .macro early_uart_ready rb, rc 1: - ldrh \rc, [\rb, #FR] /* <- UARTFR (Flag register) */ + PL011_LDRH \rc, [\rb, #FR] /* <- UARTFR (Flag register) */ tst \rc, #BUSY /* Check BUSY bit */ bne 1b /* Wait for the UART to be ready */ .endm @@ -53,7 +53,7 @@ * rt: register which contains the character to transmit */ .macro early_uart_transmit rb, rt - strb \rt, [\rb, #DR] /* -> UARTDR (Data Register) */ + PL011_STRB \rt, [\rb, #DR] /* -> UARTDR (Data Register) */ .endm =20 /* diff --git a/xen/arch/arm/arm64/debug-pl011.inc b/xen/arch/arm/arm64/debug-= pl011.inc index df713eff4922..430594610b2c 100644 --- a/xen/arch/arm/arm64/debug-pl011.inc +++ b/xen/arch/arm/arm64/debug-pl011.inc @@ -25,13 +25,13 @@ */ .macro early_uart_init xb, c mov x\c, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE % 16) - strb w\c, [\xb, #FBRD] /* -> UARTFBRD (Baud divisor fraction= ) */ + PL011_STRB w\c, [\xb, #FBRD] /* -> UARTFBRD (Baud divisor fracti= on) */ mov x\c, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE / 16) - strh w\c, [\xb, #IBRD] /* -> UARTIBRD (Baud divisor integer)= */ + PL011_STRH w\c, [\xb, #IBRD] /* -> UARTIBRD (Baud divisor intege= r) */ mov x\c, #WLEN_8 /* 8n1 */ - strb w\c, [\xb, #LCR_H] /* -> UARTLCR_H (Line control) */ + PL011_STRB w\c, [\xb, #LCR_H] /* -> UARTLCR_H (Line control) */ ldr x\c, =3D(RXE | TXE | UARTEN) - strh w\c, [\xb, #CR] /* -> UARTCR (Control Register) */ + PL011_STRH w\c, [\xb, #CR] /* -> UARTCR (Control Register) */ .endm =20 /* @@ -41,7 +41,7 @@ */ .macro early_uart_ready xb, c 1: - ldrh w\c, [\xb, #FR] /* <- UARTFR (Flag register) */ + PL011_LDRH w\c, [\xb, #FR] /* <- UARTFR (Flag register) */ tst w\c, #BUSY /* Check BUSY bit */ b.ne 1b /* Wait for the UART to be ready */ .endm @@ -52,7 +52,7 @@ * wt: register which contains the character to transmit */ .macro early_uart_transmit xb, wt - strb \wt, [\xb, #DR] /* -> UARTDR (Data Register) */ + PL011_STRB \wt, [\xb, #DR] /* -> UARTDR (Data Register) */ .endm =20 /* diff --git a/xen/arch/arm/include/asm/pl011-uart.h b/xen/arch/arm/include/a= sm/pl011-uart.h index 5bb563ec0814..27c9bfa444cb 100644 --- a/xen/arch/arm/include/asm/pl011-uart.h +++ b/xen/arch/arm/include/asm/pl011-uart.h @@ -21,6 +21,25 @@ #ifndef __ASM_ARM_PL011_H #define __ASM_ARM_PL011_H =20 +#ifdef __ASSEMBLY__ + +/* + * PL011 registers are 8/16-bit wide. However, there are implementations t= hat + * can only handle 32-bit accesses. The following macros used in early pri= ntk + * are defined to distinguish accessors for normal case from 32-bit MMIO o= ne. + */ +#ifdef CONFIG_EARLY_UART_PL011_MMIO32 +#define PL011_STRH str +#define PL011_STRB str +#define PL011_LDRH ldr +#else +#define PL011_STRH strh +#define PL011_STRB strb +#define PL011_LDRH ldrh +#endif + +#endif /* __ASSEMBLY__ */ + /* PL011 register addresses */ #define DR (0x00) #define RSR (0x04) --=20 2.25.1 From nobody Thu Oct 31 23:52:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1686130107; cv=pass; d=zohomail.com; s=zohoarc; b=OUQQEITmJfdgds8JtYA0W4bed9LR0GeNdCLr/D3d70xl3uA/CUkCSXdRJTjfPl2I5iP5WZZ5zJKLbuVRdG7yemNlnbaeH9CB1XM93xBB4BhFuulZO/pARlRxUceisOmL1ve61j6w805cH41ZqpNYf9+bYV+aYCHwqYNsbhFeIyg= ARC-Message-Signature: i=2; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 3/4] xen/arm: pl011: Use correct accessors Date: Wed, 7 Jun 2023 11:27:26 +0200 Message-ID: <20230607092727.19654-4-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607092727.19654-1-michal.orzel@amd.com> References: <20230607092727.19654-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT020:EE_|SA1PR12MB8597:EE_ X-MS-Office365-Filtering-Correlation-Id: b9949e3a-1cb8-468d-c34f-08db6739780e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2023 09:27:52.7618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9949e3a-1cb8-468d-c34f-08db6739780e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8597 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1686130107520100001 Content-Type: text/plain; charset="utf-8" At the moment, we use 32-bit only accessors (i.e. readl/writel) to match the SBSA v2.x requirement. This should not be the default case for normal PL011 where accesses shall be 8/16-bit (max register size is 16-bit). There are however implementations of this UART that can only handle 32-bit MMIO. This is advertised by dt property "reg-io-width" set to 4. Introduce new struct pl011 member mmio32 and replace pl011_{read/write} macros with static inline helpers that use 32-bit or 16-bit accessors (largest-common not to end up using different ones depending on the actual register size) according to mmio32 value. By default this property is set to false, unless: - reg-io-width is specified with value 4, - SBSA UART is in use. For now, no changes done for ACPI due to lack of testing possibilities (i.e. current behavior maintained resulting in 32-bit accesses). Signed-off-by: Michal Orzel Reviewed-by: Stefano Stabellini Tested-by: Henry Wang --- xen/drivers/char/pl011.c | 53 +++++++++++++++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 6 deletions(-) diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index 052a6512515c..403b1ac06551 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -41,6 +41,7 @@ static struct pl011 { /* unsigned int timeout_ms; */ /* bool_t probing, intr_works; */ bool sbsa; /* ARM SBSA generic interface */ + bool mmio32; /* 32-bit only MMIO */ } pl011_com =3D {0}; =20 /* These parity settings can be ORed directly into the LCR. */ @@ -50,9 +51,30 @@ static struct pl011 { #define PARITY_MARK (PEN|SPS) #define PARITY_SPACE (PEN|EPS|SPS) =20 -/* SBSA v2.x document requires, all reads/writes must be 32-bit accesses */ -#define pl011_read(uart, off) readl((uart)->regs + (off)) -#define pl011_write(uart, off,val) writel((val), (uart)->regs + (off)) +/* + * By default, PL011 accesses shall be done using 8/16-bit accessors to + * support legacy devices that cannot cope with 32-bit. On the other hand, + * there are implementations of PL011 that can only handle 32-bit MMIO. Al= so, + * SBSA v2.x requires 32-bit accesses. Note that for default case, we use + * largest-common accessors (i.e. 16-bit) not to end up using different on= es + * depending on the actual register size. + */ +static inline void +pl011_write(struct pl011 *uart, unsigned int offset, unsigned int val) +{ + if ( uart->mmio32 ) + writel(val, uart->regs + offset); + else + writew(val, uart->regs + offset); +} + +static inline unsigned int pl011_read(struct pl011 *uart, unsigned int off= set) +{ + if ( uart->mmio32 ) + return readl(uart->regs + offset); + + return readw(uart->regs + offset); +} =20 static unsigned int pl011_intr_status(struct pl011 *uart) { @@ -222,7 +244,8 @@ static struct uart_driver __read_mostly pl011_driver = =3D { .vuart_info =3D pl011_vuart, }; =20 -static int __init pl011_uart_init(int irq, paddr_t addr, paddr_t size, boo= l sbsa) +static int __init +pl011_uart_init(int irq, paddr_t addr, paddr_t size, bool sbsa, bool mmio3= 2) { struct pl011 *uart; =20 @@ -233,6 +256,9 @@ static int __init pl011_uart_init(int irq, paddr_t addr= , paddr_t size, bool sbsa uart->stop_bits =3D 1; uart->sbsa =3D sbsa; =20 + /* Set 32-bit MMIO also for SBSA since v2.x requires it */ + uart->mmio32 =3D (mmio32 || sbsa); + uart->regs =3D ioremap_nocache(addr, size); if ( !uart->regs ) { @@ -259,6 +285,8 @@ static int __init pl011_dt_uart_init(struct dt_device_n= ode *dev, const char *config =3D data; int res; paddr_t addr, size; + uint32_t io_width; + bool mmio32 =3D false; =20 if ( strcmp(config, "") ) { @@ -280,7 +308,19 @@ static int __init pl011_dt_uart_init(struct dt_device_= node *dev, return -EINVAL; } =20 - res =3D pl011_uart_init(res, addr, size, false); + /* See linux Documentation/devicetree/bindings/serial/pl011.yaml */ + if ( dt_property_read_u32(dev, "reg-io-width", &io_width) ) + { + if ( io_width =3D=3D 4 ) + mmio32 =3D true; + else if ( io_width !=3D 1 ) + { + printk("pl011: Unsupported reg-io-width (%"PRIu32")\n", io_wid= th); + return -EINVAL; + } + } + + res =3D pl011_uart_init(res, addr, size, false, mmio32); if ( res < 0 ) { printk("pl011: Unable to initialize\n"); @@ -328,8 +368,9 @@ static int __init pl011_acpi_uart_init(const void *data) /* trigger/polarity information is not available in spcr */ irq_set_type(spcr->interrupt, IRQ_TYPE_LEVEL_HIGH); =20 + /* TODO - mmio32 proper handling (for now set to true) */ res =3D pl011_uart_init(spcr->interrupt, spcr->serial_port.address, - PAGE_SIZE, sbsa); + PAGE_SIZE, sbsa, true); if ( res < 0 ) { printk("pl011: Unable to initialize\n"); --=20 2.25.1 From nobody Thu Oct 31 23:52:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1686130107; cv=pass; d=zohomail.com; s=zohoarc; b=n9B0VkFSidF4RXQqNSfpQY6I6BAruvXFxlnvAEdHw6az/XjBC42wcKys9FYlEc4FIV9ihpiDBcTNaIr1sCni2D9LEgg23P2UJM746EDCnDcQWDIIH1AvJayseNePEK8XcBrHT/fCi0yMtm7bRTwZ/HisaDlIeJ6Jp26AZO4O+H4= ARC-Message-Signature: i=2; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 4/4] xen/arm: pl011: Add SBSA UART device-tree support Date: Wed, 7 Jun 2023 11:27:27 +0200 Message-ID: <20230607092727.19654-5-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607092727.19654-1-michal.orzel@amd.com> References: <20230607092727.19654-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT020:EE_|DS0PR12MB6462:EE_ X-MS-Office365-Filtering-Correlation-Id: bb995567-5812-46e7-2cf2-08db673978de X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2023 09:27:54.1211 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb995567-5812-46e7-2cf2-08db673978de X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6462 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1686130109379100003 Content-Type: text/plain; charset="utf-8" We already have all the bits necessary in PL011 driver to support SBSA UART thanks to commit 032ea8c736d10f02672863c6e369338f948f7ed8 that enabled it for ACPI. Plumb in the remaining part for device-tree boot: - add arm,sbsa-uart compatible to pl011_dt_match (no need for a separate struct and DT_DEVICE_START as SBSA is a subset of PL011), - from pl011_dt_uart_init(), check for SBSA UART compatible to determine the UART type in use. Signed-off-by: Michal Orzel Reviewed-by: Henry Wang Reviewed-by: Stefano Stabellini Tested-by: Henry Wang --- After this series the last thing not to be in spec for newer UARTs (well, for rev1.5 introduced in 2007 I believe) is incorrect FIFO size. We hardcod= e it to 16 but in r1.5 it is 32. This requires checking the peripheral ID regist= er or using arm,primecell-periphid dt property for overriding HW. Something to be done in the future (at least 16 is not harmful). --- xen/drivers/char/pl011.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index 403b1ac06551..f7bf3ad117af 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -286,7 +286,7 @@ static int __init pl011_dt_uart_init(struct dt_device_n= ode *dev, int res; paddr_t addr, size; uint32_t io_width; - bool mmio32 =3D false; + bool mmio32 =3D false, sbsa; =20 if ( strcmp(config, "") ) { @@ -320,7 +320,9 @@ static int __init pl011_dt_uart_init(struct dt_device_n= ode *dev, } } =20 - res =3D pl011_uart_init(res, addr, size, false, mmio32); + sbsa =3D dt_device_is_compatible(dev, "arm,sbsa-uart"); + + res =3D pl011_uart_init(res, addr, size, sbsa, mmio32); if ( res < 0 ) { printk("pl011: Unable to initialize\n"); @@ -335,6 +337,8 @@ static int __init pl011_dt_uart_init(struct dt_device_n= ode *dev, static const struct dt_device_match pl011_dt_match[] __initconst =3D { DT_MATCH_COMPATIBLE("arm,pl011"), + /* No need for a separate struct as SBSA UART is a subset of PL011 */ + DT_MATCH_COMPATIBLE("arm,sbsa-uart"), { /* sentinel */ }, }; =20 --=20 2.25.1