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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH] xen/arm: debug-pl011: Use 32-bit accessors for broader compatibility Date: Thu, 1 Jun 2023 10:50:01 +0200 Message-ID: <20230601085001.1782-1-michal.orzel@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT088:EE_|PH0PR12MB5401:EE_ X-MS-Office365-Filtering-Correlation-Id: 0242eac6-b127-4595-7079-08db627d3c0d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hGUabM30yQNiM9GrEJNtSRbOjVrMbG/W1m4CWoXiMbICCmeuK1YRJ3exaM9UW4hEuAM7fDmZRl+ucDhfBMCuP2YIcsdaAnLMIj6V6gkSroNp0N7i+adQSb8Sffjt3epJD1Q3qsTIDB5Zwpnyife9mAAmoL4Ma8ACKmOPG65wQM9riq6YQmNlxRbY/nsXjAsp0o6IQ0U54LYdZWJ9csj0eLOABrjQtX0z1QvDry4afVF+z0k8/7dU/QtL7TG6aHDtbIQbd/rIj0oSXdAhneKhCOcNjWauRcH6HKc4YdZfxP6BVK0OcrbYT7Lj+WPqm8J2CKD5Bu2krqTAlsUJMv2+yx1HovkanhOwDqjJ3ao4EbllX8Ykfdk28tcHfli1ux49GFU2FRkDllsVhYiTXHiSTTu0EB4xNj2knkTmgUjCFVLWk5Rz++fTcYiMWM1wk+IYGbm/Qnc+CoiKYg1DFGRtj0KI58Rz4rUZvGUBLWGTyCsSPrf22ex74hJzphw7GIHlENw+IO9npjEXTTnxNz38XJXhL9hYrLdWyeW1HjYAEhwggoIBViwJU+ulF6AzduB0TVrMO0eLwRRpyHovr6rR0dUdX0RgPA19t6wRdI/1QRt/vMUnvq2bgqSlzzKhVuUdhAWWTncY4S+QktrWT9Nkqiyj/2UBxAIrgYoRwXeb3MBHWNRdlGpaunA0bhfzwtObqm9Z48Aqh+pOHqYG0wQlsAyMbxhOX9IQP0zGVv7Rpo66zmHzm8XVwFbfOtwkK8vqy1aKVbYICy/rMqMhLNZNRg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(136003)(376002)(346002)(39860400002)(451199021)(46966006)(36840700001)(40470700004)(83380400001)(26005)(1076003)(336012)(426003)(41300700001)(6666004)(47076005)(186003)(36860700001)(2616005)(478600001)(40460700003)(54906003)(81166007)(4326008)(6916009)(356005)(70586007)(70206006)(40480700001)(82740400003)(316002)(82310400005)(5660300002)(8676002)(8936002)(44832011)(2906002)(86362001)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jun 2023 08:50:22.0536 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0242eac6-b127-4595-7079-08db627d3c0d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT088.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5401 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1685609469816100001 Content-Type: text/plain; charset="utf-8" There are implementations of the PL011 that can only handle 32-bit accesses (i.e. no 16-bit or 8-bit), usually advertised by 'reg-io-width' dt property set to 4. On such UARTs, the current early printk code for arm64 does not work. To fix this issue, make all the accesses to be 32-bit by using ldr, str without a size field. This makes it possible to use early printk on such platforms, while all the other implementations should generally cope with 32-bit accesses. In case they do not, they would already fail as we explicitly use writel/readl in the runtime driver to maintain broader compatibility and to be SBSAv2 compliant. Therefore, this change makes the runtime/early handling consistent (also it matches the arm32 debug-pl011 code). Signed-off-by: Michal Orzel Reviewed-by: Henry Wang --- xen/arch/arm/arm64/debug-pl011.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm64/debug-pl011.inc b/xen/arch/arm/arm64/debug-= pl011.inc index 6d60e78c8ba3..80eb8fdc1ec7 100644 --- a/xen/arch/arm/arm64/debug-pl011.inc +++ b/xen/arch/arm/arm64/debug-pl011.inc @@ -25,9 +25,9 @@ */ .macro early_uart_init xb, c mov x\c, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE % 16) - strh w\c, [\xb, #FBRD] /* -> UARTFBRD (Baud divisor fraction= ) */ + str w\c, [\xb, #FBRD] /* -> UARTFBRD (Baud divisor fraction= ) */ mov x\c, #(7372800 / CONFIG_EARLY_UART_PL011_BAUD_RATE / 16) - strh w\c, [\xb, #IBRD] /* -> UARTIBRD (Baud divisor integer)= */ + str w\c, [\xb, #IBRD] /* -> UARTIBRD (Baud divisor integer)= */ mov x\c, #WLEN_8 /* 8n1 */ str w\c, [\xb, #LCR_H] /* -> UARTLCR_H (Line control) */ ldr x\c, =3D(RXE | TXE | UARTEN) @@ -41,7 +41,7 @@ */ .macro early_uart_ready xb, c 1: - ldrh w\c, [\xb, #FR] /* <- UARTFR (Flag register) */ + ldr w\c, [\xb, #FR] /* <- UARTFR (Flag register) */ tst w\c, #BUSY /* Check BUSY bit */ b.ne 1b /* Wait for the UART to be ready */ .endm @@ -52,7 +52,7 @@ * wt: register which contains the character to transmit */ .macro early_uart_transmit xb, wt - strb \wt, [\xb, #DR] /* -> UARTDR (Data Register) */ + str \wt, [\xb, #DR] /* -> UARTDR (Data Register) */ .endm =20 /* --=20 2.25.1