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d="scan'208";a="109294592" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 1/4] x86/spec-ctrl: Rename retpoline_safe() to retpoline_calculations() Date: Fri, 26 May 2023 12:06:52 +0100 Message-ID: <20230526110656.4018711-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230526110656.4018711-1-andrew.cooper3@citrix.com> References: <20230526110656.4018711-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1685099283895100005 This is prep work, split out to simply the diff on the following change. * Rename to retpoline_calculations(), and call unconditionally. It is shortly going to synthesize missing enumerations required for guest safe= ty. * For Broadwell, store the ucode revision calculation in a variable and fa= ll out of the bottom of the switch statement. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- xen/arch/x86/spec_ctrl.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 50d467f74cf8..0774d40627dd 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -579,9 +579,10 @@ static bool __init check_smt_enabled(void) } =20 /* Calculate whether Retpoline is known-safe on this CPU. */ -static bool __init retpoline_safe(void) +static bool __init retpoline_calculations(void) { unsigned int ucode_rev =3D this_cpu(cpu_sig).rev; + bool safe =3D false; =20 if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) return true; @@ -626,18 +627,18 @@ static bool __init retpoline_safe(void) * versions. */ case 0x3d: /* Broadwell */ - return ucode_rev >=3D 0x2a; + safe =3D ucode_rev >=3D 0x2a; break; case 0x47: /* Broadwell H */ - return ucode_rev >=3D 0x1d; + safe =3D ucode_rev >=3D 0x1d; break; case 0x4f: /* Broadwell EP/EX */ - return ucode_rev >=3D 0xb000021; + safe =3D ucode_rev >=3D 0xb000021; break; case 0x56: /* Broadwell D */ switch ( boot_cpu_data.x86_mask ) { - case 2: return ucode_rev >=3D 0x15; - case 3: return ucode_rev >=3D 0x7000012; - case 4: return ucode_rev >=3D 0xf000011; - case 5: return ucode_rev >=3D 0xe000009; + case 2: safe =3D ucode_rev >=3D 0x15; break; + case 3: safe =3D ucode_rev >=3D 0x7000012; break; + case 4: safe =3D ucode_rev >=3D 0xf000011; break; + case 5: safe =3D ucode_rev >=3D 0xe000009; break; default: printk("Unrecognised CPU stepping %#x - assuming not reptpolin= e safe\n", boot_cpu_data.x86_mask); @@ -681,6 +682,12 @@ static bool __init retpoline_safe(void) boot_cpu_data.x86_model); return false; } + + /* Only Broadwell gets here. */ + if ( safe ) + return true; + + return false; } =20 /* @@ -1113,7 +1120,7 @@ void __init init_speculation_mitigations(void) { enum ind_thunk thunk =3D THUNK_DEFAULT; bool has_spec_ctrl, ibrs =3D false, hw_smt_enabled; - bool cpu_has_bug_taa; + bool cpu_has_bug_taa, retpoline_safe; =20 hw_smt_enabled =3D check_smt_enabled(); =20 @@ -1139,6 +1146,9 @@ void __init init_speculation_mitigations(void) thunk =3D THUNK_JMP; } =20 + /* Determine if retpoline is safe on this CPU. */ + retpoline_safe =3D retpoline_calculations(); + /* * Has the user specified any custom BTI mitigations? If so, follow t= heir * instructions exactly and disable all heuristics. @@ -1160,7 +1170,7 @@ void __init init_speculation_mitigations(void) * On all hardware, we'd like to use retpoline in preference to * IBRS, but only if it is safe on this hardware. */ - if ( retpoline_safe() ) + if ( retpoline_safe ) thunk =3D THUNK_RETPOLINE; else if ( has_spec_ctrl ) ibrs =3D true; --=20 2.30.2 From nobody Thu Apr 18 13:42:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1685099289; cv=none; d=zohomail.com; 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d="scan'208";a="113007428" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 2/4] x86/spec-ctrl: Synthesize RSBA/RRSBA bits with older microcode Date: Fri, 26 May 2023 12:06:54 +0100 Message-ID: <20230526110656.4018711-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230526110656.4018711-1-andrew.cooper3@citrix.com> References: <20230526110656.4018711-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1685099290526100005 In order to level a VM safely for migration, the toolstack needs to know the RSBA/RRSBA properties of the CPU, whether or not they happen to be enumerat= ed. Synthesize the bits when missing. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/spec_ctrl.c | 50 +++++++++++++++++++++++---- 2 files changed, 44 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/a= sm/cpufeature.h index 50235f098d70..08e3eedd1280 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -192,6 +192,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_tsx_ctrl boot_cpu_has(X86_FEATURE_TSX_CTRL) #define cpu_has_taa_no boot_cpu_has(X86_FEATURE_TAA_NO) #define cpu_has_fb_clear boot_cpu_has(X86_FEATURE_FB_CLEAR) +#define cpu_has_rrsba boot_cpu_has(X86_FEATURE_RRSBA) =20 /* Synthesized. */ #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 0774d40627dd..2647784615cc 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -578,7 +578,10 @@ static bool __init check_smt_enabled(void) return false; } =20 -/* Calculate whether Retpoline is known-safe on this CPU. */ +/* + * Calculate whether Retpoline is known-safe on this CPU. Synthesize miss= ing + * RSBA/RRSBA bits when running with old microcode. + */ static bool __init retpoline_calculations(void) { unsigned int ucode_rev =3D this_cpu(cpu_sig).rev; @@ -592,13 +595,18 @@ static bool __init retpoline_calculations(void) return false; =20 /* - * RSBA may be set by a hypervisor to indicate that we may move to a - * processor which isn't retpoline-safe. - * * Processors offering Enhanced IBRS are not guarenteed to be * repoline-safe. */ - if ( cpu_has_rsba || cpu_has_eibrs ) + if ( cpu_has_eibrs ) + goto unsafe_maybe_fixup_rrsba; + + /* + * RSBA is explicitly enumerated in some cases, but may also be set by= a + * hypervisor to indicate that we may move to a processor which isn't + * retpoline-safe. + */ + if ( cpu_has_rsba ) return false; =20 switch ( boot_cpu_data.x86_model ) @@ -648,6 +656,8 @@ static bool __init retpoline_calculations(void) =20 /* * Skylake, Kabylake and Cannonlake processors are not retpoline-s= afe. + * Note: the eIBRS-capable steppings are filtered out earlier, so = the + * remainder here are the ones which suffer only RSBA behaviour. */ case 0x4e: /* Skylake M */ case 0x55: /* Skylake X */ @@ -656,7 +666,7 @@ static bool __init retpoline_calculations(void) case 0x67: /* Cannonlake? */ case 0x8e: /* Kabylake M */ case 0x9e: /* Kabylake D */ - return false; + goto unsafe_maybe_fixup_rsba; =20 /* * Atom processors before Goldmont Plus/Gemini Lake are retpoline-= safe. @@ -687,6 +697,32 @@ static bool __init retpoline_calculations(void) if ( safe ) return true; =20 + /* + * The meaning of the RSBA and RRSBA bits have evolved over time. The + * agreed upon meaning at the time of writing (May 2023) is thus: + * + * - RSBA (RSB Alterantive) means that an RSB may fall back to an + * alternative predictor on underflow. Skylake uarch and later all = have + * this property. Broadwell too, when running microcode versions pr= ior + * to Jan 2018. + * + * - All eIBRS-capable processors suffer RSBA, but eIBRS also introduc= es + * tagging of predictions with the mode in which they were learned. = So + * when eIBRS is active, RSBA becomes RRSBA (Restricted RSBA). + * + * Some parts (Broadwell) are not expected to ever enumerate this + * behaviour directly. Other parts have differing enumeration with + * microcode version. Fix up Xen's idea, so we can advertise them saf= ely + * to guests, and so toolstacks can level a VM safelty for migration. + */ + unsafe_maybe_fixup_rrsba: + if ( !cpu_has_rrsba ) + setup_force_cpu_cap(X86_FEATURE_RRSBA); + + unsafe_maybe_fixup_rsba: + if ( !cpu_has_rsba ) + setup_force_cpu_cap(X86_FEATURE_RSBA); + return false; } =20 @@ -1146,7 +1182,7 @@ void __init init_speculation_mitigations(void) thunk =3D THUNK_JMP; } =20 - /* Determine if retpoline is safe on this CPU. */ + /* Determine if retpoline is safe on this CPU. Fix up RSBA/RRSBA enum= erations. */ retpoline_safe =3D retpoline_calculations(); =20 /* --=20 2.30.2 From nobody Thu Apr 18 13:42:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1685099280; cv=none; d=zohomail.com; s=zohoarc; b=jcDYPbBsGbjv4PUd5ZMJOX7BGPkAFZryDVphb/v918BN1C6lGfq1gI1PXNtRapfFvRDKQgJ7kKihRfNR3LsfDMrnMJMLr5626Ud/nOoGhlwZHUPtCPlnWsYJoFCZ8wLDq9URs6EM+SzOmGqkfXsBxcH+Xf/LLVmALRRCcRXNs/U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685099280; 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d="scan'208";a="113007427" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper Subject: [PATCH 2/4] x86/spec-ctrl: Synthesize missing RSBA/RRSBA bits Date: Fri, 26 May 2023 12:06:53 +0100 Message-ID: <20230526110656.4018711-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230526110656.4018711-1-andrew.cooper3@citrix.com> References: <20230526110656.4018711-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1685099282962100003 Content-Type: text/plain; charset="utf-8" --- xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/spec_ctrl.c | 50 +++++++++++++++++++++++---- 2 files changed, 44 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/a= sm/cpufeature.h index 50235f098d70..08e3eedd1280 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -192,6 +192,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_tsx_ctrl boot_cpu_has(X86_FEATURE_TSX_CTRL) #define cpu_has_taa_no boot_cpu_has(X86_FEATURE_TAA_NO) #define cpu_has_fb_clear boot_cpu_has(X86_FEATURE_FB_CLEAR) +#define cpu_has_rrsba boot_cpu_has(X86_FEATURE_RRSBA) =20 /* Synthesized. */ #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 0774d40627dd..daf77d77e139 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -578,7 +578,10 @@ static bool __init check_smt_enabled(void) return false; } =20 -/* Calculate whether Retpoline is known-safe on this CPU. */ +/* + * Calculate whether Retpoline is known-safe on this CPU. Fixes up missing + * RSBA/RRSBA enumeration from older microcode versions. + */ static bool __init retpoline_calculations(void) { unsigned int ucode_rev =3D this_cpu(cpu_sig).rev; @@ -592,13 +595,18 @@ static bool __init retpoline_calculations(void) return false; =20 /* - * RSBA may be set by a hypervisor to indicate that we may move to a - * processor which isn't retpoline-safe. - * * Processors offering Enhanced IBRS are not guarenteed to be * repoline-safe. */ - if ( cpu_has_rsba || cpu_has_eibrs ) + if ( cpu_has_eibrs ) + goto unsafe_maybe_fixup_rrsba; + + /* + * RSBA is explicitly enumerated in some cases, but may also be set by= a + * hypervisor to indicate that we may move to a processor which isn't + * retpoline-safe. + */ + if ( cpu_has_rsba ) return false; =20 switch ( boot_cpu_data.x86_model ) @@ -648,6 +656,8 @@ static bool __init retpoline_calculations(void) =20 /* * Skylake, Kabylake and Cannonlake processors are not retpoline-s= afe. + * Note: the eIBRS-capable steppings are filtered out earlier, so = the + * remainder here are the ones which suffer only RSBA behaviour. */ case 0x4e: /* Skylake M */ case 0x55: /* Skylake X */ @@ -656,7 +666,7 @@ static bool __init retpoline_calculations(void) case 0x67: /* Cannonlake? */ case 0x8e: /* Kabylake M */ case 0x9e: /* Kabylake D */ - return false; + goto unsafe_maybe_fixup_rsba; =20 /* * Atom processors before Goldmont Plus/Gemini Lake are retpoline-= safe. @@ -687,6 +697,32 @@ static bool __init retpoline_calculations(void) if ( safe ) return true; =20 + /* + * The meaning of the RSBA and RRSBA bits have evolved over time. The + * agreed upon meaning at the time of writing (May 2023) is thus: + * + * - RSBA (RSB Alterantive) means that an RSB may fall back to an + * alternative predictor on underflow. Skylake uarch and later all = have + * this property. Broadwell too, when running microcode versions pr= ior + * to Jan 2018. + * + * - All eIBRS-capable processors suffer RSBA, but eIBRS also introduc= es + * tagging of predictions with the mode in which they were learned. = So + * when eIBRS is active, RSBA becomes RRSBA (Restricted RSBA). + * + * Some parts (Broadwell) are not expected to ever enumerate this + * behaviour directly. Other parts have differing enumeration with + * microcode version. Fix up Xen's idea, so we can advertise them saf= ely + * to guests, and so toolstacks can level a VM safelty for migration. + */ + unsafe_maybe_fixup_rrsba: + if ( !cpu_has_rrsba ) + setup_force_cpu_cap(X86_FEATURE_RRSBA); + + unsafe_maybe_fixup_rsba: + if ( !cpu_has_rsba ) + setup_force_cpu_cap(X86_FEATURE_RSBA); + return false; } =20 @@ -1146,7 +1182,7 @@ void __init init_speculation_mitigations(void) thunk =3D THUNK_JMP; } =20 - /* Determine if retpoline is safe on this CPU. */ + /* Determine if retpoline is safe on this CPU. Fix up RSBA/RRSBA enum= erations. */ retpoline_safe =3D retpoline_calculations(); =20 /* --=20 2.30.2 From nobody Thu Apr 18 13:42:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1685099288; cv=none; d=zohomail.com; s=zohoarc; b=k8Q0oj1f3OjFXEOKFuC1Qg58QNyNZb4RMLuMMCLyQSGYADzPW59R4HKZ2Pji/IxR62EW6fEOMnlxMMp1eEqrsHHGXiN73f8bowpmrHm4DFlrEVx1WRMb60dkxdb9Hh2Gct5LZcYfgQEZis/m/ez1m55UiWXwPT9ruIrDlvgyfTY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685099288; 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d="scan'208";a="109294593" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 3/4] x86/cpu-policy: Rearrange guest_common_default_feature_adjustments() Date: Fri, 26 May 2023 12:06:55 +0100 Message-ID: <20230526110656.4018711-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230526110656.4018711-1-andrew.cooper3@citrix.com> References: <20230526110656.4018711-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1685099288548100003 This is prep work, split out to simply the diff on the following change. * Split the INTEL check out of the IvyBridge RDRAND check, as the former w= ill be reused. * Use asm/intel-family.h to remove a raw 0x3a model number. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- xen/arch/x86/cpu-policy.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 74266d30b551..bdbc5660acd4 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -429,21 +430,24 @@ static void __init guest_common_max_feature_adjustmen= ts(uint32_t *fs) =20 static void __init guest_common_default_feature_adjustments(uint32_t *fs) { - /* - * IvyBridge client parts suffer from leakage of RDRAND data due to SR= BDS - * (XSA-320 / CVE-2020-0543), and won't be receiving microcode to - * compensate. - * - * Mitigate by hiding RDRAND from guests by default, unless explicitly - * overridden on the Xen command line (cpuid=3Drdrand). Irrespective = of the - * default setting, guests can use RDRAND if explicitly enabled - * (cpuid=3D"host,rdrand=3D1") in the VM's config file, and VMs which = were - * previously using RDRAND can migrate in. - */ - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && - boot_cpu_data.x86 =3D=3D 6 && boot_cpu_data.x86_model =3D=3D 0x3a= && - cpu_has_rdrand && !is_forced_cpu_cap(X86_FEATURE_RDRAND) ) - __clear_bit(X86_FEATURE_RDRAND, fs); + if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) + { + /* + * IvyBridge client parts suffer from leakage of RDRAND data due t= o SRBDS + * (XSA-320 / CVE-2020-0543), and won't be receiving microcode to + * compensate. + * + * Mitigate by hiding RDRAND from guests by default, unless explic= itly + * overridden on the Xen command line (cpuid=3Drdrand). Irrespect= ive of the + * default setting, guests can use RDRAND if explicitly enabled + * (cpuid=3D"host,rdrand=3D1") in the VM's config file, and VMs wh= ich were + * previously using RDRAND can migrate in. + */ + if ( boot_cpu_data.x86 =3D=3D 6 && + boot_cpu_data.x86_model =3D=3D INTEL_FAM6_IVYBRIDGE && + cpu_has_rdrand && !is_forced_cpu_cap(X86_FEATURE_RDRAND) ) + __clear_bit(X86_FEATURE_RDRAND, fs); + } =20 /* * On certain hardware, speculative or errata workarounds can result in --=20 2.30.2 From nobody Thu Apr 18 13:42:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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d="scan'208";a="113007431" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 4/4] x86/cpu-policy: Derive {,R}RSBA for guest policies Date: Fri, 26 May 2023 12:06:56 +0100 Message-ID: <20230526110656.4018711-6-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230526110656.4018711-1-andrew.cooper3@citrix.com> References: <20230526110656.4018711-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1685099281428100001 The RSBA bit, "RSB Alternative", means that the RSB may use alternative predictors when empty. From a practical point of view, this mean "Retpoline not safe". Enhanced IBRS (officially IBRS_ALL in Intel's docs, previously IBRS_ATT) is= a statement that IBRS is implemented in hardware (as opposed to the form retrofitted to existing CPUs in microcode). The RRSBA bit, "Restricted-RSBA", is a combination of RSBA, and the eIBRS property that predictions are tagged with the mode in which they were learn= t. Therefore, it means "when eIBRS is active, the RSB may fall back to alternative predictors but restricted to the current prediction mode". As such, it's stronger statement than RSBA, but still means "Retpoline not saf= e". Add feature dependencies for EIBRS and RRSBA. While technically they're not linked, absolutely nothing good can of letting the guest see RRSBA without EIBRS. Furthermore, we use this dependency to simplify the max/default derivation logic. The max policies gets RSBA and RRSBA unconditionally set (with the EIBRS dependency maybe hiding RRSBA). We can run any VM, even if it has been told "somewhere else, Retpoline isn't safe". The default policies inherit the host settings, because the guest wants to = run with as few (anti)features as it can safely get away with. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- xen/arch/x86/cpu-policy.c | 25 +++++++++++++++++++++++++ xen/tools/gen-cpuid.py | 5 ++++- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index bdbc5660acd4..eb1ecb75f593 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -423,8 +423,14 @@ static void __init guest_common_max_feature_adjustment= s(uint32_t *fs) * Retpoline not safe)", so these need to be visible to a guest in= all * cases, even when it's only some other server in the pool which * suffers the identified behaviour. + * + * We can always run any VM which has previously (or will + * subsequently) run on hardware where Retpoline is not safe. Not= e: + * The dependency logic may hide RRSBA for other reasons. */ __set_bit(X86_FEATURE_ARCH_CAPS, fs); + __set_bit(X86_FEATURE_RSBA, fs); + __set_bit(X86_FEATURE_RRSBA, fs); } } =20 @@ -432,6 +438,25 @@ static void __init guest_common_default_feature_adjust= ments(uint32_t *fs) { if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) { + /* + * The {,R}RSBA bits under virt mean "you might migrate somewhere + * where retpoline is not safe". In particular, a VM's settings m= ay + * not be applicable to the current host. + * + * Discard the settings inherited from the max policy, and and fee= d in + * the host values. The ideal case for a VM is for neither of the= se + * bits to be set, but toolstacks must accumuate them across anywh= ere + * the VM might migrate to, in case any possible destination happe= ns + * to be unsafe. + * + * Note: The dependency logic might hide RRSBA for other reasons. + */ + fs[FEATURESET_m10Al] &=3D ~(cpufeat_mask(X86_FEATURE_RSBA) | + cpufeat_mask(X86_FEATURE_RRSBA)); + fs[FEATURESET_m10Al] |=3D + host_cpu_policy.arch_caps.lo & (cpufeat_mask(X86_FEATURE_RSBA)= | + cpufeat_mask(X86_FEATURE_RRSBA= )); + /* * IvyBridge client parts suffer from leakage of RDRAND data due t= o SRBDS * (XSA-320 / CVE-2020-0543), and won't be receiving microcode to diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index f28ff708a2fc..22294a26adc0 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -318,7 +318,7 @@ def crunch_numbers(state): # IBRSB/IBRS, and we pass this MSR directly to guests. Treating t= hem # as dependent features simplifies Xen's logic, and prevents the g= uest # from seeing implausible configurations. - IBRSB: [STIBP, SSBD, INTEL_PSFD], + IBRSB: [STIBP, SSBD, INTEL_PSFD, EIBRS], IBRS: [AMD_STIBP, AMD_SSBD, PSFD, IBRS_ALWAYS, IBRS_FAST, IBRS_SAME_MODE], AMD_STIBP: [STIBP_ALWAYS], @@ -328,6 +328,9 @@ def crunch_numbers(state): =20 # The ARCH_CAPS CPUID bit enumerates the availability of the whole= register. ARCH_CAPS: list(range(RDCL_NO, RDCL_NO + 64)), + + # The behaviour described by RRSBA depend on eIBRS being active. + EIBRS: [RRSBA], } =20 deep_features =3D tuple(sorted(deps.keys())) --=20 2.30.2