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d="scan'208";a="112680542" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH v2 04/10] x86/cpu-policy: MSR_ARCH_CAPS feature names Date: Wed, 24 May 2023 12:25:20 +0100 Message-ID: <20230524112526.3475200-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230524112526.3475200-1-andrew.cooper3@citrix.com> References: <20230524112526.3475200-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1684927592985100011 Seed the default visibility from the dom0 special case, which for the most part just exposes the *_NO bits. EIBRS is the one non-*_NO bit, which is "just" a status bit to the guest indicating a change in implemention of IBRS which is already fully supported. Insert a block dependency from the ARCH_CAPS CPUID bit to the entire content of the MSR. This is because MSRs have no structure information similar to CPUID, and used by x86_cpu_policy_clear_out_of_range_leaves(), in order to bulk-clear inaccessable words. The overall CPUID bit is still max-only, so all of MSR_ARCH_CAPS is hidden = in the default policies. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu There is no libxl logic because libxl still uses the older xend format which is specific to CPUID data. That is going to need untangling at some other point. v2: * Don't expose SKIP_L1DFL to guests (it's only applicable for nested virt) * Fix SBDR_SSDP_NO and FBSDP_NO names. * Extend the commit message. --- tools/misc/xen-cpuid.c | 13 ++++++++++++ xen/include/public/arch-x86/cpufeatureset.h | 23 +++++++++++++++++++++ xen/tools/gen-cpuid.py | 3 +++ 3 files changed, 39 insertions(+) diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 15ad2d33e2a1..8925a583edd5 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -228,6 +228,19 @@ static const char *const str_7d2[32] =3D =20 static const char *const str_10Al[32] =3D { + [ 0] =3D "rdcl-no", [ 1] =3D "eibrs", + [ 2] =3D "rsba", [ 3] =3D "skip-l1dfl", + [ 4] =3D "intel-ssb-no", [ 5] =3D "mds-no", + [ 6] =3D "if-pschange-mc-no", [ 7] =3D "tsx-ctrl", + [ 8] =3D "taa-no", [ 9] =3D "mcu-ctrl", + [10] =3D "misc-pkg-ctrl", [11] =3D "energy-ctrl", + [12] =3D "doitm", [13] =3D "sbdr-ssdp-no", + [14] =3D "fbsdp-no", [15] =3D "psdp-no", + /* 16 */ [17] =3D "fb-clear", + [18] =3D "fb-clear-ctrl", [19] =3D "rrsba", + [20] =3D "bhi-no", [21] =3D "xapic-status", + /* 22 */ [23] =3D "ovrclk-status", + [24] =3D "pbrsb-no", }; =20 static const char *const str_10Ah[32] =3D diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/publ= ic/arch-x86/cpufeatureset.h index 032cec3ccba2..033b1a72feea 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -308,6 +308,29 @@ XEN_CPUFEATURE(AVX_NE_CONVERT, 15*32+ 5) /*A AVX-= NE-CONVERT Instructions */ XEN_CPUFEATURE(CET_SSS, 15*32+18) /* CET Supervisor Shadow St= acks safe to use */ =20 /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.eax, word 16 */ +XEN_CPUFEATURE(RDCL_NO, 16*32+ 0) /*A No Rogue Data Cache Load= (Meltdown) */ +XEN_CPUFEATURE(EIBRS, 16*32+ 1) /*A Enhanced IBRS */ +XEN_CPUFEATURE(RSBA, 16*32+ 2) /*!A RSB Alternative (Retpoli= ne not safe) */ +XEN_CPUFEATURE(SKIP_L1DFL, 16*32+ 3) /* Don't need to flush L1D = on VMEntry */ +XEN_CPUFEATURE(INTEL_SSB_NO, 16*32+ 4) /*A No Speculative Store Byp= ass */ +XEN_CPUFEATURE(MDS_NO, 16*32+ 5) /*A No Microarchitectural Da= ta Sampling */ +XEN_CPUFEATURE(IF_PSCHANGE_MC_NO, 16*32+ 6) /*A No Instruction fetch #MC= */ +XEN_CPUFEATURE(TSX_CTRL, 16*32+ 7) /* MSR_TSX_CTRL */ +XEN_CPUFEATURE(TAA_NO, 16*32+ 8) /*A No TSX Async Abort */ +XEN_CPUFEATURE(MCU_CTRL, 16*32+ 9) /* MSR_MCU_CTRL */ +XEN_CPUFEATURE(MISC_PKG_CTRL, 16*32+10) /* MSR_MISC_PKG_CTRL */ +XEN_CPUFEATURE(ENERGY_FILTERING, 16*32+11) /* MSR_MISC_PKG_CTRL.ENERGY= _FILTERING */ +XEN_CPUFEATURE(DOITM, 16*32+12) /* Data Operand Invariant T= iming Mode */ +XEN_CPUFEATURE(SBDR_SSDP_NO, 16*32+13) /*A No Shared Buffer Data Re= ad or Sideband Stale Data Propagation */ +XEN_CPUFEATURE(FBSDP_NO, 16*32+14) /*A No Fill Buffer Stale Dat= a Propagation */ +XEN_CPUFEATURE(PSDP_NO, 16*32+15) /*A No Primary Stale Data Pr= opagation */ +XEN_CPUFEATURE(FB_CLEAR, 16*32+17) /*A Fill Buffers cleared by = VERW */ +XEN_CPUFEATURE(FB_CLEAR_CTRL, 16*32+18) /* MSR_OPT_CPU_CTRL.FB_CLEA= R_DIS */ +XEN_CPUFEATURE(RRSBA, 16*32+19) /*!A Restricted RSB Alternati= ve */ +XEN_CPUFEATURE(BHI_NO, 16*32+20) /*A No Branch History Inject= ion */ +XEN_CPUFEATURE(XAPIC_STATUS, 16*32+21) /* MSR_XAPIC_DISABLE_STATUS= */ +XEN_CPUFEATURE(OVRCLK_STATUS, 16*32+23) /* MSR_OVERCLOCKING_STATUS = */ +XEN_CPUFEATURE(PBRSB_NO, 16*32+24) /*A No Post-Barrier RSB pred= ictions */ =20 /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.edx, word 17 */ =20 diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index 86d00bb3c273..f28ff708a2fc 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -325,6 +325,9 @@ def crunch_numbers(state): =20 # In principle the TSXLDTRK insns could also be considered indepen= dent. RTM: [TSXLDTRK], + + # The ARCH_CAPS CPUID bit enumerates the availability of the whole= register. + ARCH_CAPS: list(range(RDCL_NO, RDCL_NO + 64)), } =20 deep_features =3D tuple(sorted(deps.keys())) --=20 2.30.2