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d="scan'208";a="111689032" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 3/4] x86/tsx: Remove opencoded MSR_ARCH_CAPS check Date: Tue, 16 May 2023 15:53:33 +0100 Message-ID: <20230516145334.1271347-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230516145334.1271347-1-andrew.cooper3@citrix.com> References: <20230516145334.1271347-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1684248864002100005 The current cpu_has_tsx_ctrl tristate is serving double pupose; to signal t= he first pass through tsx_init(), and the availability of MSR_TSX_CTRL. Drop the variable, replacing it with a once boolean, and altering cpu_has_tsx_ctrl to come out of the feature information. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/include/asm/processor.h | 2 +- xen/arch/x86/tsx.c | 13 ++++++++----- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/a= sm/cpufeature.h index 8446f98625f7..deca5bfc2629 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -185,6 +185,7 @@ static inline bool boot_cpu_has(unsigned int feat) =20 /* MSR_ARCH_CAPS 10A */ #define cpu_has_if_pschange_mc_no boot_cpu_has(X86_FEATURE_IF_PSCHANGE_MC_= NO) +#define cpu_has_tsx_ctrl boot_cpu_has(X86_FEATURE_TSX_CTRL) =20 /* Synthesized. */ #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/as= m/processor.h index 0eaa2c3094d0..f983ff501d95 100644 --- a/xen/arch/x86/include/asm/processor.h +++ b/xen/arch/x86/include/asm/processor.h @@ -535,7 +535,7 @@ static inline uint8_t get_cpu_family(uint32_t raw, uint= 8_t *model, return fam; } =20 -extern int8_t opt_tsx, cpu_has_tsx_ctrl; +extern int8_t opt_tsx; extern bool rtm_disabled; void tsx_init(void); =20 diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c index 41b6092cfe16..fc199815994d 100644 --- a/xen/arch/x86/tsx.c +++ b/xen/arch/x86/tsx.c @@ -19,7 +19,6 @@ * controlling TSX behaviour, and where TSX isn't force-disabled by firmwa= re. */ int8_t __read_mostly opt_tsx =3D -1; -int8_t __read_mostly cpu_has_tsx_ctrl =3D -1; bool __read_mostly rtm_disabled; =20 static int __init cf_check parse_tsx(const char *s) @@ -37,24 +36,28 @@ custom_param("tsx", parse_tsx); =20 void tsx_init(void) { + static bool __read_mostly once; + /* * This function is first called between microcode being loaded, and C= PUID * being scanned generally. Read into boot_cpu_data.x86_capability[] = for * the cpu_has_* bits we care about using here. */ - if ( unlikely(cpu_has_tsx_ctrl < 0) ) + if ( unlikely(!once) ) { - uint64_t caps =3D 0; bool has_rtm_always_abort; =20 + once =3D true; + if ( boot_cpu_data.cpuid_level >=3D 7 ) boot_cpu_data.x86_capability[FEATURESET_7d0] =3D cpuid_count_edx(7, 0); =20 if ( cpu_has_arch_caps ) - rdmsrl(MSR_ARCH_CAPABILITIES, caps); + rdmsr(MSR_ARCH_CAPABILITIES, + boot_cpu_data.x86_capability[FEATURESET_10Al], + boot_cpu_data.x86_capability[FEATURESET_10Ah]); =20 - cpu_has_tsx_ctrl =3D !!(caps & ARCH_CAPS_TSX_CTRL); has_rtm_always_abort =3D cpu_has_rtm_always_abort; =20 if ( cpu_has_tsx_ctrl && cpu_has_srbds_ctrl ) --=20 2.30.2