From nobody Sat May 18 07:09:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1684248854; cv=none; d=zohomail.com; s=zohoarc; b=h7fBkEA78fBImxwewLzgmyYQcVNPsffnktWYP9WZ6evHG7dUnqYzOu4qaE2LmmdAf2uap5WMh/yxnycVLsBm5fWRe9TM7gvCPvIyUziZc8zKbCKSSkPbuQtA3jEF4jaw8JN2A/JeYznPvk2ZNIXx8+uTVrMr/fj2Jq/ZEag4F/I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684248854; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CuN+1sQRC/72AdfMCcHk80XroOdWWTS6o8GiPqXmGzQ=; b=ES2KXW7y8rTLG+T5TcG/T9hPqkc+TWmbHSM2Ruh0J4i1Y5iktApiN7x1y6FUd0ZHnZfpkhzMHTnEOLQbYrP03AtTmj/6fb3OepiXY9xRm+/DK7yFe3SzTz4/IUug9Y2/OYNlABf1iEHQYvjjV4xCjdeb1WwIgULE13nbQ6Ckj98= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1684248854031160.1718701898593; Tue, 16 May 2023 07:54:14 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.535262.832948 (Exim 4.92) (envelope-from ) id 1pyw3h-0006Sa-D2; Tue, 16 May 2023 14:53:49 +0000 Received: by outflank-mailman (output) from mailman id 535262.832948; Tue, 16 May 2023 14:53:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pyw3h-0006S2-83; Tue, 16 May 2023 14:53:49 +0000 Received: by outflank-mailman (input) for mailman id 535262; Tue, 16 May 2023 14:53:48 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pyw3g-0006OC-DR for xen-devel@lists.xenproject.org; Tue, 16 May 2023 14:53:48 +0000 Received: from esa2.hc3370-68.iphmx.com (esa2.hc3370-68.iphmx.com [216.71.145.153]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 745f770e-f3f9-11ed-b229-6b7b168915f2; Tue, 16 May 2023 16:53:46 +0200 (CEST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 745f770e-f3f9-11ed-b229-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1684248825; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nyQur+30ZM6XscWFa3iBiYiEbv5nHeYpGVnr0FExeKQ=; b=VSFv6Z+6ku77nlo+gSIF+uvMIjQD5fKGuo89Oz6Z/p/fsGeEFtMU8fVm VmxTHFSIpTwyZ03W5i1bx4Z+m4is51H6MQHH5ywC+UgqnraOTf/ejMDpm b5+vNtjRvkp/bsb4kriQRPoM0nsXpy77GZPDCHhB4mGedk4PjfPCY9BY9 I=; Authentication-Results: esa2.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none X-SBRS: 4.0 X-MesageID: 109117764 X-Ironport-Server: esa2.hc3370-68.iphmx.com X-Remote-IP: 162.221.156.123 X-Policy: $RELAYED IronPort-Data: A9a23:QB58IK71qn8wGRrfY7ImjgxRtDHHchMFZxGqfqrLsTDasY5as4F+v jcbD2iHOqmKNjHyc412PIrnoE9T6p7WndJgSAU4rHxhHi5G8cbLO4+Ufxz6V8+wwm8vb2o8t plDNYOQRCwQZiWBzvt4GuG59RGQ7YnRGvynTraCYnsrLeNdYH9JoQp5nOIkiZJfj9G8Agec0 fv/uMSaM1K+s9JOGjt8B5mr9VU+7ZwehBtC5gZlPa0S4geE/5UoJMl3yZ+ZfiOQrrZ8RoZWd 86bpJml82XQ+QsaC9/Nut4XpWVTH9Y+lSDX4pZnc/DKbipq/0Te4Y5iXBYoUm9Fii3hojxE4 I4lWapc6+seFvakdOw1C3G0GszlVEFM0OevzXOX6aR/w6BaGpdFLjoH4EweZOUlFuhL7W5m3 uIFAzcNPlO4rO+omI2DW9tn1+t7BZy+VG8fkikIITDxCP8nRdbIQrnQ5M8e1zA17ixMNa+AP YxDM2MpNUmeJUQVYT/7C7pn9AusrlD5fydVtxS+oq0v7nKI5AdwzKLsIJzefdniqcB9xx7J/ zuZoDqlav0cHIez1Weo7FGoveCMpjrEe4U8G/6WrfE/1TV/wURMUUZLBDNXu8KRlUqWS99Zb UsO9UIGvaU0sUCmUNT5dxm5u2Kf+A4RXcJKFO834x3LzbDbiy67LGUZSj9KaPQ9qdQ7Azct0 ze0c8jBXGI19ufPEDTEq+nS9GnpUcQIEYMcTQQaUCAC44mgm6o+kErwdsdRG/+a1vSgTFkc3 Au2hCQ5grwSi+sC2KO64U3LjlqQm3TZcuImzl6JBzz4t2uVcKbgPtX1sgaDsZ6sOa7DFjG8U G44d99yBQzkJbWEj2SzTeoEB9lFDN7VYWSH0TaD83TMnglBGkJPn6gKuFmSx28zaK7onAMFh 2eN0T69HLcJYBOXgVZfOupd8fgCw6n6DsjCXfvJdNdIaZUZXFbZrH03OhPOjjmxzxJEfUQD1 XCzIK6R4YsyU/w7nFJauc9HuVPU+szO7TyKHs2qp/hW+bGfeGSUWd84Dbd6VchgtPnsiFyMo 75i2z6il003vBvWPnOGrub+7DkicRAGOHwBg5IHKbPTflU/QwnMyZb5mNscRmCspIwN/s+gw 513chYwJIbX7ZEfFTi3Vw== IronPort-HdrOrdr: A9a23:VvZXy6HQsft+I1SQpLqFUpHXdLJyesId70hD6qkvc3Jom52j+P xGws526fatskdsZJkh8erwXJVoMkmsiqKdgLNhcItKOTOGhILGFvAb0WKP+UyDJ8S6zJ8h6U 4CSdkzNDSTNykAsS+S2mDReLxMoKjlzEnrv5al854Ed3AtV0gK1XYfNu/vKDwOeOAwP+teKH Pz3Lsjm9OIQwVZUu2LQl0+G8TTrdzCk5zrJTQcAQQ81QWIhTS0rJbnDhmxxH4lInJy6IZn1V KAvx3y562lvf3+4ATbzXXv45Nfn8ak4sdfBfaLltMeJlzX+0aVjcVaKv6/VQIO0aSSAWUR4Z 3xSiIbToZOAzS4RBD6nfKi4Xim7N9k0Q6d9bbRuwqTnSW+fkNjN+NxwbtQaAHU5ncgp9dh3q Ns2FuDu55WFx/b9R6NvuQgHisa5nacsD4sl/UegGdYVpZbYLhNrZYH9EcQC5sYGjnmgbpXWN WGo/uskMq+XGnqGUwxhFMfieCETzA2BFOLU0ICssua33xfm2141VIRwIgakm0b/JwwRpFY76 CcW54Y3o1mX4sTd+ZwFe0BScy4BijERg/NKnubJRDiGLscM3zAppbr6PE+5f2sepYP0Jwu8a 6xG2+wdVRCDH4GJff+qaGjqCq9M1lVdQ6duP1j2w== X-Talos-CUID: =?us-ascii?q?9a23=3AcNYIIWhBew4ACRNy0Gp+98n0PzJuWWPA53DQcwy?= =?us-ascii?q?DImt3EIKtWG2bqYw8up87?= X-Talos-MUID: =?us-ascii?q?9a23=3A1sEVUQ7S5rIBv2XxGS2G2UO2xowzz7jzJV4ula4?= =?us-ascii?q?J+PKdCg93FTjeom+4F9o=3D?= X-IronPort-AV: E=Sophos;i="5.99,278,1677560400"; d="scan'208";a="109117764" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 1/4] x86/cpufeature: Rework {boot_,}cpu_has() Date: Tue, 16 May 2023 15:53:31 +0100 Message-ID: <20230516145334.1271347-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230516145334.1271347-1-andrew.cooper3@citrix.com> References: <20230516145334.1271347-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1684248854840100003 One area where Xen deviates from Linux is that test_bit() forces a volatile read. This leads to poor code generation, because the optimiser cannot mer= ge bit operations on the same word. Drop the use of test_bit(), and write the expressions in regular C. This removes the include of bitops.h (which is a frequent source of header tangles), and it offers the optimiser far more flexibility. Bloat-o-meter reports a net change of: add/remove: 0/0 grow/shrink: 21/87 up/down: 641/-2751 (-2110) with half of that in x86_emulate() alone. vmx_ctxt_switch_to() seems to be the fastpath with the greatest delta at -24, where the optimiser has successfully removed the branch hidden in cpu_has_msr_tsc_aux. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- xen/arch/x86/include/asm/cpufeature.h | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/a= sm/cpufeature.h index 4140ec0938b2..4f827cc6ff91 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -7,6 +7,7 @@ #define __ASM_I386_CPUFEATURE_H =20 #include +#include #include =20 #define cpufeat_word(idx) ((idx) / 32) @@ -17,7 +18,6 @@ #define X86_FEATURE_ALWAYS X86_FEATURE_LM =20 #ifndef __ASSEMBLY__ -#include =20 struct cpuinfo_x86 { unsigned char x86; /* CPU family */ @@ -43,8 +43,15 @@ struct cpuinfo_x86 { =20 extern struct cpuinfo_x86 boot_cpu_data; =20 -#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) -#define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) +static inline bool cpu_has(const struct cpuinfo_x86 *info, unsigned int fe= at) +{ + return info->x86_capability[cpufeat_word(feat)] & cpufeat_mask(feat); +} + +static inline bool boot_cpu_has(unsigned int feat) +{ + return cpu_has(&boot_cpu_data, feat); +} =20 #define CPUID_PM_LEAF 6 #define CPUID6_ECX_APERFMPERF_CAPABILITY 0x1 base-commit: 8f9c8274a4e3e860bd777269cb2c91971e9fa69e prerequisite-patch-id: ceeba7d5ab9498cb188e5012953c7e8c9a86347d prerequisite-patch-id: c0957b9e1157ae6eb8de973c96716fd02587c486 prerequisite-patch-id: d2574bba15748cd021e5b33fa50e6cadc38863b6 prerequisite-patch-id: 0f66cd4287ffdc06f24dc01c7d26fb428f3e8c09 prerequisite-patch-id: a585f61b546ff96be3624ff253f8100b2f465de6 prerequisite-patch-id: 54551cdefaca083b4a4b97528d27d0f3dc9753ee prerequisite-patch-id: 051423463e4a34728ab524f03e801e7103777684 --=20 2.30.2 From nobody Sat May 18 07:09:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1684248854; cv=none; d=zohomail.com; s=zohoarc; b=gmPrDEKlqb6s0aZcBL8At+A1xYxQUBo2hXj8n5LMrg/n+jtALzKXLfax8PrpMDpwvVcjj7bemgZg3cH/CKRVeMh44NqSWQdHHXa28uk1em0liVzb50z/C18EmfrLBjOAazutXR0A9X1gy0r8FPutlQTPLVdP94wx1k4lG4YK/fQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684248854; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=az8nWlXpRMQAznH0DXlyRuNHYAtX8qCcsK3uGBSm/Bg=; b=FYlG8KuspeGOWT0s6DXfQuUcufAWirEDJ6TiYqeg+Y7qvfhOia1Fq7tYqqAjYZLQqD6vrQqyYte7RH2EKysznJOKM/brtP9fggiFDKG4+PkdYmfl4+jzTAQsHLQSSXR3elxVVyEJVFhKKScJBNDrtO1Wlt/6JRZ7tNKwLuLkUDM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1684248854313259.342100746559; Tue, 16 May 2023 07:54:14 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.535261.832944 (Exim 4.92) (envelope-from ) id 1pyw3h-0006P7-3i; Tue, 16 May 2023 14:53:49 +0000 Received: by outflank-mailman (output) from mailman id 535261.832944; Tue, 16 May 2023 14:53:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pyw3g-0006P0-Vy; Tue, 16 May 2023 14:53:48 +0000 Received: by outflank-mailman (input) for mailman id 535261; Tue, 16 May 2023 14:53:47 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pyw3f-0006OC-Nj for xen-devel@lists.xenproject.org; Tue, 16 May 2023 14:53:47 +0000 Received: from esa3.hc3370-68.iphmx.com (esa3.hc3370-68.iphmx.com [216.71.145.155]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 74c30a6d-f3f9-11ed-b229-6b7b168915f2; Tue, 16 May 2023 16:53:46 +0200 (CEST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 74c30a6d-f3f9-11ed-b229-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1684248826; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LZA9DiPzTWBX0eSgS7FnHPS/B/27DbsY3IexopoDr6Y=; b=AvgpE37ZbnVokSWYKFJ2qe26tIkMQHvnOeYMHZoff/W+J9akpAm8iOO3 0uQAFz8o1uX1fdLKhW1FjS1hOZTtgV+IpDxAWKuUPp+a84H66puOa7zzP 6uOPBH3pU8womLd4iRYUpvkuZ9gdPUYsz+TAwqiKGIkgRKTiVCz5Gr6Dm I=; Authentication-Results: esa3.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none X-SBRS: 4.0 X-MesageID: 109243519 X-Ironport-Server: esa3.hc3370-68.iphmx.com X-Remote-IP: 162.221.156.123 X-Policy: $RELAYED IronPort-Data: A9a23:hHoczq9imQHx+vMaQrs3DrUDv36TJUtcMsCJ2f8bNWPcYEJGY0x3n zAdWmGDb/2LZzH0fdtxbY++9E0EuJ/UndRkTQpsrSA8E34SpcT7XtnIdU2Y0wF+jCHgZBk+s 5hBMImowOQcFCK0SsKFa+C5xZVE/fjUAOG6UKicYXoZqTZMEE8JkQhkl/MynrlmiN24BxLlk d7pqojUNUTNNwRcawr40Ire7kI+1BjOkGlA5AdmOKkV5AW2e0Q9V/rzG4ngdxMUfaEMdgKKb 76r5K20+Grf4yAsBruN+losWhRXKlJ6FVHmZkt+A8BOsDAbzsAB+v9T2M4nQVVWk120c+VZk 72hg3ASpTABZcUgkMxFO/VR/roX0aduoNcrKlDn2SCfItGvn9IBDJyCAWlvVbD09NqbDklPy v4FGD8hRCupgtKsnunmUvIrq5QseZyD0IM34hmMzBncBPciB5vCX7/L9ZlT2zJYasJmRKiEI ZBDMHw2MUqGOkcUUrsUIMtWcOOAr3/zaTBH7nmSorI6+TP7xw1tyrn9dtHSf7RmQO0MxhfC+ jmbpjWR7hcyaeCR0hTdzHyWhrHEuQ3pSp0KSa2y36s/6LGU7jNKU0BHPbehmtGmjmauVtQZL FYbkgIssK508kWoR9v8WhSQoXiYsxpaUN1Ve8U55R+MzOzI4g+fLmkCUjNFLtchsaceVTEsk 1OEgd7tLThuq6GOD2KQ8K+OqjG/MjRTKnUNDQcmZwYY59jooKkokwnCCN1kFcaIYsbdQG+qh WrQ9W5n2utV1JRQv0mmwbzZqzOTpIX5QSIf3S/Sbnj7tV5hf8mIN4P9vDA38s18BIqeS1CAu l0NlM6f8P0CAPmxqcCdfAkeNOr3vqjYaVUwlXYqRsB8rGr1pxZPaKgKuFlDyFFV3tHokNMDS Gvaoktv6ZBaJxNGhocnMtvqW6zGIUUNfOkJt8w4jPIUOvCdlyfdpkmCgHJ8OEiz+HXAaYllZ f+mnT+EVB7285hPwjusXPs62rQ23C04zm67bcmln0j+jufANSfJFu1t3L6yggcRvcu5TPj9q Y4DZ6NmNT0FOAEBXsUn2dFKdg1bRZTKLZv3t9ZWZoa+H+aSI0l4U6W56ep4K+RYc1F9yr+gE oeVBhUJlzISRBTvdW23V5yUQO2/Assv8S1iZkTB/z+AghAeXGpm149HH7NfQFXt3LULISJcJ xXdR/i9Pw== IronPort-HdrOrdr: A9a23:u8L0iKqLY652xS2w1VZxeF0aV5uRL9V00zEX/kB9WHVpm5Oj+f xGzc516farslossSkb6Ky90KnpewK5yXcH2/hvAV7CZniqhILMFuBfBOTZskXd8kHFh4xgPO JbAtVD4b7LfBRHZKTBkXKF+r8bqbHtms3J9ITjJjVWPHtXgslbnkFE422gYypLrXx9dOME/e 2nl6x6TlSbCBEqh+2AdzY4dtmGg+eOuIPtYBYACRJiwhKJlymU5LnzFAXd9gsCUhtUqI1SsF Ttokjc3OGOovu7whjT2yv49JJNgubszdNFGYilltUVEDPxkQylDb4RG4Fq/QpF491H2mxa1e UkkC1Qe/ib3kmhPF1c5nPWqkfdOXgVmjjfIBSj8AXeSITCNUMH4ox69NpkWyqc0kI7pt1w7a NR2X6WtrxRNAjNmCTm68KgbWAyqqP8mwtTrccDy3NYSocQc7lXsMgW+15UCo4JGGbg5JkgC/ QGNrCV2B/4SyLvU5n1hBgY/DWXZAV7Ij6WBkwZ/sCF2Tlfm350i0Me2cwEh38FsJYwUYNN6e jIOrlh0OgmdL5dUYttQOMaBcenAG3ERhzBdGqUPFT8DakCf3bAsYT+7rk57PyjPJYI0Jwxkp LcV04wjx94R6svM7z44HRmyGG5fIzmZ0Wf9ih33ekKhoHB X-Talos-CUID: =?us-ascii?q?9a23=3ANY0Q0mjmxrZpR5c3un12WD3YOTJuc0Lf0UffD2W?= =?us-ascii?q?DI2NZUuPOFEeLv440nJ87?= X-Talos-MUID: =?us-ascii?q?9a23=3AOcCANg8BF75ysaasesJnxF6Qf5pU7b+AUH4Dq5V?= =?us-ascii?q?YsO2qJz5vI2qNhh3iFw=3D=3D?= X-IronPort-AV: E=Sophos;i="5.99,278,1677560400"; d="scan'208";a="109243519" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Jun Nakajima , Kevin Tian Subject: [PATCH 2/4] x86/vtx: Remove opencoded MSR_ARCH_CAPS check Date: Tue, 16 May 2023 15:53:32 +0100 Message-ID: <20230516145334.1271347-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230516145334.1271347-1-andrew.cooper3@citrix.com> References: <20230516145334.1271347-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1684248854806100001 MSR_ARCH_CAPS data is now included in featureset information. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Jun Nakajima CC: Kevin Tian --- xen/arch/x86/hvm/vmx/vmx.c | 8 ++------ xen/arch/x86/include/asm/cpufeature.h | 3 +++ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 096c69251d58..9dc16d0cc6b9 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2849,8 +2849,6 @@ static void __init ler_to_fixup_check(void); */ static bool __init has_if_pschange_mc(void) { - uint64_t caps =3D 0; - /* * If we are virtualised, there is nothing we can do. Our EPT tables = are * shadowed by our hypervisor, and not walked by hardware. @@ -2858,10 +2856,8 @@ static bool __init has_if_pschange_mc(void) if ( cpu_has_hypervisor ) return false; =20 - if ( cpu_has_arch_caps ) - rdmsrl(MSR_ARCH_CAPABILITIES, caps); - - if ( caps & ARCH_CAPS_IF_PSCHANGE_MC_NO ) + /* Hardware reports itself as fixed. */ + if ( cpu_has_if_pschange_mc_no ) return false; =20 /* diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/a= sm/cpufeature.h index 4f827cc6ff91..8446f98625f7 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -183,6 +183,9 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_avx_vnni_int8 boot_cpu_has(X86_FEATURE_AVX_VNNI_INT8) #define cpu_has_avx_ne_convert boot_cpu_has(X86_FEATURE_AVX_NE_CONVERT) =20 +/* MSR_ARCH_CAPS 10A */ +#define cpu_has_if_pschange_mc_no boot_cpu_has(X86_FEATURE_IF_PSCHANGE_MC_= NO) + /* Synthesized. */ #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) #define cpu_has_cpuid_faulting boot_cpu_has(X86_FEATURE_CPUID_FAULTING) --=20 2.30.2 From nobody Sat May 18 07:09:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1684248862; cv=none; d=zohomail.com; s=zohoarc; b=jI9KbChONcP4UjT1XkDXZtkPGGkUeWu6HftPzu4RuD4HP7eGKc+uaj8yF2oysVYibzjz8cUXMiUKF0dUpujgqNgStZKCk2TdCPdvrCMdfM2QtHHFFgLwqkT0CymJThaTh3kDNt4WEC9rhGFlWxrnS3+NbzMw7zCkateXnK3iC2g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684248862; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OziYH5lEwRKpJsLuMhCOthBWHigO13aJANJzHI6Birg=; b=ksuZlGX2pI+CqE124iQl8qrHJtBzDiBGXohTTlxIP4HkNQmo1BX8Rhb/Ogt0H1nKTwnFf3nDB1egg9p3+uJLHx5IZC/zqAmPnWUcnaN+Ahjos/Oh46C7s/NPXM6Y+wKU+jmmKW/lPITxd1eQ/IHQiiCOtQpdbYlH1+u3MzioJu0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 168424886296377.79329235817715; Tue, 16 May 2023 07:54:22 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.535266.832980 (Exim 4.92) (envelope-from ) id 1pyw3q-0007Oi-G4; Tue, 16 May 2023 14:53:58 +0000 Received: by outflank-mailman (output) from mailman id 535266.832980; Tue, 16 May 2023 14:53:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pyw3q-0007Ny-7K; Tue, 16 May 2023 14:53:58 +0000 Received: by outflank-mailman (input) for mailman id 535266; Tue, 16 May 2023 14:53:56 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pyw3o-00067V-Dw for xen-devel@lists.xenproject.org; Tue, 16 May 2023 14:53:56 +0000 Received: from esa4.hc3370-68.iphmx.com (esa4.hc3370-68.iphmx.com [216.71.155.144]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 799ec1ce-f3f9-11ed-8611-37d641c3527e; Tue, 16 May 2023 16:53:54 +0200 (CEST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 799ec1ce-f3f9-11ed-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1684248834; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lMkiMk+JiUBw0hNgilS4qSHGS05jFL3O36UzQf8lnjo=; b=Z151AEIeZh+lgWZLiUIM5oxx1Z1Y6Jiq2q3620FydbOlm5KvHcC/v/cv zq3v6rj3K1jhuSKQXI1Mzuq0sMQUcehBqNbB/ZrKRyzi5hko1+aYvtNaF DoRsJFU5dszRLjYQ3PdXsPHQuGj0upCrN3dAO6LOID+hy7r9gwew+vbFV s=; Authentication-Results: esa4.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none X-SBRS: 4.0 X-MesageID: 111689032 X-Ironport-Server: esa4.hc3370-68.iphmx.com X-Remote-IP: 162.221.156.123 X-Policy: $RELAYED IronPort-Data: A9a23:jULSca17vEt4G5MuofbD5dpxkn2cJEfYwER7XKvMYLTBsI5bp2MOy GtNCm2EM/2CN2r3Loh2boqy80xUsZKAmoM1QAdrpC1hF35El5HIVI+TRqvS04F+DeWYFR46s J9OAjXkBJppJpMJjk71atANlVEliefTAOK6ULWeUsxIbVcMYD87jh5+kPIOjIdtgNyoayuAo tq3qMDEULOf82cc3lk8tuTS+XuDgNyo4GlD5gFnO6gR1LPjvyJ94Kw3dPnZw0TQGuG4LsbiL 87fwbew+H/u/htFIrtJRZ6iLyXm6paLVeS/oiI+t5qK23CulQRrukoPD9IOaF8/ttm8t4sZJ OOhF3CHYVxB0qXkwIzxWvTDes10FfUuFLTveRBTvSEPpqFvnrSFL/hGVSkL0YMkFulfLGh3/ tUIJwg0Qk6fprOX6oKgT8tgmZF2RCXrFNt3VnBIyDjYCbAtQIzZQrWM7thdtNsyrpkQR7CEP ZNfMGcxKk2aOHWjOX9OYH46tM6uimPybHtzr1WNqLBsy2PS0BZwwP7mN9+9ltmiHJwMwBbJ/ jmcl4j/KkE4JNaa6yufyF72jcL/mDP4Qp4OTKLto5aGh3XMnzdOWXX6T2CTsfS/z0KzRd9bA 0gV4TY167g/8lSxSdvwVAH+p2SL1jY+cddNF+wx6CmW17HZpQ2eAwAsUTppeNEg8sgsSlQXO kShxo2zQ2Y16fvMFCzbr+3Pxd+vBcQLBUILXCQtXQQ92vW9vKBirzj/VdNBHLHg27UZBgrM6 zyNqSE/gZAagsgKy7i38Dj7vt68mnTaZlVrv1uKBwpJ+is8Pdf4PNLwtTA3+N4adO6kok+9U G/ociR0xMQHFtmzmSOEW43h95n5tq/eYFUwbbOCdqTNFghBGVb5Jei8Axkkfi+F1/ronhe3C HI/QSsLuPdu0IKCNMebmb6ZBcUw1rTHHt/4TP3SZdcmSsEvJFPeo3wwNBfMgDqFfK0QfUYXa P+mnTuEVy5GWcyLMhLsLwvi7VPb7n9nnj6CLXwK5x+mzaCfdBaodFvxC3PXNrpRxPrd8G3oH yN3a5PiJ+N3DLevPUE6MOc7cTg3EJTMLc6m9JEHKrHaeWKL2ggJUpfs/F/oQKQ994w9qwsC1 ijVtpNwoLYnuUD6FA== IronPort-HdrOrdr: A9a23:LJl+wKjSpoGFeaLJsqaEaHZe7HBQX9J23DAbv31ZSRFFG/FwyP rCoB1L73XJYWgqM03IwerwXpVoMkmsjKKdgLNhdItKOTOLhILGFvAH0WKP+Vzd8k7Fh6ZgPM VbAs9D4bTLZDAU4/oSizPIcOrIteP3lZxA8t2urUuFIzsLV4hQqyNCTiqLGEx/QwdLQbI/CZ qn/8JC4xawZHgNacy/J38dG8zOvcfCmp7KaQMPQ0dP0njFsRqYrJrBVzSI1BYXVD1ChZ8k7G j+igT8oomzrv2hzRfY9mnLq7BbgsHoxNdvDNGFzuIVNjLvoAC1Y5kJYczIgBkF5MWUrHo6mt jFpBkte+5p7WnKQ22zqRzxnyH9zTcH8RbZuBOlqEqmhfa8aCMxCsJHi44cWADe8VAcsNZ117 8O936FtqBQEQjLkE3Glpf1vlBR5wSJSEgZ4K4uZk9kIMgjgXhq3M4iFXZuYdY99eTBmcUa+a dVfYXhDb1tACunhjjizxJSKZqXLzkO9169MzU/UsD56UktoFlpi0Qf38ARhXEG6dY0TIRF/f 3NNuBymKhJVdJ+V9MIOA4te7rENoX2e2O4DEuCZVD8UK0XMXPErJD6pL0z+eGxYZQNiJ8/go 7IXl9UvXM7PxuGM7z54LRbthTWBGmtVzXkzc9To5B/p73nXbLudSmOUkonncesq+gWRsfbR/ GwMpRLBOKLFxqYJa9ZmwnlH5VCI3gXV8MY/t49RlKVu8rObpbns+TKGcyjV4YF0QxUKl8XLk FzIgQbfv8wknxDckWI/yT5SjfqZlH1+452HezT4/UTobJ9R7Fxjg== X-Talos-CUID: =?us-ascii?q?9a23=3ARgzM4mro4N4SQVM0cCe2GszmUe0sS3b03HjoGmP?= =?us-ascii?q?mFUc4aZelUlqy9Lwxxg=3D=3D?= X-Talos-MUID: 9a23:O88yugtWlovu7NLUDs2n1BNyPsJK8r6UJBoGvKUDq8qeKTAoJGLI X-IronPort-AV: E=Sophos;i="5.99,278,1677560400"; d="scan'208";a="111689032" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 3/4] x86/tsx: Remove opencoded MSR_ARCH_CAPS check Date: Tue, 16 May 2023 15:53:33 +0100 Message-ID: <20230516145334.1271347-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230516145334.1271347-1-andrew.cooper3@citrix.com> References: <20230516145334.1271347-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1684248864002100005 The current cpu_has_tsx_ctrl tristate is serving double pupose; to signal t= he first pass through tsx_init(), and the availability of MSR_TSX_CTRL. Drop the variable, replacing it with a once boolean, and altering cpu_has_tsx_ctrl to come out of the feature information. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/include/asm/processor.h | 2 +- xen/arch/x86/tsx.c | 13 ++++++++----- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/a= sm/cpufeature.h index 8446f98625f7..deca5bfc2629 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -185,6 +185,7 @@ static inline bool boot_cpu_has(unsigned int feat) =20 /* MSR_ARCH_CAPS 10A */ #define cpu_has_if_pschange_mc_no boot_cpu_has(X86_FEATURE_IF_PSCHANGE_MC_= NO) +#define cpu_has_tsx_ctrl boot_cpu_has(X86_FEATURE_TSX_CTRL) =20 /* Synthesized. */ #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/as= m/processor.h index 0eaa2c3094d0..f983ff501d95 100644 --- a/xen/arch/x86/include/asm/processor.h +++ b/xen/arch/x86/include/asm/processor.h @@ -535,7 +535,7 @@ static inline uint8_t get_cpu_family(uint32_t raw, uint= 8_t *model, return fam; } =20 -extern int8_t opt_tsx, cpu_has_tsx_ctrl; +extern int8_t opt_tsx; extern bool rtm_disabled; void tsx_init(void); =20 diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c index 41b6092cfe16..fc199815994d 100644 --- a/xen/arch/x86/tsx.c +++ b/xen/arch/x86/tsx.c @@ -19,7 +19,6 @@ * controlling TSX behaviour, and where TSX isn't force-disabled by firmwa= re. */ int8_t __read_mostly opt_tsx =3D -1; -int8_t __read_mostly cpu_has_tsx_ctrl =3D -1; bool __read_mostly rtm_disabled; =20 static int __init cf_check parse_tsx(const char *s) @@ -37,24 +36,28 @@ custom_param("tsx", parse_tsx); =20 void tsx_init(void) { + static bool __read_mostly once; + /* * This function is first called between microcode being loaded, and C= PUID * being scanned generally. Read into boot_cpu_data.x86_capability[] = for * the cpu_has_* bits we care about using here. */ - if ( unlikely(cpu_has_tsx_ctrl < 0) ) + if ( unlikely(!once) ) { - uint64_t caps =3D 0; bool has_rtm_always_abort; =20 + once =3D true; + if ( boot_cpu_data.cpuid_level >=3D 7 ) boot_cpu_data.x86_capability[FEATURESET_7d0] =3D cpuid_count_edx(7, 0); =20 if ( cpu_has_arch_caps ) - rdmsrl(MSR_ARCH_CAPABILITIES, caps); + rdmsr(MSR_ARCH_CAPABILITIES, + boot_cpu_data.x86_capability[FEATURESET_10Al], + boot_cpu_data.x86_capability[FEATURESET_10Ah]); =20 - cpu_has_tsx_ctrl =3D !!(caps & ARCH_CAPS_TSX_CTRL); has_rtm_always_abort =3D cpu_has_rtm_always_abort; =20 if ( cpu_has_tsx_ctrl && cpu_has_srbds_ctrl ) --=20 2.30.2 From nobody Sat May 18 07:09:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1684248858; cv=none; d=zohomail.com; s=zohoarc; b=Ed49/6fjk8tUNYl0dRmVW7AFVB/Voxqgr+RnvkDZxEg2jIAS04p5KE9EfhgFsjr0IwzCFuQPslcqkWSj5bYqk3xJUvO0hZWajZoM5xXkcG29GlcxBOrARp2SZKB8xcOqad8tVhyuqsmEMhj7dcZjOlzs17PfQ2xCiI0+rXZFFc8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684248858; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+NaysSjsjTPyVOz9fX+Zp15I+8HpatX1zxGj0haoeMg=; b=nixTLEf/avQ1JtEToMUrY6PGN3Lx4VLX28Tw6it6whxmDa2TKjsoJ4gNqDunwd8D1xq8b1NcPDvWlaOpwCdTfK8nrJzeVN2UZ19p7WuX0e9j9gTeNlo7F4DSOpwbWr8YRn8tWITcyiSZPJOBMbD8UD2QUjRa2qlX4ZLqwGeHnzc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1684248858903988.8616753743961; Tue, 16 May 2023 07:54:18 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.535264.832964 (Exim 4.92) (envelope-from ) id 1pyw3n-00070G-PK; Tue, 16 May 2023 14:53:55 +0000 Received: by outflank-mailman (output) from mailman id 535264.832964; Tue, 16 May 2023 14:53:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pyw3n-000709-LT; Tue, 16 May 2023 14:53:55 +0000 Received: by outflank-mailman (input) for mailman id 535264; Tue, 16 May 2023 14:53:54 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pyw3m-00067V-3y for xen-devel@lists.xenproject.org; Tue, 16 May 2023 14:53:54 +0000 Received: from esa4.hc3370-68.iphmx.com (esa4.hc3370-68.iphmx.com [216.71.155.144]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 77c9e0d8-f3f9-11ed-8611-37d641c3527e; Tue, 16 May 2023 16:53:51 +0200 (CEST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 77c9e0d8-f3f9-11ed-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1684248831; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GMlRcLDKg4s3arvBRJ23Or4PyYQ1A2vHuJYymPBgPdQ=; b=g5d17d/MDvxEdSn4VBia7e5xijAqo6pfM8Qztt3gQzSUG5ejSOie1jHV z2m33jhDv4f30j0JWu98Y7iwkFb+jTH7nH2I8yLQyLCsMxE27GVexr273 JE121N8rHXAWQpGxsq+Si64I9MVLalZ59RVhJSdlmHUQ+1zdTKXblS3/R s=; Authentication-Results: esa4.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none X-SBRS: 4.0 X-MesageID: 111689025 X-Ironport-Server: esa4.hc3370-68.iphmx.com X-Remote-IP: 162.221.156.123 X-Policy: $RELAYED IronPort-Data: A9a23:Gf2vtK5WG0SBXkUkBV+1PQxRtDHHchMFZxGqfqrLsTDasY5as4F+v mBJCGzXaaqOMTCnL4siYdjlpkoHup/cmNVnQARlqSk9Hi5G8cbLO4+Ufxz6V8+wwm8vb2o8t plDNYOQRCwQZiWBzvt4GuG59RGQ7YnRGvynTraCYnsrLeNdYH9JoQp5nOIkiZJfj9G8Agec0 fv/uMSaM1K+s9JOGjt8B5mr9VU+7ZwehBtC5gZlPa0S4geE/5UoJMl3yZ+ZfiOQrrZ8RoZWd 86bpJml82XQ+QsaC9/Nut4XpWVTH9Y+lSDX4pZnc/DKbipq/0Te4Y5iXBYoUm9Fii3hojxE4 I4lWapc6+seFvakdOw1C3G0GszlVEFM0OevzXOX6aR/w6BaGpdFLjoH4EweZOUlFuhL7W5m/ /VEMj8jTxm/g92v6qLhY8Nuj/4eFZy+VG8fkikIITDxCP8nRdbIQrnQ5M8e1zA17ixMNa+AP YxDM2MpNUmeJUQVYT/7C7pn9AusrlD5fydVtxS+oq0v7nKI5AdwzKLsIJzefdniqcB9xx/B+ DKXpz6kav0cHI2VkCrCwnDxv8/CoifYAaIZE7rn6fE/1TV/wURMUUZLBDNXu8KRlUqWS99Zb UsO9UIGvaU0sUCmUNT5dxm5u2Kf+A4RXcJKFO834x3LzbDbiy67LGUZSj9KaPQ9qdQ7Azct0 ze0c8jBXGI19ufPEDTEq+nS9GnpUcQIEYMcTSUNEREKzfjqnIUMlzjfFP9JEqePs+SgTFkc3 Au2hCQ5grwSi+sC2KO64U3LjlqQm3TZcuImzl6JBzz4t2uVcKbgPtX1sgaDsZ6sOa7DFjG8U G44d99yBQzkJbWEj2SzTeoEB9lFDN7VYWSH0TaD83TMnglBGkJPn6gKuFmSx28zaK7onAMFh 2eN0T69HLcJYBOXgVZfOupd8fgCw6n6DsjCXfvJdNdIaZUZXFbZrH03OhPOjjmxzxJEfUQD1 XCzIK6R4YsyU/w7nFJauc9HuVPU+szO7TyKHs2qp/hW+bGfeGSUWd84Dbd6VchgtPnsiFyMo 75i2z6il003vBvWPnOGrub+7DkicRAGOHwBg5IHKbPTflU/QwnMyZb5mNscRmCspIwN/s+gw 513chUwJIbX7ZEfFTi3Vw== IronPort-HdrOrdr: A9a23:0aSzw6CKhgtfj0blHeiksseALOsnbusQ8zAXPh9KJCC9I/bzqy nxpp8mPEfP+VAssQIb6Km90ci7MDrhHPtOjbX5Uo3SODUO1FHIEGgA1/qr/9SDIVyYygc178 4JHMZD4bbLfDtHZLPBkWyF+qEbsbu6Gc6T5dv2/jNId0VHeqtg5wB2BkKyFVB3fhBPAd4UBY eR/c1OohunYDAyYt6gDncIcuDfr5mT/aiWKyIuNloC0k2jnDmo4Ln1H1yx2QofaSpGxfMP4H XIiAvw44SkqrWexgXH32HewpxKkJ/Ky8dFBuaLls8JQw+cwTqAVcBEYfmvrTo1qOag5BIBi9 /XuSotOMx19jf4Yny1iQGF4Xit7B8er1vZjXOIi3rqpsL0ABggDdBauI5fehzFr2I9odBH1r 5R1W7xjesZMfqAplWy2zH7bWArqqOGmwtgrQfVtQ0cbWIqUs4RkWXYxjIRLH5PJlO/1GltKp gXMCiV3ocsTbrdVQGVgoAn+q3QYpw+cy32OHQqq4ib1SNbk2t+yFZdzMsDnm0Y/JZ4UJVc4f /YW54Y4I2mY/VmH56VPt1xNPefGyjIW1bBIWiSKVPoGOUOPG/MsYf+5PEw6PuxcJIFwZMukN CZOWkow1IaagbrE4mDzZdL+hfCTCG0Wins0NhX49x8tqfnTLTmPCWfQBQlktemof8YHsrHMs zDT65+ErvmNy/jCIxJ1wrxV91bLmQfStQcvpIhV1eHsqvwW/7XXyzgAYbuzZbWYEgZsznEcw c+tRDIVbp9x1HuXGPkix7MXH6oclDj/PtLYdnnw9Q= X-Talos-CUID: =?us-ascii?q?9a23=3Aje1LP2nciwB3gSQFdYCAlOOoDY/XOXfUkG3fDW6?= =?us-ascii?q?xNWJWUZeFE3a6+qpervM7zg=3D=3D?= X-Talos-MUID: 9a23:3Iz8Ogr1Q3nKBlX8FPIez2Bobdcv06bzMWAArpEl4umPMisvJDjI2Q== X-IronPort-AV: E=Sophos;i="5.99,278,1677560400"; d="scan'208";a="111689025" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 4/4] x86/spec-ctrl: Remove opencoded MSR_ARCH_CAPS check Date: Tue, 16 May 2023 15:53:34 +0100 Message-ID: <20230516145334.1271347-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230516145334.1271347-1-andrew.cooper3@citrix.com> References: <20230516145334.1271347-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1684248860821100001 MSR_ARCH_CAPS data is now included in featureset information. Replace opencoded checks with regular feature ones. No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- xen/arch/x86/include/asm/cpufeature.h | 7 ++++ xen/arch/x86/spec_ctrl.c | 56 +++++++++++++-------------- 2 files changed, 33 insertions(+), 30 deletions(-) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/a= sm/cpufeature.h index deca5bfc2629..00a43123ac82 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -184,8 +184,15 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_avx_ne_convert boot_cpu_has(X86_FEATURE_AVX_NE_CONVERT) =20 /* MSR_ARCH_CAPS 10A */ +#define cpu_has_rdcl_no boot_cpu_has(X86_FEATURE_RDCL_NO) +#define cpu_has_eibrs boot_cpu_has(X86_FEATURE_EIBRS) +#define cpu_has_rsba boot_cpu_has(X86_FEATURE_RSBA) +#define cpu_has_skip_l1dfl boot_cpu_has(X86_FEATURE_SKIP_L1DFL) +#define cpu_has_mds_no boot_cpu_has(X86_FEATURE_MDS_NO) #define cpu_has_if_pschange_mc_no boot_cpu_has(X86_FEATURE_IF_PSCHANGE_MC_= NO) #define cpu_has_tsx_ctrl boot_cpu_has(X86_FEATURE_TSX_CTRL) +#define cpu_has_taa_no boot_cpu_has(X86_FEATURE_TAA_NO) +#define cpu_has_fb_clear boot_cpu_has(X86_FEATURE_FB_CLEAR) =20 /* Synthesized. */ #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index f81db2143328..50d467f74cf8 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -282,12 +282,10 @@ custom_param("spec-ctrl", parse_spec_ctrl); int8_t __read_mostly opt_xpti_hwdom =3D -1; int8_t __read_mostly opt_xpti_domu =3D -1; =20 -static __init void xpti_init_default(uint64_t caps) +static __init void xpti_init_default(void) { - if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) - caps =3D ARCH_CAPS_RDCL_NO; - - if ( caps & ARCH_CAPS_RDCL_NO ) + if ( (boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) = || + cpu_has_rdcl_no ) { if ( opt_xpti_hwdom < 0 ) opt_xpti_hwdom =3D 0; @@ -390,9 +388,10 @@ static int __init cf_check parse_pv_l1tf(const char *s) } custom_param("pv-l1tf", parse_pv_l1tf); =20 -static void __init print_details(enum ind_thunk thunk, uint64_t caps) +static void __init print_details(enum ind_thunk thunk) { unsigned int _7d0 =3D 0, _7d2 =3D 0, e8b =3D 0, max =3D 0, tmp; + uint64_t caps =3D 0; =20 /* Collect diagnostics about available mitigations. */ if ( boot_cpu_data.cpuid_level >=3D 7 ) @@ -401,6 +400,8 @@ static void __init print_details(enum ind_thunk thunk, = uint64_t caps) cpuid_count(7, 2, &tmp, &tmp, &tmp, &_7d2); if ( boot_cpu_data.extended_cpuid_level >=3D 0x80000008 ) cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp); + if ( cpu_has_arch_caps ) + rdmsrl(MSR_ARCH_CAPABILITIES, caps); =20 printk("Speculative mitigation facilities:\n"); =20 @@ -578,7 +579,7 @@ static bool __init check_smt_enabled(void) } =20 /* Calculate whether Retpoline is known-safe on this CPU. */ -static bool __init retpoline_safe(uint64_t caps) +static bool __init retpoline_safe(void) { unsigned int ucode_rev =3D this_cpu(cpu_sig).rev; =20 @@ -596,7 +597,7 @@ static bool __init retpoline_safe(uint64_t caps) * Processors offering Enhanced IBRS are not guarenteed to be * repoline-safe. */ - if ( caps & (ARCH_CAPS_RSBA | ARCH_CAPS_IBRS_ALL) ) + if ( cpu_has_rsba || cpu_has_eibrs ) return false; =20 switch ( boot_cpu_data.x86_model ) @@ -845,7 +846,7 @@ static void __init ibpb_calculations(void) } =20 /* Calculate whether this CPU is vulnerable to L1TF. */ -static __init void l1tf_calculations(uint64_t caps) +static __init void l1tf_calculations(void) { bool hit_default =3D false; =20 @@ -933,7 +934,7 @@ static __init void l1tf_calculations(uint64_t caps) } =20 /* Any processor advertising RDCL_NO should be not vulnerable to L1TF.= */ - if ( caps & ARCH_CAPS_RDCL_NO ) + if ( cpu_has_rdcl_no ) cpu_has_bug_l1tf =3D false; =20 if ( cpu_has_bug_l1tf && hit_default ) @@ -992,7 +993,7 @@ static __init void l1tf_calculations(uint64_t caps) } =20 /* Calculate whether this CPU is vulnerable to MDS. */ -static __init void mds_calculations(uint64_t caps) +static __init void mds_calculations(void) { /* MDS is only known to affect Intel Family 6 processors at this time.= */ if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || @@ -1000,7 +1001,7 @@ static __init void mds_calculations(uint64_t caps) return; =20 /* Any processor advertising MDS_NO should be not vulnerable to MDS. */ - if ( caps & ARCH_CAPS_MDS_NO ) + if ( cpu_has_mds_no ) return; =20 switch ( boot_cpu_data.x86_model ) @@ -1113,10 +1114,6 @@ void __init init_speculation_mitigations(void) enum ind_thunk thunk =3D THUNK_DEFAULT; bool has_spec_ctrl, ibrs =3D false, hw_smt_enabled; bool cpu_has_bug_taa; - uint64_t caps =3D 0; - - if ( cpu_has_arch_caps ) - rdmsrl(MSR_ARCH_CAPABILITIES, caps); =20 hw_smt_enabled =3D check_smt_enabled(); =20 @@ -1163,7 +1160,7 @@ void __init init_speculation_mitigations(void) * On all hardware, we'd like to use retpoline in preference to * IBRS, but only if it is safe on this hardware. */ - if ( retpoline_safe(caps) ) + if ( retpoline_safe() ) thunk =3D THUNK_RETPOLINE; else if ( has_spec_ctrl ) ibrs =3D true; @@ -1392,13 +1389,13 @@ void __init init_speculation_mitigations(void) * threads. Activate this if SMT is enabled, and Xen is using a non-z= ero * MSR_SPEC_CTRL setting. */ - if ( boot_cpu_has(X86_FEATURE_IBRSB) && !(caps & ARCH_CAPS_IBRS_ALL) && + if ( boot_cpu_has(X86_FEATURE_IBRSB) && !cpu_has_eibrs && hw_smt_enabled && default_xen_spec_ctrl ) setup_force_cpu_cap(X86_FEATURE_SC_MSR_IDLE); =20 - xpti_init_default(caps); + xpti_init_default(); =20 - l1tf_calculations(caps); + l1tf_calculations(); =20 /* * By default, enable PV domU L1TF mitigations on all L1TF-vulnerable @@ -1419,7 +1416,7 @@ void __init init_speculation_mitigations(void) if ( !boot_cpu_has(X86_FEATURE_L1D_FLUSH) ) opt_l1d_flush =3D 0; else if ( opt_l1d_flush =3D=3D -1 ) - opt_l1d_flush =3D cpu_has_bug_l1tf && !(caps & ARCH_CAPS_SKIP_L1DF= L); + opt_l1d_flush =3D cpu_has_bug_l1tf && !cpu_has_skip_l1dfl; =20 /* We compile lfence's in by default, and nop them out if requested. */ if ( !opt_branch_harden ) @@ -1442,7 +1439,7 @@ void __init init_speculation_mitigations(void) "enabled. Please assess your configuration and choose an\n" "explicit 'smt=3D' setting. See XSA-273.\n"); =20 - mds_calculations(caps); + mds_calculations(); =20 /* * Parts which enumerate FB_CLEAR are those which are post-MDS_NO and = have @@ -1454,7 +1451,7 @@ void __init init_speculation_mitigations(void) * the return-to-guest path. */ if ( opt_unpriv_mmio ) - opt_fb_clear_mmio =3D caps & ARCH_CAPS_FB_CLEAR; + opt_fb_clear_mmio =3D cpu_has_fb_clear; =20 /* * By default, enable PV and HVM mitigations on MDS-vulnerable hardwar= e. @@ -1484,7 +1481,7 @@ void __init init_speculation_mitigations(void) */ if ( opt_md_clear_pv || opt_md_clear_hvm || opt_fb_clear_mmio ) setup_force_cpu_cap(X86_FEATURE_SC_VERW_IDLE); - opt_md_clear_hvm &=3D !(caps & ARCH_CAPS_SKIP_L1DFL) && !opt_l1d_flush; + opt_md_clear_hvm &=3D !cpu_has_skip_l1dfl && !opt_l1d_flush; =20 /* * Warn the user if they are on MLPDS/MFBDS-vulnerable hardware with HT @@ -1515,8 +1512,7 @@ void __init init_speculation_mitigations(void) * we check both to spot TSX in a microcode/cmdline independent = way. */ cpu_has_bug_taa =3D - (cpu_has_rtm || (caps & ARCH_CAPS_TSX_CTRL)) && - (caps & (ARCH_CAPS_MDS_NO | ARCH_CAPS_TAA_NO)) =3D=3D ARCH_CAPS_MD= S_NO; + (cpu_has_rtm || cpu_has_tsx_ctrl) && cpu_has_mds_no && !cpu_has_ta= a_no; =20 /* * On TAA-affected hardware, disabling TSX is the preferred mitigation= , vs @@ -1535,7 +1531,7 @@ void __init init_speculation_mitigations(void) * plausibly value TSX higher than Hyperthreading...), disable TSX to * mitigate TAA. */ - if ( opt_tsx =3D=3D -1 && cpu_has_bug_taa && (caps & ARCH_CAPS_TSX_CTR= L) && + if ( opt_tsx =3D=3D -1 && cpu_has_bug_taa && cpu_has_tsx_ctrl && ((hw_smt_enabled && opt_smt) || !boot_cpu_has(X86_FEATURE_SC_VERW_IDLE)) ) { @@ -1560,15 +1556,15 @@ void __init init_speculation_mitigations(void) if ( cpu_has_srbds_ctrl ) { if ( opt_srb_lock =3D=3D -1 && !opt_unpriv_mmio && - (caps & (ARCH_CAPS_MDS_NO|ARCH_CAPS_TAA_NO)) =3D=3D ARCH_CAPS= _MDS_NO && - (!cpu_has_hle || ((caps & ARCH_CAPS_TSX_CTRL) && rtm_disabled= )) ) + cpu_has_mds_no && !cpu_has_taa_no && + (!cpu_has_hle || (cpu_has_tsx_ctrl && rtm_disabled)) ) opt_srb_lock =3D 0; =20 set_in_mcu_opt_ctrl(MCU_OPT_CTRL_RNGDS_MITG_DIS, opt_srb_lock ? 0 : MCU_OPT_CTRL_RNGDS_MITG_DIS= ); } =20 - print_details(thunk, caps); + print_details(thunk); =20 /* * If MSR_SPEC_CTRL is available, apply Xen's default setting and disc= ard --=20 2.30.2