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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id s9-20020a5d5109000000b002ffbf2213d4sm14754606wrt.75.2023.05.09.09.43.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 May 2023 09:43:41 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a8d2fb1d-ee88-11ed-b229-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1683650622; x=1686242622; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2enxHJVvB53hhS6w5p4MreN4cLpgSnyXWT9wrZUvS/4=; b=Jx1Y62UZFeAOx2gMKCjK4jBHh3yhgyKAn9n7FuUAvNutUqg8yAeuRofpXYb8vErxfI 7mrXPYxG+D4C8qtZvknk5JZ1buBWqM91LA8CGQylC4OiOQNkJyFM8JFHan2FaHKM8qrS D4S45+nSoit9/DdwrTanwMs6g87mBGlF5IcYU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683650622; x=1686242622; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2enxHJVvB53hhS6w5p4MreN4cLpgSnyXWT9wrZUvS/4=; b=F+RtZctmdlk1u4hnyJaebmVIITPuxovDcCUH9M5PiGIjHzVJw7EtwKmAwU83XB4gCr gv67lLrH4IIwNdMleLU/5Umq13hBN0JARzZmpFVMdzfnK20FgWWdvJzXCvGqFUiAmu0F 7lxRxns8kfYX/WGGxZP8/KRI8Oxr+6Zveqvi2jtRruz9GvAtHZKgh4Vzhe1FW9BJD50z U9cg1MTMQ0FlNGKa8lkYIu7yBpwj5UR6opRa5bBBkjJtJX5YsP4WzTJ8EGDBAeXg9qpP m49XQ7mRPXR0X89DCO2UG62FjtKJcz9g67wytX6YxRGX5mWELFF02gfKtLLnyDXlZKRz LMeA== X-Gm-Message-State: AC+VfDxVHJPam9f7x1Yy0O51mWMYpNhF+7+6Z8QCqLZTQbof7kq6G37A qQwBzninmoSbTx5llR5TlwYsCiZvflXaM9BplII= X-Google-Smtp-Source: ACHHUZ581+1hPFk3uezFqtzRz8gKAsnHQjClnXioOR9gPVCwBkgpowVceLxszo8PH6MPDLUn03qoRg== X-Received: by 2002:a05:600c:2206:b0:3f4:2220:28cc with SMTP id z6-20020a05600c220600b003f4222028ccmr5959782wml.9.1683650622346; Tue, 09 May 2023 09:43:42 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Wei Liu , Anthony PERARD , Juergen Gross , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 1/3] x86: Add AMD's CpuidUserDis bit definitions Date: Tue, 9 May 2023 17:43:34 +0100 Message-Id: <20230509164336.12523-2-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230509164336.12523-1-alejandro.vallejo@cloud.com> References: <20230509164336.12523-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @cloud.com) X-ZM-MESSAGEID: 1683650660693100005 Content-Type: text/plain; charset="utf-8" AMD reports support for CpuidUserDis in CPUID and provides the toggle in HW= CR. This patch adds the positions of both of those bits to both xen and tools. No functional change. Signed-off-by: Alejandro Vallejo Reviewed-by: Jan Beulich --- tools/libs/light/libxl_cpuid.c | 1 + tools/misc/xen-cpuid.c | 2 ++ xen/arch/x86/include/asm/msr-index.h | 1 + xen/include/public/arch-x86/cpufeatureset.h | 1 + 4 files changed, 5 insertions(+) diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c index 5f0bf93810..4d2fab5414 100644 --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -317,6 +317,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *c= puid, const char* str) =20 {"lfence+", 0x80000021, NA, CPUID_REG_EAX, 2, 1}, {"nscb", 0x80000021, NA, CPUID_REG_EAX, 6, 1}, + {"cpuid-user-dis", 0x80000021, NA, CPUID_REG_EAX, 17, 1}, =20 {"maxhvleaf", 0x40000000, NA, CPUID_REG_EAX, 0, 8}, =20 diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index d7efc59d31..8ec143ebc8 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -199,6 +199,8 @@ static const char *const str_e21a[32] =3D { [ 2] =3D "lfence+", [ 6] =3D "nscb", + + /* 16 */ [17] =3D "cpuid-user-dis", }; =20 static const char *const str_7b1[32] =3D diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/as= m/msr-index.h index fa771ed0b5..082fb2e0d9 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -337,6 +337,7 @@ =20 #define MSR_K8_HWCR 0xc0010015 #define K8_HWCR_TSC_FREQ_SEL (1ULL << 24) +#define K8_HWCR_CPUID_USER_DIS (1ULL << 35) =20 #define MSR_K7_FID_VID_CTL 0xc0010041 #define MSR_K7_FID_VID_STATUS 0xc0010042 diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/publ= ic/arch-x86/cpufeatureset.h index 12e3dc80c6..623dcb1bce 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -287,6 +287,7 @@ XEN_CPUFEATURE(AVX_IFMA, 10*32+23) /*A AVX-IFMA In= structions */ /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */ XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializin= g */ XEN_CPUFEATURE(NSCB, 11*32+ 6) /*A Null Selector Clears Bas= e (and limit too) */ +XEN_CPUFEATURE(CPUID_USER_DIS, 11*32+17) /* CPUID disable for non-pr= ivileged software */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */ XEN_CPUFEATURE(INTEL_PPIN, 12*32+ 0) /* Protected Processor Inve= ntory Number */ --=20 2.34.1 From nobody Sun Feb 8 12:32:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id s9-20020a5d5109000000b002ffbf2213d4sm14754606wrt.75.2023.05.09.09.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 May 2023 09:43:42 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a9d017aa-ee88-11ed-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1683650624; x=1686242624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oQyCUxTpPixPBVFBdSiN0k/YI9aqhLZJQE2OAMb3ZSg=; b=XKh1o0IgXOTR8pP6xG5QopyY1l3y18i6SbkyqgaYeApyoLGSwmQqskMhCdfK8PiKlx hZsFMYdruCgUuqpKvRiOHLxtzSm7F6qfb92tbMj9hM/rf5Dg3lGcdNBbPmOqlN87lNNX esDFxd4EnbwvdY1XizIi7/oaISq0xuXxA9EM8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683650624; x=1686242624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oQyCUxTpPixPBVFBdSiN0k/YI9aqhLZJQE2OAMb3ZSg=; b=Yq7+wJ8TLQdz8yR4jjPX/5m+pzg9xShn4d9VRWlBPlN3WTov1LVtDWh1av7vHqPQ4/ OU7ElZe2dwRcOBwxQiV3o2PM7cuJhOm+cZjhg6sxxd5kQXgENCVURtpblbtJtIRr9Fcp 27MSbE9PiIHAsT1GJ9K7iboODimQtQ2YmZ9cHpZs3VVpeLqIpMPEJer4m/DkbaMqGy6L FXNcvcBS99W1l1id79uYCSFBNWvKFF/gQEPq+K1YGO4onu9qOWLw9VJ6fS5kI2E6anlp Utr594ffQ5DqtET5Olm3WTzuAKbhP810X9IpxTtVa0bJheqAtEAYB0/xelj2V/oZHo2F q79g== X-Gm-Message-State: AC+VfDyLlfxcdVFu7QWw61WIt95gR4LVUYQzhJf0M4E4ZfPEnR1mzUaS iyvhGADQYwcZk9Wf8zf4ElyV4vY5ddp5OSQ+lkQ= X-Google-Smtp-Source: ACHHUZ66heKHNtZecnybWt7F3Z5YP/uYyRzYh7uooIzmomVHTOppE0QrYKMEGi9+Efhd8qFzR3KEag== X-Received: by 2002:adf:fa06:0:b0:2fb:600e:55bd with SMTP id m6-20020adffa06000000b002fb600e55bdmr10065258wrr.39.1683650623951; Tue, 09 May 2023 09:43:43 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH v2 2/3] x86: Refactor conditional guard in probe_cpuid_faulting() Date: Tue, 9 May 2023 17:43:35 +0100 Message-Id: <20230509164336.12523-3-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230509164336.12523-1-alejandro.vallejo@cloud.com> References: <20230509164336.12523-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @cloud.com) X-ZM-MESSAGEID: 1683650659561100001 Content-Type: text/plain; charset="utf-8" Move vendor-specific checks to the vendor-specific callers. No functional change. Signed-off-by: Alejandro Vallejo Reviewed-by: Jan Beulich --- v2: * Patch factored out from patch2 of v1 --- xen/arch/x86/cpu/amd.c | 10 +++++++++- xen/arch/x86/cpu/common.c | 11 ----------- xen/arch/x86/cpu/intel.c | 9 ++++++++- 3 files changed, 17 insertions(+), 13 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index caafe44740..899bae7a10 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -271,7 +271,15 @@ static void __init noinline amd_init_levelling(void) { const struct cpuidmask *m =3D NULL; =20 - if (probe_cpuid_faulting()) + /* + * If there's support for CpuidUserDis or CPUID faulting then + * we can skip levelling because CPUID accesses are trapped anyway. + * + * CPUID faulting is an Intel feature analogous to CpuidUserDis, so + * that can only be present when Xen is itself virtualized (because + * it can be emulated) + */ + if (cpu_has_hypervisor && probe_cpuid_faulting()) return; =20 probe_masking_msrs(); diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index edc4db1335..4bfaac4590 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -131,17 +131,6 @@ bool __init probe_cpuid_faulting(void) uint64_t val; int rc; =20 - /* - * Don't bother looking for CPUID faulting if we aren't virtualised on - * AMD or Hygon hardware - it won't be present. Likewise for Fam0F - * Intel hardware. - */ - if (((boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) || - ((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) && - boot_cpu_data.x86 =3D=3D 0xf)) && - !cpu_has_hypervisor) - return false; - if ((rc =3D rdmsr_safe(MSR_INTEL_PLATFORM_INFO, val)) =3D=3D 0) raw_cpu_policy.platform_info.cpuid_faulting =3D val & MSR_PLATFORM_INFO_CPUID_FAULTING; diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 71fc1a1e18..a04414ba1d 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -226,7 +226,14 @@ static void cf_check intel_ctxt_switch_masking(const s= truct vcpu *next) */ static void __init noinline intel_init_levelling(void) { - if (probe_cpuid_faulting()) + /* + * Intel Fam0f is old enough that probing for CPUID faulting support + * introduces spurious #GP(0) when the appropriate MSRs are read, + * so skip it altogether. In the case where Xen is virtualized these + * MSRs may be emulated though, so we allow it in that case. + */ + if ((boot_cpu_data.x86 !=3D 0xf || cpu_has_hypervisor) && + probe_cpuid_faulting()) return; =20 probe_masking_msrs(); --=20 2.34.1 From nobody Sun Feb 8 12:32:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=cloud.com ARC-Seal: i=1; a=rsa-sha256; t=1683650662; cv=none; d=zohomail.com; s=zohoarc; b=BMhdamGFwznbkUINTMGLHfWSWZKLz2gPhsu9JIJ/S5+Ccx9TOe/l7+00Wwa1fZ2c6B/BXll2d9/nVVLYD2fHxlMOTcMQbCzueeX2TVJLVys4ZL1NheQJr3LbYnCSYAFiY1n/lR/lm/Z7FMf0sp013XmnQEWRFM/Rd8oE7ix2XaY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683650662; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=16GgcLP2BBqsFeayUECe7ljf4/vLwO1azevfRpDiAnE=; b=QNdirI8wLdq/0TacXV7ztFETOm9Mb6WTywiNza3otwTsm2yJPUckNsFIpAmQdBkBXBQ1pt9nylgk5NHhfGB6nLklvtwiSBL3PH1imEKY/3tXkWjbWKqEOON7vlISb6tFwcrovmqUnEvyS8tUoIbwk/J8PdZCMoNuLB6/UjF2TRg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1683650662113608.7174156287573; Tue, 9 May 2023 09:44:22 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.532378.828568 (Exim 4.92) (envelope-from ) id 1pwQRK-0002cm-0Y; Tue, 09 May 2023 16:43:50 +0000 Received: by outflank-mailman (output) from mailman id 532378.828568; Tue, 09 May 2023 16:43:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pwQRJ-0002cd-TN; Tue, 09 May 2023 16:43:49 +0000 Received: by outflank-mailman (input) for mailman id 532378; Tue, 09 May 2023 16:43:48 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pwQRI-0002Ky-DQ for xen-devel@lists.xenproject.org; Tue, 09 May 2023 16:43:48 +0000 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [2a00:1450:4864:20::436]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id aabb4d0a-ee88-11ed-8611-37d641c3527e; Tue, 09 May 2023 18:43:46 +0200 (CEST) Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-3064099f9b6so3915731f8f.1 for ; Tue, 09 May 2023 09:43:46 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id s9-20020a5d5109000000b002ffbf2213d4sm14754606wrt.75.2023.05.09.09.43.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 May 2023 09:43:44 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: aabb4d0a-ee88-11ed-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1683650625; x=1686242625; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=16GgcLP2BBqsFeayUECe7ljf4/vLwO1azevfRpDiAnE=; b=HuBJiOT6QALlrn9nb56NQbzi6cla2ddOsWT7xW5nGmKpcyzIYNsdiPxKyWV9v1KN4B /uIHJ7Xy/LdlgRK3eynfeh8W3+AQGlV/DVg0JCRSqLnHxZqU4FpCzVgbw242PvnRAFrb KZv11Jspf0AuzoLRYVG11tRamYzXLmkAKH/E8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683650625; x=1686242625; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=16GgcLP2BBqsFeayUECe7ljf4/vLwO1azevfRpDiAnE=; b=Qe/kYIS/nk4zN18OEe5bPE3UVMbbzCbwoaeuyPGvzySAp3ncE6zy/6k2xNL1Kp9pNc Nx3ZcYLAKr6+0ne2bchZYI4JN4BIS4zgoCEwweD1Qz0VnMZT/rLBGrLGXVrzhOaUTF7P xDRK/eo4d1jaAujPuko+JE1jJo0ROxDqVlEUCCVBPRievF5Sr+ns6k3Q2/jExK7T6mmj 87BNNRjVN1Xz+5LLUF8qzX19ldiXo5oBH43uuJOSibZAdf/g/FbTlhBbUDlYeDJIs7n6 BqQ5fBlkAdrjMtJPSBSbB5s8at0AHvDND1iX12oNse57p3B/dyg0TvCHenGO8hCHz2Cr lXNA== X-Gm-Message-State: AC+VfDwvdx8U8E18cBtw9bqGMkmX9WxVLoCW19jJVHwOLdPkrqgM2GVg WMtSKKlDhionSoW90SrKDSBHu3dMoQtX09Q4oK4= X-Google-Smtp-Source: ACHHUZ7NMADEFOOpRrJnC2oe43bnCiHaWZNRSN6qIYJRojhJXSRulKGcG6OnzfawBJdlc/o7zsGVEg== X-Received: by 2002:a5d:5701:0:b0:307:2ba7:c617 with SMTP id a1-20020a5d5701000000b003072ba7c617mr10532538wrv.52.1683650625641; Tue, 09 May 2023 09:43:45 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH v2 3/3] x86: Add support for CpuidUserDis Date: Tue, 9 May 2023 17:43:36 +0100 Message-Id: <20230509164336.12523-4-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230509164336.12523-1-alejandro.vallejo@cloud.com> References: <20230509164336.12523-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @cloud.com) X-ZM-MESSAGEID: 1683650662677100007 Content-Type: text/plain; charset="utf-8" Because CpuIdUserDis is reported in CPUID itself, the extended leaf containing that bit must be retrieved before calling c_early_init() Signed-off-by: Alejandro Vallejo --- v2: * Style fixes * MSR index inlined in rdmsr/wrmsr * Swapped Intel's conditional guard so typically true condition goes first * Factored the vendor-specific non functional changes into another patch --- xen/arch/x86/cpu/amd.c | 20 ++++++++++++++++- xen/arch/x86/cpu/common.c | 40 +++++++++++++++++++++++----------- xen/arch/x86/cpu/intel.c | 5 ++++- xen/arch/x86/include/asm/amd.h | 1 + 4 files changed, 51 insertions(+), 15 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 899bae7a10..cc9c89fd19 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -279,8 +279,12 @@ static void __init noinline amd_init_levelling(void) * that can only be present when Xen is itself virtualized (because * it can be emulated) */ - if (cpu_has_hypervisor && probe_cpuid_faulting()) + if ((cpu_has_hypervisor && probe_cpuid_faulting()) || + boot_cpu_has(X86_FEATURE_CPUID_USER_DIS)) { + expected_levelling_cap |=3D LCAP_faulting; + levelling_caps |=3D LCAP_faulting; return; + } =20 probe_masking_msrs(); =20 @@ -371,6 +375,20 @@ static void __init noinline amd_init_levelling(void) ctxt_switch_masking =3D amd_ctxt_switch_masking; } =20 +void amd_set_cpuid_user_dis(bool enable) +{ + const uint64_t bit =3D K8_HWCR_CPUID_USER_DIS; + uint64_t val; + + rdmsrl(MSR_K8_HWCR, val); + + if (!!(val & bit) =3D=3D enable) + return; + + val ^=3D bit; + wrmsrl(MSR_K8_HWCR, val); +} + /* * Check for the presence of an AMD erratum. Arguments are defined in amd.= h=20 * for each known erratum. Return 1 if erratum is found. diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 4bfaac4590..9bbb385db4 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -4,6 +4,7 @@ #include #include =20 +#include #include #include #include @@ -144,8 +145,6 @@ bool __init probe_cpuid_faulting(void) return false; } =20 - expected_levelling_cap |=3D LCAP_faulting; - levelling_caps |=3D LCAP_faulting; setup_force_cpu_cap(X86_FEATURE_CPUID_FAULTING); =20 return true; @@ -168,8 +167,10 @@ static void set_cpuid_faulting(bool enable) void ctxt_switch_levelling(const struct vcpu *next) { const struct domain *nextd =3D next ? next->domain : NULL; + bool enable_cpuid_faulting; =20 - if (cpu_has_cpuid_faulting) { + if (cpu_has_cpuid_faulting || + boot_cpu_has(X86_FEATURE_CPUID_USER_DIS)) { /* * No need to alter the faulting setting if we are switching * to idle; it won't affect any code running in idle context. @@ -190,12 +191,18 @@ void ctxt_switch_levelling(const struct vcpu *next) * an interim escape hatch in the form of * `dom0=3Dno-cpuid-faulting` to restore the older behaviour. */ - set_cpuid_faulting(nextd && (opt_dom0_cpuid_faulting || - !is_control_domain(nextd) || - !is_pv_domain(nextd)) && - (is_pv_domain(nextd) || - next->arch.msrs-> - misc_features_enables.cpuid_faulting)); + enable_cpuid_faulting =3D nextd && (opt_dom0_cpuid_faulting || + !is_control_domain(nextd) || + !is_pv_domain(nextd)) && + (is_pv_domain(nextd) || + next->arch.msrs-> + misc_features_enables.cpuid_faulting); + + if (cpu_has_cpuid_faulting) + set_cpuid_faulting(enable_cpuid_faulting); + else + amd_set_cpuid_user_dis(enable_cpuid_faulting); + return; } =20 @@ -404,6 +411,17 @@ static void generic_identify(struct cpuinfo_x86 *c) c->apicid =3D phys_pkg_id((ebx >> 24) & 0xFF, 0); c->phys_proc_id =3D c->apicid; =20 + eax =3D cpuid_eax(0x80000000); + if ((eax >> 16) =3D=3D 0x8000) + c->extended_cpuid_level =3D eax; + + /* + * These AMD-defined flags are out of place, but we need + * them early for the CPUID faulting probe code + */ + if (c->extended_cpuid_level >=3D 0x80000021) + c->x86_capability[FEATURESET_e21a] =3D cpuid_eax(0x80000021); + if (this_cpu->c_early_init) this_cpu->c_early_init(c); =20 @@ -420,10 +438,6 @@ static void generic_identify(struct cpuinfo_x86 *c) (cpuid_ecx(CPUID_PM_LEAF) & CPUID6_ECX_APERFMPERF_CAPABILITY) ) __set_bit(X86_FEATURE_APERFMPERF, c->x86_capability); =20 - eax =3D cpuid_eax(0x80000000); - if ((eax >> 16) =3D=3D 0x8000) - c->extended_cpuid_level =3D eax; - /* AMD-defined flags: level 0x80000001 */ if (c->extended_cpuid_level >=3D 0x80000001) cpuid(0x80000001, &tmp, &tmp, diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index a04414ba1d..bbe7b7d1ce 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -233,8 +233,11 @@ static void __init noinline intel_init_levelling(void) * MSRs may be emulated though, so we allow it in that case. */ if ((boot_cpu_data.x86 !=3D 0xf || cpu_has_hypervisor) && - probe_cpuid_faulting()) + probe_cpuid_faulting()) { + expected_levelling_cap |=3D LCAP_faulting; + levelling_caps |=3D LCAP_faulting; return; + } =20 probe_masking_msrs(); =20 diff --git a/xen/arch/x86/include/asm/amd.h b/xen/arch/x86/include/asm/amd.h index a975d3de26..09ee52dc1c 100644 --- a/xen/arch/x86/include/asm/amd.h +++ b/xen/arch/x86/include/asm/amd.h @@ -155,5 +155,6 @@ extern bool amd_legacy_ssbd; extern bool amd_virt_spec_ctrl; bool amd_setup_legacy_ssbd(void); void amd_set_legacy_ssbd(bool enable); +void amd_set_cpuid_user_dis(bool enable); =20 #endif /* __AMD_H__ */ --=20 2.34.1