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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v6 11/12] xen/arm: p2m: Use the pa_range_info table to support ARM_32 and ARM_64 Date: Fri, 28 Apr 2023 18:55:42 +0100 Message-ID: <20230428175543.11902-12-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230428175543.11902-1-ayan.kumar.halder@amd.com> References: <20230428175543.11902-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT021:EE_|SA1PR12MB7038:EE_ X-MS-Office365-Filtering-Correlation-Id: e39507f3-398e-404c-afc2-08db481247da X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OamGLiBcpppl2eYNyW0nRJ0izW8tJKjPAKcRXc8wXuaaQ+vizWsXGPhaF0m2LqpktaDvVTK2q1TTMgIWRFSElf2LlgQtefKpqjwbu+lleRp9NCr+x6lHNpW8oZ1E2hrmsuTB4jOtUgCZCREEABkCzMJKvQChcSATqP2N4PSvY/mtHHyk2CBn+gCO364xwOFtKadszIQAF3vLxHvIasD5WTnR6FKi8QFFmmkDMZIIBzRH5paabVGhriSQ4QTXp5QhqiolbsZOyQB1UxfOUwOomz9YLRHSd6QTY25UVq/VOj55hZ/icLXP76kDkQNLC91A48hcYswwh6jNIZhw1CkfDZWwr4ssBuAWQX8NrQ5leC4yrFoIq1tgSVtAkiipa5ZGI0zUD47OLrViau/CxaKO+bgdc8Q6neNda6y0yHQGV0UVBSisNpPQs14r0Dfw2nD2Ymkl+wwZeAiVCvt9n6oitTYAqE5Uf6He8pRSIG1YiiucTwv0HA4N6FcxiYxbXKPSnqKFf0hbq7xqp7qHqR/d7SmH+LQFTETMXidb591WT98IvCSfIva2wuEWap+yiuLW5iPI50uGVWDvg2+2onJLCaBJdxAUJt1yiLyJWDp3iJ9BSiBotW/acJl/qUkzvJ3YthhEfTsCV8mktE4r7s1y9hnr4UqXm8TApmXORraOZNX+Jeqt+IQSG+OU/RkKZzIxux2C8NDhGzAFIbqoifdDv4TbjpcWv3CwpJSEbtAUHZs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(39860400002)(346002)(136003)(396003)(451199021)(40470700004)(36840700001)(46966006)(40480700001)(7416002)(81166007)(70206006)(6916009)(40460700003)(70586007)(478600001)(8676002)(8936002)(5660300002)(54906003)(4326008)(82740400003)(316002)(356005)(336012)(83380400001)(426003)(6666004)(186003)(2616005)(36860700001)(1076003)(26005)(47076005)(82310400005)(36756003)(86362001)(103116003)(2906002)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2023 17:59:15.4713 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e39507f3-398e-404c-afc2-08db481247da X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7038 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1682704783128100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Restructure the code so that one can use pa_range_info[] table for both ARM_32 as well as ARM_64. Also, removed the hardcoding for P2M_ROOT_ORDER and P2M_ROOT_LEVEL as p2m_root_order can be obtained from the pa_range_info[].root_order and p2m_root_level can be obtained from pa_range_info[].sl0. Refer ARM DDI 0406C.d ID040418, B3-1345, "Use of concatenated first-level translation tables ...However, a 40-bit input address range with a translation granularity of = 4KB requires a total of 28 bits of address resolution. Therefore, a stage 2 translation that supports a 40-bit input address range requires two concate= nated first-level translation tables,..." Thus, root-order is 1 for 40-bit IPA on ARM_32. Refer ARM DDI 0406C.d ID040418, B3-1348, "Determining the required first lookup level for stage 2 translations For a stage 2 translation, the output address range from the stage 1 translations determines the required input address range for the stage 2 translation. The permitted values of VTCR.SL0 are: 0b00 Stage 2 translation lookup must start at the second level. 0b01 Stage 2 translation lookup must start at the first level. VTCR.T0SZ must indicate the required input address range. The size of the i= nput address region is 2^(32-T0SZ) bytes." Thus VTCR.SL0 =3D 1 (maximum value) and VTCR.T0SZ =3D -8 when the size of i= nput address region is 2^40 bytes. Thus, pa_range_info[].t0sz =3D 1 (VTCR.S) | 8 (VTCR.T0SZ) ie 11000b which i= s 24. Signed-off-by: Ayan Kumar Halder --- Changes from - v3 - 1. New patch introduced in v4. 2. Restructure the code such that pa_range_info[] is used both by ARM_32 as well as ARM_64. v4 - 1. Removed the hardcoded definitions of P2M_ROOT_ORDER and P2M_ROOT_LE= VEL. The reason being root_order will not be always 1 (See the next patch). 2. Updated the commit message to explain t0sz, sl0 and root_order values for 32-bit IPA on Arm32. 3. Some sanity fixes. v5 - pa_range_info is indexed by system_cpuinfo.mm64.pa_range. ie when PARange is 0, the PA size is 32, 1 -> 36 and so on. So pa_range_info[]= has been updated accordingly. For ARM_32 pa_range_info[0] =3D 0 and pa_range_info[1] =3D 0 as we do not s= upport 32-bit, 36-bit physical address range yet. xen/arch/arm/include/asm/p2m.h | 8 +------- xen/arch/arm/p2m.c | 32 ++++++++++++++++++-------------- 2 files changed, 19 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index f67e9ddc72..4ddd4643d7 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -14,16 +14,10 @@ /* Holds the bit size of IPAs in p2m tables. */ extern unsigned int p2m_ipa_bits; =20 -#ifdef CONFIG_ARM_64 extern unsigned int p2m_root_order; extern unsigned int p2m_root_level; -#define P2M_ROOT_ORDER p2m_root_order +#define P2M_ROOT_ORDER p2m_root_order #define P2M_ROOT_LEVEL p2m_root_level -#else -/* First level P2M is always 2 consecutive pages */ -#define P2M_ROOT_ORDER 1 -#define P2M_ROOT_LEVEL 1 -#endif =20 struct domain; =20 diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 418997843d..1fe3cccf46 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -19,9 +19,9 @@ =20 #define INVALID_VMID 0 /* VMID 0 is reserved */ =20 -#ifdef CONFIG_ARM_64 unsigned int __read_mostly p2m_root_order; unsigned int __read_mostly p2m_root_level; +#ifdef CONFIG_ARM_64 static unsigned int __read_mostly max_vmid =3D MAX_VMID_8_BIT; /* VMID is by default 8 bit width on AArch64 */ #define MAX_VMID max_vmid @@ -2247,16 +2247,6 @@ void __init setup_virt_paging(void) /* Setup Stage 2 address translation */ register_t val =3D VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0_WB= WA; =20 -#ifdef CONFIG_ARM_32 - if ( p2m_ipa_bits < 40 ) - panic("P2M: Not able to support %u-bit IPA at the moment\n", - p2m_ipa_bits); - - printk("P2M: 40-bit IPA\n"); - p2m_ipa_bits =3D 40; - val |=3D VTCR_T0SZ(0x18); /* 40 bit IPA */ - val |=3D VTCR_SL0(0x1); /* P2M starts at first level */ -#else /* CONFIG_ARM_64 */ static const struct { unsigned int pabits; /* Physical Address Size */ unsigned int t0sz; /* Desired T0SZ, minimum in comment */ @@ -2265,19 +2255,26 @@ void __init setup_virt_paging(void) } pa_range_info[] __initconst =3D { /* T0SZ minimum and SL0 maximum from ARM DDI 0487H.a Table D5-6 */ /* PA size, t0sz(min), root-order, sl0(max) */ + [2] =3D { 40, 24/*24*/, 1, 1 }, +#ifdef CONFIG_ARM_64 [0] =3D { 32, 32/*32*/, 0, 1 }, [1] =3D { 36, 28/*28*/, 0, 1 }, - [2] =3D { 40, 24/*24*/, 1, 1 }, [3] =3D { 42, 22/*22*/, 3, 1 }, [4] =3D { 44, 20/*20*/, 0, 2 }, [5] =3D { 48, 16/*16*/, 0, 2 }, [6] =3D { 52, 12/*12*/, 4, 2 }, [7] =3D { 0 } /* Invalid */ +#else + [0] =3D { 0 }, /* Invalid */ + [1] =3D { 0 }, /* Invalid */ + [3] =3D { 0 } /* Invalid */ +#endif }; =20 unsigned int i; unsigned int pa_range =3D 0x10; /* Larger than any possible value */ =20 +#ifdef CONFIG_ARM_64 /* * Restrict "p2m_ipa_bits" if needed. As P2M table is always configured * with IPA bits =3D=3D PA bits, compare against "pabits". @@ -2291,6 +2288,9 @@ void __init setup_virt_paging(void) */ if ( system_cpuinfo.mm64.vmid_bits =3D=3D MM64_VMID_16_BITS_SUPPORT ) max_vmid =3D MAX_VMID_16_BIT; +#else + p2m_ipa_bits =3D PADDR_BITS; +#endif =20 /* Choose suitable "pa_range" according to the resulted "p2m_ipa_bits"= . */ for ( i =3D 0; i < ARRAY_SIZE(pa_range_info); i++ ) @@ -2306,24 +2306,28 @@ void __init setup_virt_paging(void) if ( pa_range >=3D ARRAY_SIZE(pa_range_info) || !pa_range_info[pa_rang= e].pabits ) panic("Unknown encoding of ID_AA64MMFR0_EL1.PARange %x\n", pa_rang= e); =20 +#ifdef CONFIG_ARM_64 val |=3D VTCR_PS(pa_range); val |=3D VTCR_TG0_4K; =20 /* Set the VS bit only if 16 bit VMID is supported. */ if ( MAX_VMID =3D=3D MAX_VMID_16_BIT ) val |=3D VTCR_VS; + + p2m_ipa_bits =3D 64 - pa_range_info[pa_range].t0sz; +#endif + val |=3D VTCR_SL0(pa_range_info[pa_range].sl0); val |=3D VTCR_T0SZ(pa_range_info[pa_range].t0sz); =20 p2m_root_order =3D pa_range_info[pa_range].root_order; p2m_root_level =3D 2 - pa_range_info[pa_range].sl0; - p2m_ipa_bits =3D 64 - pa_range_info[pa_range].t0sz; =20 printk("P2M: %d-bit IPA with %d-bit PA and %d-bit VMID\n", p2m_ipa_bits, pa_range_info[pa_range].pabits, ( MAX_VMID =3D=3D MAX_VMID_16_BIT ) ? 16 : 8); -#endif + printk("P2M: %d levels with order-%d root, VTCR 0x%"PRIregister"\n", 4 - P2M_ROOT_LEVEL, P2M_ROOT_ORDER, val); =20 --=20 2.17.1