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bh=rTjpNh+BHfToII30u7IVf5AGDUbfYB8YKJohyCLK1pQ=; b=tEhm6AW4eQRfV6ho0FbQogVzJddsBYsVAdmf7jk04n65gm1+Dv9KoEUfmRPVHLBc5w2GCibGKHR1RPLtukblXNq6vQ2vSNg13Qq0EAu1j/fOGYuLINUdVaWbFLUZvZhHJNgkQYIdauvVEWWyue2c+4ecCqu4k6QFoTEqlT8QPDU= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v5 05/10] xen/arm: Introduce choice to enable 64/32 bit physical addressing Date: Thu, 13 Apr 2023 18:37:30 +0100 Message-ID: <20230413173735.48387-6-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413173735.48387-1-ayan.kumar.halder@amd.com> References: <20230413173735.48387-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT022:EE_|MN0PR12MB5931:EE_ X-MS-Office365-Filtering-Correlation-Id: cbdf1f5b-395a-4866-7162-08db3c45dafd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:38:12.7041 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cbdf1f5b-395a-4866-7162-08db3c45dafd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5931 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1681407515832100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Arm based hardware platforms which does not support LPAE (eg Cortex-R52), uses 32 bit physical addresses. Also, users may choose to use 32 bits to represent physical addresses for optimization. To support the above use cases, we have introduced arch independent configs to choose if the physical address can be represented using 32 bits (PHYS_ADDR_T_32) or 64 bits (!PHYS_ADDR_T_32). For now only ARM_32 provides support to enable 32 bit physical addressing. When PHYS_ADDR_T_32 is defined, PADDR_BITS is set to 32. When PHYS_ADDR_T_32 is not defined for ARM_32, PADDR_BITS is set to 40. When PHYS_ADDR_T_32 is not defined for ARM_64, PADDR_BITS is set to 48. The last two are same as the current configuration used today on Xen. PADDR_BITS is also set to 48 when ARM_64 is defined. The reason being the choice to select ARM_PA_BITS_32/ARM_PA_BITS_40/ARM_PA_BITS_48 is currently allowed when ARM_32 is defined. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - 1. Extracted from "[XEN v1 8/9] xen/arm: Other adaptations required to= support 32bit paddr". v2 - 1. Introduced Kconfig choice. ARM_64 can select PHYS_ADDR_64 only wher= eas ARM_32 can select PHYS_ADDR_32 or PHYS_ADDR_64. 2. For CONFIG_ARM_PA_32, paddr_t is defined as 'unsigned long'.=20 v3 - 1. Allow user to define PADDR_BITS by selecting different config optio= ns ARM_PA_BITS_32, ARM_PA_BITS_40 and ARM_PA_BITS_48. 2. Add the choice under "Architecture Features". v4 - 1. Removed PHYS_ADDR_T_64 as !PHYS_ADDR_T_32 means PHYS_ADDR_T_32. xen/arch/Kconfig | 3 +++ xen/arch/arm/Kconfig | 37 ++++++++++++++++++++++++++-- xen/arch/arm/include/asm/page-bits.h | 6 +---- xen/arch/arm/include/asm/types.h | 6 +++++ xen/arch/arm/mm.c | 5 ++++ 5 files changed, 50 insertions(+), 7 deletions(-) diff --git a/xen/arch/Kconfig b/xen/arch/Kconfig index 7028f7b74f..67ba38f32f 100644 --- a/xen/arch/Kconfig +++ b/xen/arch/Kconfig @@ -1,6 +1,9 @@ config 64BIT bool =20 +config PHYS_ADDR_T_32 + bool + config NR_CPUS int "Maximum number of CPUs" range 1 4095 diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 239d3aed3c..3f6e13e475 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -19,13 +19,46 @@ config ARM select HAS_PMAP select IOMMU_FORCE_PT_SHARE =20 +menu "Architecture Features" + +choice + prompt "Physical address space size" if ARM_32 + default ARM_PA_BITS_48 if ARM_64 + default ARM_PA_BITS_40 if ARM_32 + help + User can choose to represent the width of physical address. This can + sometimes help in optimizing the size of image when user chooses a + smaller size to represent physical address. + +config ARM_PA_BITS_32 + bool "32-bit" + help + On platforms where any physical address can be represented within 32 bi= ts, + user should choose this option. This will help is reduced size of the + binary. + select PHYS_ADDR_T_32 + depends on ARM_32 + +config ARM_PA_BITS_40 + bool "40-bit" + depends on ARM_32 + +config ARM_PA_BITS_48 + bool "40-bit" + depends on ARM_48 +endchoice + +config PADDR_BITS + int + default 32 if ARM_PA_BITS_32 + default 40 if ARM_PA_BITS_40 + default 48 if ARM_PA_BITS_48 || ARM_64 + config ARCH_DEFCONFIG string default "arch/arm/configs/arm32_defconfig" if ARM_32 default "arch/arm/configs/arm64_defconfig" if ARM_64 =20 -menu "Architecture Features" - source "arch/Kconfig" =20 config ACPI diff --git a/xen/arch/arm/include/asm/page-bits.h b/xen/arch/arm/include/as= m/page-bits.h index 5d6477e599..deb381ceeb 100644 --- a/xen/arch/arm/include/asm/page-bits.h +++ b/xen/arch/arm/include/asm/page-bits.h @@ -3,10 +3,6 @@ =20 #define PAGE_SHIFT 12 =20 -#ifdef CONFIG_ARM_64 -#define PADDR_BITS 48 -#else -#define PADDR_BITS 40 -#endif +#define PADDR_BITS CONFIG_PADDR_BITS =20 #endif /* __ARM_PAGE_SHIFT_H__ */ diff --git a/xen/arch/arm/include/asm/types.h b/xen/arch/arm/include/asm/ty= pes.h index e218ed77bd..e3cfbbb060 100644 --- a/xen/arch/arm/include/asm/types.h +++ b/xen/arch/arm/include/asm/types.h @@ -34,9 +34,15 @@ typedef signed long long s64; typedef unsigned long long u64; typedef u32 vaddr_t; #define PRIvaddr PRIx32 +#if defined(CONFIG_PHYS_ADDR_T_32) +typedef unsigned long paddr_t; +#define INVALID_PADDR (~0UL) +#define PRIpaddr "08lx" +#else typedef u64 paddr_t; #define INVALID_PADDR (~0ULL) #define PRIpaddr "016llx" +#endif typedef u32 register_t; #define PRIregister "08x" #elif defined (CONFIG_ARM_64) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index b99806af99..6dc37be97e 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -690,6 +690,11 @@ void __init setup_frametable_mappings(paddr_t ps, padd= r_t pe) const unsigned long mapping_size =3D frametable_size < MB(32) ? MB(2) = : MB(32); int rc; =20 + /* + * The size of paddr_t should be sufficient for the complete range of + * physical address. + */ + BUILD_BUG_ON((sizeof(paddr_t) * 8) < PADDR_BITS); BUILD_BUG_ON(sizeof(struct page_info) !=3D PAGE_INFO_SIZE); =20 if ( frametable_size > FRAMETABLE_SIZE ) --=20 2.17.1