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bh=Vf1B+8bx5vatlGHL4Tv5xbYFLO09J4Ep2zXFRUGljAc=; b=5C7jYlvjlYl3IJJ9QSCqkQZXNAJFN3WP974TtsnanagY2sHy9yTJynyz6WIJcbG5Shu+TzJovEPy2qjSlAiOzyMP0HDGcVDSI48gCWQpIrwkV5OAxk+RRNVsz5Ejj6f81tkwg+RwyTxWyvta0txWSEw4l9gblUUmXCynWsUmgfE= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v5 10/10] xen/arm: p2m: Enable support for 32bit IPA for ARM_32 Date: Thu, 13 Apr 2023 18:37:35 +0100 Message-ID: <20230413173735.48387-11-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413173735.48387-1-ayan.kumar.halder@amd.com> References: <20230413173735.48387-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT089:EE_|SA1PR12MB5613:EE_ X-MS-Office365-Filtering-Correlation-Id: 963d6794-6a95-4b08-355b-08db3c45edca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:38:44.2105 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 963d6794-6a95-4b08-355b-08db3c45edca X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT089.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5613 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1681407568949100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refer ARM DDI 0406C.d ID040418, B3-1345, "A stage 2 translation with an input address range of 31-34 bits can start the translation either: - With a first-level lookup, accessing a first-level translation table with 2-16 entries. - With a second-level lookup, accessing a set of concatenated second-level translation tables" Thus, for 32 bit IPA, there will be no concatenated root level tables. So, the root-order is 0. Also, Refer ARM DDI 0406C.d ID040418, B3-1348 "Determining the required first lookup level for stage 2 translations For a stage 2 translation, the output address range from the stage 1 translations determines the required input address range for the stage 2 translation. The permitted values of VTCR.SL0 are: 0b00 Stage 2 translation lookup must start at the second level. 0b01 Stage 2 translation lookup must start at the first level. VTCR.T0SZ must indicate the required input address range. The size of the input address region is 2^(32-T0SZ) bytes." Thus VTCR.SL0 =3D 1 (maximum value) and VTCR.T0SZ =3D 0 when the size of input address region is 2^32 bytes. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - New patch. v2 - 1. Added Ack. v3 - 1. Dropped Ack.=20 2. Rebased the patch based on the previous change. v4 - 1. t0sz is 0 for 32-bit IPA on Arm32. 2. Updated the commit message to explain t0sz, sl0 and root_order. xen/arch/arm/p2m.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 4583658f92..746b6553e5 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -2283,7 +2283,8 @@ void __init setup_virt_paging(void) [6] =3D { 52, 12/*12*/, 4, 2 }, [7] =3D { 0 } /* Invalid */ #else - [1] =3D { 0 } /* Invalid */ + [1] =3D { 32, 0/*0*/, 0, 1 }, + [2] =3D { 0 } /* Invalid */ #endif }; =20 --=20 2.17.1